1 /*
2 * Copyright (c) 2024 EXALT Technologies.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/drivers/i3c.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #ifdef CONFIG_I3C_STM32_DMA
15 #include <zephyr/drivers/dma/dma_stm32.h>
16 #include <zephyr/drivers/dma.h>
17 #endif
18 #include <zephyr/pm/policy.h>
19 #include <zephyr/pm/device.h>
20 #include <zephyr/pm/device_runtime.h>
21 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
22 #include <zephyr/logging/log.h>
23
24 #include <stm32_ll_i3c.h>
25 #include <stm32_ll_bus.h>
26 #include <stm32_ll_rcc.h>
27 #include <stm32_ll_system.h>
28 #include <stm32_ll_cortex.h>
29
30 LOG_MODULE_REGISTER(i3c_stm32, CONFIG_I3C_LOG_LEVEL);
31
32 #define DT_DRV_COMPAT st_stm32_i3c
33
34 #define STM32_I3C_SCLH_I2C_MIN_FM_NS 600ull
35 #define STM32_I3C_SCLH_I2C_MIN_FMP_NS 260ull
36 #define STM32_I3C_SCLL_OD_MIN_FM_NS 1320ull
37 #define STM32_I3C_SCLL_OD_MIN_FMP_NS 500ull
38 #define STM32_I3C_SCLL_OD_MIN_I3C_NS 200ull
39
40 #define STM32_I3C_SCLL_PP_MIN_NS 32ull
41 #define STM32_I3C_SCLH_I3C_MIN_NS 32ull
42
43 #define STM32_I3C_TBUF_FMP_MIN_NS 500.0
44 #define STM32_I3C_TBUF_FM_MIN_NS 1300.0
45 #define STM32_I3C_TCAS_MIN_NS 38.4
46
47 #define STM32_I3C_TRANSFER_TIMEOUT K_MSEC(100)
48
49 #ifdef CONFIG_I3C_STM32_DMA
50 K_HEAP_DEFINE(stm32_i3c_fifo_heap, CONFIG_I3C_STM32_DMA_FIFO_HEAP_SIZE);
51 #endif
52
53 typedef void (*irq_config_func_t)(const struct device *port);
54
55 enum i3c_stm32_sf_state {
56 STM32_I3C_SF_DAA, /* Dynamic addressing state */
57 STM32_I3C_SF_CCC, /* First part of CCC command state*/
58 STM32_I3C_SF_CCC_P2, /* Second part of CCC command state (used for direct commands)*/
59 STM32_I3C_SF, /* Private msg state */
60 STM32_I2C_SF, /* I2C legacy msg state */
61 STM32_I3C_SF_IDLE, /* Idle bus state */
62 STM32_I3C_SF_ERR, /* Error state */
63 STM32_I3C_SF_INVAL, /* Invalid state */
64 };
65
66 enum i3c_stm32_msg_state {
67 STM32_I3C_MSG_DAA, /* Dynamic addressing state */
68 STM32_I3C_MSG_CCC, /* First part of CCC command state*/
69 STM32_I3C_MSG_CCC_P2, /* Second part of CCC command state (used for direct commands)*/
70 STM32_I3C_MSG, /* Private msg state */
71 STM32_I3C_MSG_IDLE, /* Idle bus state */
72 STM32_I3C_MSG_ERR, /* Error state */
73 STM32_I3C_MSG_INVAL, /* Invalid state */
74 };
75
76 #ifdef CONFIG_I3C_STM32_DMA
77 struct i3c_stm32_dma_stream {
78 const struct device *dma_dev;
79 uint32_t dma_channel;
80 struct dma_config dma_cfg;
81 uint8_t priority;
82 bool src_addr_increment;
83 bool dst_addr_increment;
84 int fifo_threshold;
85 struct dma_block_config blk_cfg;
86 };
87 #endif
88
89 /* Struct to hold the information about the current message on the bus */
90 struct i3c_stm32_msg {
91 uint8_t target_addr; /* Current target xfer address */
92 struct i3c_msg *i3c_msg_ptr; /* Pointer to the current private message to send on the bus */
93 struct i3c_msg *i3c_msg_ctrl_ptr; /* Pointer to the private message that will be used by the
94 * control FIFO
95 */
96 struct i3c_msg *i3c_msg_status_ptr; /* Pointer to the private message that will be used by
97 * the status FIFO
98 */
99 struct i2c_msg *i2c_msg_ptr; /* Pointer to the current legacy message to send on the bus */
100 struct i2c_msg *i2c_msg_ctrl_ptr; /* Pointer to the I2C legavy message that will be used by
101 * the control FIFO
102 */
103 size_t num_msgs; /* Number of messages */
104 size_t ctrl_msg_idx; /* Current control message index */
105 size_t status_msg_idx; /* Current status message index */
106 size_t xfer_msg_idx; /* Current trasnfer message index */
107 size_t xfer_offset; /* Current message transfer offset */
108 uint32_t msg_type; /* Either LL_I3C_CONTROLLER_MTYPE_PRIVATE or
109 * LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C
110 */
111 };
112
113 struct i3c_stm32_config {
114 struct i3c_driver_config drv_cfg; /* I3C driver config */
115 I3C_TypeDef *i3c; /* Pointer to I3C module base addr */
116 irq_config_func_t irq_config_func; /* IRQ config function */
117 const struct stm32_pclken *pclken; /* Pointer to peripheral clock configuration */
118 const struct pinctrl_dev_config *pcfg; /* Pointer to pin control configuration */
119 };
120
121 struct i3c_stm32_data {
122 struct i3c_driver_data drv_data; /* I3C driver data */
123 enum i3c_stm32_msg_state msg_state; /* Current I3C bus state */
124 enum i3c_stm32_sf_state sf_state; /* Current I3C status FIFO state */
125 struct i3c_ccc_payload *ccc_payload; /* Current CCC message payload */
126 struct i3c_ccc_target_payload *
127 ccc_target_payload; /* Current target addressed by 2nd part of direct CCC command */
128 struct i3c_ccc_target_payload
129 *ccc_target_payload_sf; /* Current target addressed
130 * by 2nd part of direct CCC command used by the
131 status FIFO
132 */
133 size_t ccc_target_idx; /* Current target index, used for filling C-FIFO */
134 struct k_sem device_sync_sem; /* Sync between device communication messages */
135 struct k_mutex bus_mutex; /* Sync between transfers */
136 struct i3c_stm32_msg curr_msg;
137 uint8_t target_addr; /* Current target xfer address */
138 uint8_t num_msgs; /* Number of messages to send on bus */
139 #ifdef CONFIG_I3C_STM32_DMA
140 struct i3c_stm32_dma_stream dma_rx; /* RX DMA channel config */
141 struct i3c_stm32_dma_stream dma_tx; /* TX DMA channel config */
142 struct i3c_stm32_dma_stream dma_tc; /* Control FIFO DMA channel config */
143 struct i3c_stm32_dma_stream dma_rs; /* Status FIFO DMA channel config */
144 uint32_t *status_fifo; /* Pointer to the allocated region for status FIFO words */
145 uint32_t *control_fifo; /* Pointer to the allocated region for control FIFO words */
146 size_t fifo_len; /* The size in bytes for the allocated region for each FIFO */
147 #endif
148 uint64_t pid; /* Current DAA target PID */
149 size_t daa_rx_rcv; /* Number of RX bytes received during DAA */
150 uint8_t target_id; /* Target id */
151 #ifdef CONFIG_I3C_USE_IBI
152 uint32_t ibi_payload; /* Received ibi payload */
153 uint32_t ibi_payload_size; /* Received payload size */
154 uint32_t ibi_target_addr; /* Received target dynamic address */
155 struct {
156 uint8_t addr[4]; /* List of target addresses */
157 uint8_t num_addr; /* Number of valid addresses */
158 } ibi;
159 struct k_sem ibi_lock_sem; /* Semaphore used for ibi requests */
160 #endif
161 };
162 /**
163 * Determine I3C bus mode from the i2c devices on the bus.
164 *
165 * Reads the LVR of all I2C devices and returns the I3C bus
166 * Mode.
167 *
168 * @param dev_list Pointer to device list
169 *
170 * @return @see enum i3c_bus_mode.
171 */
i3c_bus_mode(const struct i3c_dev_list * dev_list)172 static enum i3c_bus_mode i3c_bus_mode(const struct i3c_dev_list *dev_list)
173 {
174 enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
175
176 for (int i = 0; i < dev_list->num_i2c; i++) {
177 switch (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr)) {
178 case I3C_LVR_I2C_DEV_IDX_0:
179 if (mode < I3C_BUS_MODE_MIXED_FAST) {
180 mode = I3C_BUS_MODE_MIXED_FAST;
181 }
182 break;
183 case I3C_LVR_I2C_DEV_IDX_1:
184 if (mode < I3C_BUS_MODE_MIXED_LIMITED) {
185 mode = I3C_BUS_MODE_MIXED_LIMITED;
186 }
187 break;
188 case I3C_LVR_I2C_DEV_IDX_2:
189 if (mode < I3C_BUS_MODE_MIXED_SLOW) {
190 mode = I3C_BUS_MODE_MIXED_SLOW;
191 }
192 break;
193 default:
194 mode = I3C_BUS_MODE_INVALID;
195 break;
196 }
197 }
198 return mode;
199 }
200
get_i3c_lvr_ic_mode(const struct i3c_dev_list * dev_list)201 static int get_i3c_lvr_ic_mode(const struct i3c_dev_list *dev_list)
202 {
203 for (int i = 0; i < dev_list->num_i2c; i++) {
204 if (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr) == I3C_LVR_I2C_DEV_IDX_0) {
205 if (I3C_LVR_I2C_MODE(dev_list->i2c[i].lvr) == I3C_LVR_I2C_FM_MODE) {
206 return I3C_LVR_I2C_FM_MODE;
207 }
208 }
209 }
210 return I3C_LVR_I2C_FM_PLUS_MODE;
211 }
212
i3c_stm32_curr_msg_is_i3c(const struct device * dev)213 static bool i3c_stm32_curr_msg_is_i3c(const struct device *dev)
214 {
215 struct i3c_stm32_data *data = dev->data;
216 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
217
218 return (curr_msg->msg_type == LL_I3C_CONTROLLER_MTYPE_PRIVATE);
219 }
220
i3c_stm32_arbitration_header_config(const struct device * dev)221 static void i3c_stm32_arbitration_header_config(const struct device *dev)
222 {
223 struct i3c_stm32_data *data = dev->data;
224 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
225 const struct i3c_stm32_config *config = dev->config;
226 I3C_TypeDef *i3c = config->i3c;
227
228 if (i3c_stm32_curr_msg_is_i3c(dev)) {
229 if (curr_msg->i3c_msg_ctrl_ptr->flags & I3C_MSG_NBCH) {
230 /* Disable arbitration header for this transaction */
231 LL_I3C_DisableArbitrationHeader(i3c);
232 } else {
233 /* Enable arbitration header for this transaction */
234 LL_I3C_EnableArbitrationHeader(i3c);
235 }
236 }
237 }
238
i3c_stm32_curr_msg_init(const struct device * dev,struct i3c_msg * i3c_msgs,struct i2c_msg * i2c_msgs,uint8_t num_msgs,uint8_t tgt_addr)239 static int i3c_stm32_curr_msg_init(const struct device *dev, struct i3c_msg *i3c_msgs,
240 struct i2c_msg *i2c_msgs, uint8_t num_msgs, uint8_t tgt_addr)
241 {
242 struct i3c_stm32_data *data = dev->data;
243 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
244
245 /* Either should be NULL */
246 __ASSERT(!(i3c_msgs == NULL && i2c_msgs == NULL), "Both i3c_msgs and i2c_msgs are NULL");
247 __ASSERT(!(i3c_msgs != NULL && i2c_msgs != NULL),
248 "Both i3c_msgs and i2c_msgs are not NULL");
249
250 curr_msg->target_addr = tgt_addr;
251 curr_msg->xfer_offset = 0;
252 curr_msg->num_msgs = num_msgs;
253 curr_msg->ctrl_msg_idx = 0;
254 curr_msg->status_msg_idx = 0;
255 curr_msg->xfer_msg_idx = 0;
256
257 /* I3C private message */
258 if (i2c_msgs == NULL) {
259 curr_msg->msg_type = LL_I3C_CONTROLLER_MTYPE_PRIVATE;
260 curr_msg->i3c_msg_ptr = i3c_msgs;
261 curr_msg->i3c_msg_ctrl_ptr = i3c_msgs;
262 curr_msg->i3c_msg_status_ptr = i3c_msgs;
263 } else {
264 /* Legacy I2C message */
265 curr_msg->msg_type = LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C;
266 curr_msg->i2c_msg_ptr = i2c_msgs;
267 curr_msg->i2c_msg_ctrl_ptr = i2c_msgs;
268 }
269
270 i3c_stm32_arbitration_header_config(dev);
271 return 0;
272 }
273
i3c_stm32_curr_msg_control_get_dir(const struct device * dev)274 static int i3c_stm32_curr_msg_control_get_dir(const struct device *dev)
275 {
276 struct i3c_stm32_data *data = dev->data;
277 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
278
279 if (i3c_stm32_curr_msg_is_i3c(dev)) {
280 return (((curr_msg->i3c_msg_ctrl_ptr->flags & I3C_MSG_RW_MASK) == I3C_MSG_READ)
281 ? LL_I3C_DIRECTION_READ
282 : LL_I3C_DIRECTION_WRITE);
283 }
284
285 return (((curr_msg->i2c_msg_ctrl_ptr->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ)
286 ? LL_I3C_DIRECTION_READ
287 : LL_I3C_DIRECTION_WRITE);
288 }
289
i3c_stm32_curr_msg_control_get_len(const struct device * dev)290 static int i3c_stm32_curr_msg_control_get_len(const struct device *dev)
291 {
292 struct i3c_stm32_data *data = dev->data;
293 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
294
295 return (i3c_stm32_curr_msg_is_i3c(dev)) ? curr_msg->i3c_msg_ctrl_ptr->len
296 : curr_msg->i2c_msg_ctrl_ptr->len;
297 }
298
i3c_stm32_curr_msg_control_get_end(const struct device * dev)299 static int i3c_stm32_curr_msg_control_get_end(const struct device *dev)
300 {
301 struct i3c_stm32_data *data = dev->data;
302 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
303
304 return ((curr_msg->ctrl_msg_idx < (curr_msg->num_msgs - 1)) ? LL_I3C_GENERATE_RESTART
305 : LL_I3C_GENERATE_STOP);
306 }
307
i3c_stm32_curr_msg_control_next(const struct device * dev)308 static int i3c_stm32_curr_msg_control_next(const struct device *dev)
309 {
310 struct i3c_stm32_data *data = dev->data;
311 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
312
313 if (curr_msg->ctrl_msg_idx >= curr_msg->num_msgs) {
314 LOG_ERR("No more messages left");
315 return -EFAULT;
316 }
317
318 if (i3c_stm32_curr_msg_is_i3c(dev)) {
319 curr_msg->i3c_msg_ctrl_ptr++;
320 } else {
321 curr_msg->i2c_msg_ctrl_ptr++;
322 }
323
324 curr_msg->ctrl_msg_idx++;
325
326 return 0;
327 }
328
i3c_stm32_curr_msg_status_update_num_xfer(const struct device * dev,size_t num_xfer)329 static int i3c_stm32_curr_msg_status_update_num_xfer(const struct device *dev, size_t num_xfer)
330 {
331 struct i3c_stm32_data *data = dev->data;
332 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
333
334 if (curr_msg->status_msg_idx >= curr_msg->num_msgs) {
335 LOG_ERR("No more messages left");
336 return -EFAULT;
337 }
338
339 /* Legacy I2C messages do not have num_xfer */
340 if (i3c_stm32_curr_msg_is_i3c(dev)) {
341 curr_msg->i3c_msg_status_ptr->num_xfer = num_xfer;
342 }
343
344 return 0;
345 }
346
i3c_stm32_curr_msg_status_next(const struct device * dev)347 static int i3c_stm32_curr_msg_status_next(const struct device *dev)
348 {
349 struct i3c_stm32_data *data = dev->data;
350 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
351
352 if (curr_msg->status_msg_idx >= curr_msg->num_msgs) {
353 LOG_ERR("No more messages left");
354 return -EFAULT;
355 }
356
357 if (i3c_stm32_curr_msg_is_i3c(dev)) {
358 curr_msg->i3c_msg_status_ptr++;
359 curr_msg->status_msg_idx++;
360 }
361
362 return 0;
363 }
364
i3c_stm32_curr_msg_xfer_get_buf(const struct device * dev,uint8_t ** buf,uint32_t * len,size_t ** offset)365 static int i3c_stm32_curr_msg_xfer_get_buf(const struct device *dev, uint8_t **buf, uint32_t *len,
366 size_t **offset)
367 {
368 struct i3c_stm32_data *data = dev->data;
369 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
370
371 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) {
372 LOG_ERR("No more messages left");
373 return -EFAULT;
374 }
375
376 if (i3c_stm32_curr_msg_is_i3c(dev)) {
377 *buf = curr_msg->i3c_msg_ptr->buf;
378 *len = curr_msg->i3c_msg_ptr->len;
379 } else {
380 *buf = curr_msg->i2c_msg_ptr->buf;
381 *len = curr_msg->i2c_msg_ptr->len;
382 }
383
384 *offset = &curr_msg->xfer_offset;
385
386 return 0;
387 }
388
389 /* This method is only used in DMA mode */
390 #ifdef CONFIG_I3C_STM32_DMA
i3c_stm32_curr_msg_xfer_is_read(const struct device * dev)391 static bool i3c_stm32_curr_msg_xfer_is_read(const struct device *dev)
392 {
393 struct i3c_stm32_data *data = dev->data;
394 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
395
396 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) {
397 LOG_ERR("No more messages left");
398 return false;
399 }
400
401 if (i3c_stm32_curr_msg_is_i3c(dev)) {
402 return ((curr_msg->i3c_msg_ptr->flags & I3C_MSG_RW_MASK) == I3C_MSG_READ);
403 }
404
405 return ((curr_msg->i2c_msg_ptr->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ);
406 }
407 #endif /* CONFIG_I3C_STM32_DMA */
408
i3c_stm32_curr_msg_xfer_next(const struct device * dev)409 static int i3c_stm32_curr_msg_xfer_next(const struct device *dev)
410 {
411 struct i3c_stm32_data *data = dev->data;
412 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
413
414 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) {
415 LOG_ERR("No more messages left");
416 return -EFAULT;
417 }
418
419 if (i3c_stm32_curr_msg_is_i3c(dev)) {
420 curr_msg->i3c_msg_ptr++;
421 } else {
422 curr_msg->i2c_msg_ptr++;
423 }
424
425 curr_msg->xfer_msg_idx++;
426 curr_msg->xfer_offset = 0;
427
428 return 0;
429 }
430
431 /* Activates the device I3C pinctrl and CLK */
i3c_stm32_activate(const struct device * dev)432 static int i3c_stm32_activate(const struct device *dev)
433 {
434 int ret;
435 struct i3c_stm32_config *config = (struct i3c_stm32_config *)dev->config;
436 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
437
438 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
439 if (ret < 0) {
440 return ret;
441 }
442
443 if (clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]) != 0) {
444 return -EIO;
445 }
446 return 0;
447 }
448
i3c_stm32_calc_scll_od_sclh_i2c(const struct device * dev,uint32_t i2c_bus_freq,uint32_t i3c_clock,uint8_t * scll_od,uint8_t * sclh_i2c)449 static int i3c_stm32_calc_scll_od_sclh_i2c(const struct device *dev, uint32_t i2c_bus_freq,
450 uint32_t i3c_clock, uint8_t *scll_od, uint8_t *sclh_i2c)
451 {
452 const struct i3c_stm32_config *config = dev->config;
453
454 if (i2c_bus_freq != 0) {
455 if (i2c_bus_freq > 400000) {
456 /* I2C bus is FM+ */
457 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FMP_NS * i3c_clock,
458 1000000000ull) -
459 1;
460 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - *scll_od - 2;
461 if (*sclh_i2c <
462 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FMP_NS * i3c_clock, 1000000000ull) -
463 1) {
464 LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C at "
465 "current I3C clock "
466 "frequency for FM+ I2C bus");
467 return -EINVAL;
468 }
469 } else {
470 /* I2C bus is FM */
471 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FM_NS * i3c_clock,
472 1000000000ull) -
473 1;
474 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - *scll_od - 2;
475 }
476
477 if (*sclh_i2c <
478 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FM_NS * i3c_clock, 1000000000ull) - 1) {
479 LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C at current I3C "
480 "clock "
481 "frequency for FM I2C bus");
482 return -EINVAL;
483 }
484 } else {
485 if (config->drv_cfg.dev_list.num_i2c > 0) {
486 enum i3c_bus_mode mode = i3c_bus_mode(&config->drv_cfg.dev_list);
487
488 if (mode == I3C_BUS_MODE_MIXED_FAST) {
489 if (get_i3c_lvr_ic_mode(&config->drv_cfg.dev_list) ==
490 I3C_LVR_I2C_FM_MODE) {
491 /* I2C bus is FM */
492 i2c_bus_freq = 400000;
493 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FM_NS *
494 i3c_clock,
495 1000000000ull) -
496 1;
497 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) -
498 *scll_od - 2;
499 } else {
500 /* I2C bus is FM+ */
501 i2c_bus_freq = 1000000;
502 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FMP_NS *
503 i3c_clock,
504 1000000000ull) -
505 1;
506 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) -
507 *scll_od - 2;
508 if (*sclh_i2c <
509 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FMP_NS * i3c_clock,
510 1000000000ull) -
511 1) {
512 LOG_ERR("Cannot find a combination of SCLL_OD and "
513 "SCLH_I2C at current I3C clock "
514 "frequency for FM+ I2C bus");
515 return -EINVAL;
516 }
517 }
518
519 if (*sclh_i2c <
520 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FM_NS * i3c_clock,
521 1000000000ull) -
522 1) {
523 LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C "
524 "at current I3C clock "
525 "frequency for FM I2C bus");
526 return -EINVAL;
527 }
528 } else {
529 return -EINVAL;
530 }
531 } else {
532 /* Assume no I2C devices on the bus */
533 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_I3C_NS * i3c_clock,
534 1000000000ull) -
535 1;
536 *sclh_i2c = 0;
537 }
538 }
539
540 LOG_DBG("TimingReg0: SCLL_OD = %d, SCLH_I2C = %d", *scll_od, *sclh_i2c);
541 return 0;
542 }
543
i3c_stm32_calc_scll_pp_sclh_i3c(uint32_t i3c_bus_freq,uint32_t i3c_clock,uint8_t * scll_pp,uint8_t * sclh_i3c)544 static int i3c_stm32_calc_scll_pp_sclh_i3c(uint32_t i3c_bus_freq, uint32_t i3c_clock,
545 uint8_t *scll_pp, uint8_t *sclh_i3c)
546 {
547 *sclh_i3c = DIV_ROUND_UP(STM32_I3C_SCLH_I3C_MIN_NS * i3c_clock, 1000000000ull) - 1;
548 *scll_pp = DIV_ROUND_UP(i3c_clock, i3c_bus_freq) - *sclh_i3c - 2;
549
550 if (*scll_pp < DIV_ROUND_UP(STM32_I3C_SCLL_PP_MIN_NS * i3c_clock, 1000000000ull) - 1) {
551 LOG_ERR("Cannot find a combination of SCLL_PP and SCLH_I3C at current I3C clock "
552 "frequency for specified I3C bus speed");
553 return -EINVAL;
554 }
555
556 LOG_DBG("TimingReg0: SCLL_PP = %d, SCLH_I3C = %d", *scll_pp, *sclh_i3c);
557 return 0;
558 }
559
i3c_stm32_config_clk_wave(const struct device * dev)560 static int i3c_stm32_config_clk_wave(const struct device *dev)
561 {
562 const struct i3c_stm32_config *cfg = dev->config;
563 struct i3c_stm32_data *data = dev->data;
564 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
565 I3C_TypeDef *i3c = cfg->i3c;
566 uint32_t i3c_clock = 0;
567 uint32_t i2c_bus_freq = data->drv_data.ctrl_config.scl.i2c;
568 uint32_t i3c_bus_freq = data->drv_data.ctrl_config.scl.i3c;
569
570 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[0], &i3c_clock) < 0) {
571 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
572 return -EIO;
573 }
574
575 uint8_t scll_od = 0;
576 uint8_t sclh_i2c = 0;
577 uint8_t scll_pp = 0;
578 uint8_t sclh_i3c = 0;
579 uint32_t clk_wave = 0;
580 int ret;
581
582 LOG_DBG("I3C Clock = %u, I2C Bus Freq = %u, I3C Bus Freq = %u", i3c_clock, i2c_bus_freq,
583 i3c_bus_freq);
584
585 ret = i3c_stm32_calc_scll_od_sclh_i2c(dev, i2c_bus_freq, i3c_clock, &scll_od, &sclh_i2c);
586 if (ret != 0) {
587 LOG_ERR("Cannot calculate the timing for TimingReg0, err=%d", ret);
588 return ret;
589 }
590
591 ret = i3c_stm32_calc_scll_pp_sclh_i3c(i3c_bus_freq, i3c_clock, &scll_pp, &sclh_i3c);
592 if (ret != 0) {
593 LOG_ERR("Cannot calculate the timing for TimingReg0, err=%d", ret);
594 return ret;
595 }
596
597 clk_wave = ((uint32_t)sclh_i2c << 24) | ((uint32_t)scll_od << 16) |
598 ((uint32_t)sclh_i3c << 8) | (scll_pp);
599
600 LOG_DBG("TimigReg0 = 0x%08x", clk_wave);
601
602 LL_I3C_ConfigClockWaveForm(i3c, clk_wave);
603
604 return 0;
605 }
606 /**
607 * @brief Get current configuration of the I3C hardware.
608 *
609 * @param[in] dev Pointer to controller device driver instance.
610 * @param[in] type Type of configuration.
611 * @param[in,out] config Pointer to the configuration parameters.
612 *
613 * @retval 0 If successful.
614 * @retval -EIO General Input/Output errors.
615 * @retval -ENOSYS If not implemented.
616 */
i3c_stm32_config_get(const struct device * dev,enum i3c_config_type type,void * config)617 static int i3c_stm32_config_get(const struct device *dev, enum i3c_config_type type, void *config)
618 {
619 struct i3c_stm32_data *data = dev->data;
620
621 if ((type != I3C_CONFIG_CONTROLLER) || (config == NULL)) {
622 return -EINVAL;
623 }
624
625 (void)memcpy(config, &data->drv_data.ctrl_config, sizeof(data->drv_data.ctrl_config));
626
627 return 0;
628 }
629
i3c_stm32_config_ctrl_bus_char(const struct device * dev)630 static int i3c_stm32_config_ctrl_bus_char(const struct device *dev)
631 {
632 const struct i3c_stm32_config *config = dev->config;
633 struct i3c_stm32_data *data = dev->data;
634 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
635 I3C_TypeDef *i3c = config->i3c;
636 uint32_t i3c_clock = 0;
637 uint32_t i2c_bus_freq = data->drv_data.ctrl_config.scl.i2c;
638
639 uint8_t free_timing = 0;
640 uint8_t aval = 0;
641
642 if (clock_control_get_rate(clk, (clock_control_subsys_t)&config->pclken[0], &i3c_clock) <
643 0) {
644 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
645 return -EIO;
646 }
647
648 /* Satisfying I3C start timing min timing will statisfy the rest of the conditions */
649
650 if (i2c_bus_freq != 0) {
651 if (i2c_bus_freq > 400000) {
652 /* Mixed bus with I2C FM+ device */
653 free_timing = (uint8_t)ceil(
654 (STM32_I3C_TBUF_FMP_MIN_NS * i3c_clock / 1e9 - 0.5) / 2);
655 } else {
656 /* Mixed bus with I2C FM device */
657 free_timing = (uint8_t)ceil(
658 (STM32_I3C_TBUF_FM_MIN_NS * i3c_clock / 1e9 - 0.5) / 2);
659 }
660 } else {
661 if (config->drv_cfg.dev_list.num_i2c > 0) {
662 enum i3c_bus_mode mode = i3c_bus_mode(&config->drv_cfg.dev_list);
663
664 if (mode == I3C_BUS_MODE_MIXED_FAST) {
665 if (get_i3c_lvr_ic_mode(&config->drv_cfg.dev_list) ==
666 I3C_LVR_I2C_FM_MODE) {
667 /* Mixed bus with I2C FM device */
668 free_timing = (uint8_t)ceil(
669 (STM32_I3C_TBUF_FM_MIN_NS * i3c_clock / 1e9 - 0.5) /
670 2);
671 } else {
672 /* Mixed bus with I2C FM+ device */
673 free_timing = (uint8_t)ceil(
674 (STM32_I3C_TBUF_FMP_MIN_NS * i3c_clock / 1e9 -
675 0.5) /
676 2);
677 }
678 } else {
679 return -EINVAL;
680 }
681 } else {
682 /* Pure I3C bus */
683 free_timing =
684 (uint8_t)ceil((STM32_I3C_TCAS_MIN_NS * i3c_clock / 1e9 - 0.5) / 2);
685 }
686 }
687
688 aval = DIV_ROUND_UP(1000ull * i3c_clock, 1000000000ull) - 1;
689
690 LL_I3C_SetFreeTiming(i3c, free_timing);
691 LL_I3C_SetAvalTiming(i3c, aval);
692 LL_I3C_SetDataHoldTime(i3c, LL_I3C_SDA_HOLD_TIME_1_5);
693
694 LOG_DBG("TimingReg1 = 0x%08x", LL_I3C_GetCtrlBusCharacteristic(i3c));
695
696 return 0;
697 }
698
699 /* Configures the I3C module in controller mode */
i3c_stm32_configure(const struct device * dev,enum i3c_config_type type,void * cfg)700 static int i3c_stm32_configure(const struct device *dev, enum i3c_config_type type, void *cfg)
701 {
702 int ret;
703
704 if (type == I3C_CONFIG_TARGET || type == I3C_CONFIG_CUSTOM) {
705 return -ENOTSUP;
706 }
707
708 struct i3c_stm32_data *data = dev->data;
709 struct i3c_config_controller *ctrl_cfg = cfg;
710
711 if ((ctrl_cfg->scl.i2c == 0U) || (ctrl_cfg->scl.i3c == 0U)) {
712 return -EINVAL;
713 }
714
715 data->drv_data.ctrl_config.scl.i3c = ctrl_cfg->scl.i3c;
716 data->drv_data.ctrl_config.scl.i2c = ctrl_cfg->scl.i2c;
717
718 ret = i3c_stm32_activate(dev);
719 if (ret != 0) {
720 LOG_ERR("Clock and GPIO could not be initialized for the I3C module, err=%d", ret);
721 return ret;
722 }
723
724 ret = i3c_stm32_config_clk_wave(dev);
725 if (ret != 0) {
726 LOG_ERR("TimigReg0 timing could not be calculated, err=%d", ret);
727 return ret;
728 }
729
730 ret = i3c_stm32_config_ctrl_bus_char(dev);
731 if (ret != 0) {
732 LOG_ERR("TimingReg1 timing could not be calculated, err=%d", ret);
733 return ret;
734 }
735
736 return 0;
737 }
738
i3c_stm32_i2c_configure(const struct device * dev,uint32_t config)739 static int i3c_stm32_i2c_configure(const struct device *dev, uint32_t config)
740 {
741 struct i3c_stm32_data *data = dev->data;
742 struct i3c_config_controller *ctrl_config = &data->drv_data.ctrl_config;
743
744 switch (I2C_SPEED_GET(config)) {
745 case I2C_SPEED_FAST:
746 ctrl_config->scl.i2c = 400000;
747 break;
748 case I2C_SPEED_FAST_PLUS:
749 ctrl_config->scl.i2c = 1000000;
750 break;
751 default:
752 return -EINVAL;
753 }
754
755 return 0;
756 }
757
758 /**
759 * @brief Find a registered I3C target device.
760 *
761 * This returns the I3C device descriptor of the I3C device
762 * matching the incoming @p id.
763 *
764 * @param dev Pointer to controller device driver instance.
765 * @param id Pointer to I3C device ID.
766 *
767 * @return @see i3c_device_find.
768 */
i3c_stm32_device_find(const struct device * dev,const struct i3c_device_id * id)769 static struct i3c_device_desc *i3c_stm32_device_find(const struct device *dev,
770 const struct i3c_device_id *id)
771 {
772 const struct i3c_stm32_config *config = dev->config;
773
774 return i3c_dev_list_find(&config->drv_cfg.dev_list, id);
775 }
776
777 #ifdef CONFIG_I3C_STM32_DMA
778
i3c_stm32_end_dma_requests(const struct device * dev)779 static void i3c_stm32_end_dma_requests(const struct device *dev)
780 {
781 const struct i3c_stm32_config *config = dev->config;
782 I3C_TypeDef *i3c = config->i3c;
783
784 LL_I3C_EnableIT_TXFNF(i3c);
785 LL_I3C_EnableIT_RXFNE(i3c);
786 LL_I3C_EnableIT_CFNF(i3c);
787 LL_I3C_EnableIT_SFNE(i3c);
788
789 LL_I3C_DisableDMAReq_TX(i3c);
790 LL_I3C_DisableDMAReq_RX(i3c);
791 LL_I3C_DisableDMAReq_Control(i3c);
792 LL_I3C_DisableDMAReq_Status(i3c);
793 }
794
i3c_stm32_prepare_dma_requests(const struct device * dev)795 static void i3c_stm32_prepare_dma_requests(const struct device *dev)
796 {
797 const struct i3c_stm32_config *config = dev->config;
798 I3C_TypeDef *i3c = config->i3c;
799
800 LL_I3C_DisableIT_TXFNF(i3c);
801 LL_I3C_DisableIT_RXFNE(i3c);
802 LL_I3C_DisableIT_CFNF(i3c);
803 LL_I3C_DisableIT_SFNE(i3c);
804
805 LL_I3C_EnableDMAReq_TX(i3c);
806 LL_I3C_EnableDMAReq_RX(i3c);
807 LL_I3C_EnableDMAReq_Control(i3c);
808 LL_I3C_EnableDMAReq_Status(i3c);
809 }
810
811 #endif /* CONFIG_I3C_STM32_DMA */
812
i3c_stm32_flush_all_fifo(const struct device * dev)813 static void i3c_stm32_flush_all_fifo(const struct device *dev)
814 {
815 const struct i3c_stm32_config *config = dev->config;
816 I3C_TypeDef *i3c = config->i3c;
817
818 LL_I3C_RequestTxFIFOFlush(i3c);
819 LL_I3C_RequestRxFIFOFlush(i3c);
820 LL_I3C_RequestControlFIFOFlush(i3c);
821 LL_I3C_RequestStatusFIFOFlush(i3c);
822 }
823
i3c_stm32_log_err_type(const struct device * dev)824 static void i3c_stm32_log_err_type(const struct device *dev)
825 {
826 const struct i3c_stm32_config *config = dev->config;
827 I3C_TypeDef *i3c = config->i3c;
828
829 if (LL_I3C_IsActiveFlag_ANACK(i3c)) {
830 LOG_ERR("Address NACK");
831 }
832
833 if (LL_I3C_IsActiveFlag_COVR(i3c)) {
834 LOG_ERR("Control/Status FIFO underrun/overrun");
835 }
836
837 if (LL_I3C_IsActiveFlag_DOVR(i3c)) {
838 LOG_ERR("TX/RX FIFO underrun/overrun");
839 }
840
841 if (LL_I3C_IsActiveFlag_DNACK(i3c)) {
842 LOG_ERR("Data NACK by target");
843 }
844
845 if (LL_I3C_IsActiveFlag_PERR(i3c)) {
846 switch (LL_I3C_GetMessageErrorCode(i3c)) {
847 case LL_I3C_CONTROLLER_ERROR_CE0:
848 LOG_ERR("Illegally formatted CCC detected");
849 break;
850 case LL_I3C_CONTROLLER_ERROR_CE1:
851 LOG_ERR("Data on bus is not as expected");
852 break;
853 case LL_I3C_CONTROLLER_ERROR_CE2:
854 LOG_ERR("No response to broadcast address");
855 break;
856 default:
857 LOG_ERR("Unsupported error detected");
858 break;
859 }
860 }
861 }
862
i3c_stm32_clear_err(const struct device * dev,bool is_i2c_xfer)863 static void i3c_stm32_clear_err(const struct device *dev, bool is_i2c_xfer)
864 {
865 struct i3c_stm32_data *data = dev->data;
866 const struct i3c_stm32_config *config = dev->config;
867 I3C_TypeDef *i3c = config->i3c;
868
869 i3c_stm32_flush_all_fifo(dev);
870
871 /* Re-enable arbirtation header after exiting from error caused by legacy I2C msg */
872 if (is_i2c_xfer) {
873 LL_I3C_EnableArbitrationHeader(i3c);
874 }
875
876 #ifdef CONFIG_I3C_STM32_DMA
877 i3c_stm32_end_dma_requests(dev);
878
879 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo);
880 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo);
881 #endif
882
883 data->msg_state = STM32_I3C_MSG_IDLE;
884 data->sf_state = STM32_I3C_SF_IDLE;
885
886 k_mutex_unlock(&data->bus_mutex);
887 }
888
889 /**
890 * @brief Fills the I3C TX FIFO from a given buffer
891 *
892 * @param buf The buffer to fill the TX FIFO from
893 * @param len The total buffer length
894 * @param offset Pointer to the offset from the beginning of buffer which will be incremented by the
895 * number of bytes sent to the TX FIFO
896 *
897 * @return Returns true if last byte was sent (TXLAST flag was set)
898 */
i3c_stm32_fill_tx_fifo(const struct device * dev,uint8_t * buf,size_t len,size_t * offset)899 static bool i3c_stm32_fill_tx_fifo(const struct device *dev, uint8_t *buf, size_t len,
900 size_t *offset)
901 {
902 const struct i3c_stm32_config *config = dev->config;
903 I3C_TypeDef *i3c = config->i3c;
904 bool is_last = false;
905
906 if (*offset >= len) {
907 return 0;
908 }
909
910 while (LL_I3C_IsActiveFlag_TXFNF(i3c)) {
911 if (LL_I3C_IsActiveFlag_TXLAST(i3c)) {
912 is_last = true;
913 }
914
915 if (*offset < len) {
916 LL_I3C_TransmitData8(i3c, buf[(*offset)++]);
917 }
918
919 if (is_last) {
920 return is_last;
921 }
922 }
923
924 return is_last;
925 }
926
927 /**
928 * @brief Drains the I3C RX FIFO from a given buffer
929 *
930 * @param buf The buffer to drain the RX FIFO to
931 * @param len The total buffer length
932 * @param offset Pointer to the offset from the beginning of buffer which will be incremented by the
933 * number of bytes drained from the RX FIFO
934 *
935 * @return Returns true if last byte was received (RXLAST flag was set)
936 */
i3c_stm32_drain_rx_fifo(const struct device * dev,uint8_t * buf,uint32_t len,size_t * offset)937 static bool i3c_stm32_drain_rx_fifo(const struct device *dev, uint8_t *buf, uint32_t len,
938 size_t *offset)
939 {
940 const struct i3c_stm32_config *config = dev->config;
941 I3C_TypeDef *i3c = config->i3c;
942 bool is_last = false;
943
944 if (*offset >= len) {
945 return 0;
946 }
947
948 while (LL_I3C_IsActiveFlag_RXFNE(i3c)) {
949 if (LL_I3C_IsActiveFlag_RXLAST(i3c)) {
950 is_last = true;
951 }
952
953 if (*offset < len) {
954 buf[(*offset)++] = LL_I3C_ReceiveData8(i3c);
955 }
956
957 if (is_last) {
958 return is_last;
959 }
960 }
961
962 return is_last;
963 }
964
965 /* Handles broadcast/direct CCCs except for ENTDAA */
i3c_stm32_do_ccc(const struct device * dev,struct i3c_ccc_payload * payload)966 static int i3c_stm32_do_ccc(const struct device *dev, struct i3c_ccc_payload *payload)
967 {
968 const struct i3c_stm32_config *config = dev->config;
969 struct i3c_stm32_data *data = dev->data;
970 I3C_TypeDef *i3c = config->i3c;
971
972 __ASSERT(dev != NULL, "I3C Device is NULL.");
973 __ASSERT(payload != NULL, "I3C Payload is NULL.");
974
975 if (payload->ccc.id == I3C_CCC_ENTDAA) {
976 return -EINVAL;
977 }
978
979 /* Check if payload has targets when sending a direct CCC */
980 if (!i3c_ccc_is_payload_broadcast(payload) &&
981 (payload->targets.payloads == NULL || payload->targets.num_targets == 0)) {
982 return -EINVAL;
983 }
984
985 if (payload->ccc.data_len > 0 && payload->ccc.data == NULL) {
986 return -EINVAL;
987 }
988
989 k_mutex_lock(&data->bus_mutex, K_FOREVER);
990
991 /* Disable Status FIFO and enable the RXTGTEND interrupt flag to detected early read
992 * termination from target during read CCC commands
993 */
994 LL_I3C_DisableStatusFIFO(i3c);
995 LL_I3C_EnableIT_RXTGTEND(i3c);
996
997 (void)pm_device_runtime_get(dev);
998
999 /* Prevent the clocks to be stopped during the transaction */
1000 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1001
1002 /* Mark current transfer as CCC */
1003 data->msg_state = STM32_I3C_MSG_CCC;
1004 data->ccc_payload = payload;
1005 data->ccc_target_idx = 0;
1006 data->ccc_target_payload = payload->targets.payloads;
1007
1008 payload->ccc.num_xfer = 0;
1009
1010 for (size_t i = 0; i < payload->targets.num_targets; i++) {
1011 payload->targets.payloads[i].num_xfer = 0;
1012 }
1013
1014 /* Start CCC transfer */
1015 LL_I3C_ControllerHandleCCC(i3c, payload->ccc.id, payload->ccc.data_len,
1016 (i3c_ccc_is_payload_broadcast(payload)
1017 ? LL_I3C_GENERATE_STOP
1018 : LL_I3C_GENERATE_RESTART));
1019
1020 /* Wait for CCC to complete */
1021 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) {
1022 LL_I3C_DisableIT_RXTGTEND(i3c);
1023 LL_I3C_EnableStatusFIFO(i3c);
1024 i3c_stm32_clear_err(dev, false);
1025 return -ETIMEDOUT;
1026 }
1027
1028 if (data->msg_state == STM32_I3C_MSG_ERR) {
1029 LL_I3C_DisableIT_RXTGTEND(i3c);
1030 LL_I3C_EnableStatusFIFO(i3c);
1031 i3c_stm32_clear_err(dev, false);
1032 return -EIO;
1033 }
1034
1035 LL_I3C_DisableIT_RXTGTEND(i3c);
1036 LL_I3C_EnableStatusFIFO(i3c);
1037 k_mutex_unlock(&data->bus_mutex);
1038
1039 return 0;
1040 }
1041
1042 /* Handles the ENTDAA CCC */
i3c_stm32_do_daa(const struct device * dev)1043 static int i3c_stm32_do_daa(const struct device *dev)
1044 {
1045 const struct i3c_stm32_config *config = dev->config;
1046 struct i3c_stm32_data *data = dev->data;
1047 I3C_TypeDef *i3c = config->i3c;
1048
1049 k_mutex_lock(&data->bus_mutex, K_FOREVER);
1050
1051 (void)pm_device_runtime_get(dev);
1052
1053 /* Prevent the clocks to be stopped during the transaction */
1054 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1055
1056 /* Mark current transfer as DAA */
1057 data->msg_state = STM32_I3C_MSG_DAA;
1058
1059 /* Disable TXFNF interrupt, the RXFNE interrupt will enable it once all PID bytes are
1060 * received
1061 */
1062 LL_I3C_DisableIT_TXFNF(i3c);
1063
1064 /* Start DAA */
1065 LL_I3C_ControllerHandleCCC(i3c, I3C_CCC_ENTDAA, 0, LL_I3C_GENERATE_STOP);
1066
1067 /* Wait for DAA to finish */
1068 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) {
1069 return -ETIMEDOUT;
1070 }
1071
1072 if (data->msg_state == STM32_I3C_MSG_ERR) {
1073 i3c_stm32_clear_err(dev, false);
1074 /* Enable TXFNF interrupt in case an error occurred before it was enabled by RXFNE
1075 */
1076 LL_I3C_EnableIT_TXFNF(i3c);
1077 return -EIO;
1078 }
1079
1080 k_mutex_unlock(&data->bus_mutex);
1081
1082 return 0;
1083 }
1084
1085 #ifdef CONFIG_I3C_STM32_DMA
1086
i3c_stm32_dma_msg_control_fifo_config(const struct device * dev)1087 static int i3c_stm32_dma_msg_control_fifo_config(const struct device *dev)
1088 {
1089 struct i3c_stm32_data *data = dev->data;
1090 int ret;
1091
1092 data->dma_tc.blk_cfg.source_address = (uint32_t)data->control_fifo;
1093 data->dma_tc.blk_cfg.block_size = data->fifo_len;
1094
1095 ret = dma_config(data->dma_tc.dma_dev, data->dma_tc.dma_channel, &data->dma_tc.dma_cfg);
1096
1097 if (ret != 0) {
1098 LOG_ERR("Control DMA config error, err=%d", ret);
1099 return -EINVAL;
1100 }
1101
1102 if (dma_start(data->dma_tc.dma_dev, data->dma_tc.dma_channel)) {
1103 LOG_ERR("Control DMA start failed");
1104 return -EFAULT;
1105 }
1106
1107 return 0;
1108 }
1109
i3c_stm32_dma_msg_status_fifo_config(const struct device * dev)1110 static int i3c_stm32_dma_msg_status_fifo_config(const struct device *dev)
1111 {
1112 struct i3c_stm32_data *data = dev->data;
1113 int ret;
1114
1115 data->dma_rs.blk_cfg.dest_address = (uint32_t)data->status_fifo;
1116 data->dma_rs.blk_cfg.block_size = data->fifo_len;
1117
1118 ret = dma_config(data->dma_rs.dma_dev, data->dma_rs.dma_channel, &data->dma_rs.dma_cfg);
1119
1120 if (ret != 0) {
1121 LOG_ERR("Status DMA config error, err=%d", ret);
1122 return -EINVAL;
1123 }
1124
1125 if (dma_start(data->dma_rs.dma_dev, data->dma_rs.dma_channel)) {
1126 LOG_ERR("Status DMA start failed");
1127 return -EFAULT;
1128 }
1129
1130 return 0;
1131 }
1132
i3c_stm32_dma_msg_config(const struct device * dev,uint32_t buf_addr,size_t buf_len)1133 static int i3c_stm32_dma_msg_config(const struct device *dev, uint32_t buf_addr, size_t buf_len)
1134 {
1135 struct i3c_stm32_dma_stream *dma_stream;
1136 struct i3c_stm32_data *data = dev->data;
1137 int ret;
1138
1139 if (i3c_stm32_curr_msg_xfer_is_read(dev)) {
1140 dma_stream = &(data->dma_rx);
1141 dma_stream->blk_cfg.dest_address = buf_addr;
1142 } else {
1143 dma_stream = &(data->dma_tx);
1144 dma_stream->blk_cfg.source_address = buf_addr;
1145 }
1146
1147 i3c_stm32_arbitration_header_config(dev);
1148
1149 dma_stream->blk_cfg.block_size = buf_len;
1150 ret = dma_config(dma_stream->dma_dev, dma_stream->dma_channel, &dma_stream->dma_cfg);
1151
1152 if (ret != 0) {
1153 LOG_ERR("TX/RX DMA config error, err=%d", ret);
1154 return -EINVAL;
1155 }
1156
1157 if (dma_start(dma_stream->dma_dev, dma_stream->dma_channel)) {
1158 LOG_ERR("TX/RX DMA start failed");
1159 return -EFAULT;
1160 }
1161 return 0;
1162 }
1163 #endif
1164
i3c_stm32_transfer_begin(const struct device * dev)1165 static int i3c_stm32_transfer_begin(const struct device *dev)
1166 {
1167 struct i3c_stm32_data *data = dev->data;
1168 const struct i3c_stm32_config *config = dev->config;
1169 I3C_TypeDef *i3c = config->i3c;
1170
1171 data->msg_state = STM32_I3C_MSG;
1172 data->sf_state = STM32_I3C_SF;
1173
1174 (void)pm_device_runtime_get(dev);
1175
1176 /* Prevent the clocks to be stopped during the transaction */
1177 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1178
1179 #ifdef CONFIG_I3C_STM32_DMA
1180 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
1181
1182 data->fifo_len = curr_msg->num_msgs * sizeof(uint32_t);
1183 data->control_fifo = k_heap_alloc(&stm32_i3c_fifo_heap, data->fifo_len, K_FOREVER);
1184 data->status_fifo = k_heap_alloc(&stm32_i3c_fifo_heap, data->fifo_len, K_FOREVER);
1185 int ret;
1186
1187 /* Prepare all control words for all messages on the transfer */
1188 for (size_t i = 0; i < curr_msg->num_msgs; i++) {
1189 WRITE_REG(data->control_fifo[i],
1190 ((curr_msg->target_addr << I3C_CR_ADD_Pos) |
1191 i3c_stm32_curr_msg_control_get_len(dev) |
1192 i3c_stm32_curr_msg_control_get_dir(dev) | curr_msg->msg_type |
1193 i3c_stm32_curr_msg_control_get_end(dev)) &
1194 (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE |
1195 I3C_CR_MEND));
1196
1197 i3c_stm32_curr_msg_control_next(dev);
1198 }
1199
1200 /* Configure DMA for the first message only, DMA callback will take care of the rest */
1201 uint8_t *buf = NULL;
1202 size_t *offset = 0;
1203 uint32_t len = 0;
1204
1205 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
1206
1207 ret = i3c_stm32_dma_msg_config(dev, (uint32_t)buf, len);
1208 if (ret != 0) {
1209 return ret;
1210 }
1211
1212 ret = i3c_stm32_dma_msg_control_fifo_config(dev);
1213 if (ret != 0) {
1214 return ret;
1215 }
1216
1217 ret = i3c_stm32_dma_msg_status_fifo_config(dev);
1218 if (ret != 0) {
1219 return ret;
1220 }
1221
1222 i3c_stm32_prepare_dma_requests(dev);
1223 #endif
1224
1225 /* Begin transmission */
1226 LL_I3C_RequestTransfer(i3c);
1227
1228 /* Wait for whole transfer to complete */
1229 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) {
1230 return -ETIMEDOUT;
1231 }
1232
1233 if (data->msg_state == STM32_I3C_MSG_ERR) {
1234 return -EIO;
1235 }
1236
1237 return 0;
1238 }
1239
1240 /* Handles the controller private read/write transfers */
i3c_stm32_i3c_transfer(const struct device * dev,struct i3c_device_desc * target,struct i3c_msg * msgs,uint8_t num_msgs)1241 static int i3c_stm32_i3c_transfer(const struct device *dev, struct i3c_device_desc *target,
1242 struct i3c_msg *msgs, uint8_t num_msgs)
1243 {
1244 struct i3c_stm32_data *data = dev->data;
1245 int ret;
1246
1247 /* Verify all messages */
1248 for (size_t i = 0; i < num_msgs; i++) {
1249 if (msgs[i].buf == NULL) {
1250 return -EINVAL;
1251 }
1252 if ((msgs[i].flags & I3C_MSG_HDR) && (msgs[i].hdr_mode != 0)) {
1253 return -ENOTSUP;
1254 }
1255 }
1256
1257 k_mutex_lock(&data->bus_mutex, K_FOREVER);
1258 ret = i3c_stm32_curr_msg_init(dev, msgs, NULL, num_msgs, target->dynamic_addr);
1259 if (ret != 0) {
1260 i3c_stm32_clear_err(dev, false);
1261 LOG_ERR("Failed to initialize transfer messages, err=%d", ret);
1262 return ret;
1263 }
1264
1265 ret = i3c_stm32_transfer_begin(dev);
1266 if (ret != 0) {
1267 i3c_stm32_clear_err(dev, false);
1268 LOG_ERR("Failed to transfer messages, err=%d", ret);
1269 return ret;
1270 }
1271
1272 #ifdef CONFIG_I3C_STM32_DMA
1273 /* Fill the num_xfer for each message from the status FIFO */
1274 for (size_t i = 0; i < num_msgs; i++) {
1275 msgs[i].num_xfer = READ_BIT(data->status_fifo[i], I3C_SR_XDCNT);
1276 }
1277
1278 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo);
1279 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo);
1280
1281 i3c_stm32_end_dma_requests(dev);
1282 #endif
1283
1284 k_mutex_unlock(&data->bus_mutex);
1285
1286 return 0;
1287 }
1288
i3c_stm32_i2c_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)1289 static int i3c_stm32_i2c_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
1290 uint16_t addr)
1291 {
1292 struct i3c_stm32_data *data = dev->data;
1293 const struct i3c_stm32_config *config = dev->config;
1294 I3C_TypeDef *i3c = config->i3c;
1295 int ret;
1296
1297 /* Verify all messages */
1298 for (size_t i = 0; i < num_msgs; i++) {
1299 if (msgs[i].buf == NULL) {
1300 return -EINVAL;
1301 }
1302 if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) {
1303 LOG_ERR("10-bit addressing mode is not supported");
1304 return -ENOTSUP;
1305 }
1306 }
1307
1308 k_mutex_lock(&data->bus_mutex, K_FOREVER);
1309
1310 /* Disable arbitration header for all I2C messages in case no I3C devices exist on bus */
1311 LL_I3C_DisableArbitrationHeader(i3c);
1312
1313 ret = i3c_stm32_curr_msg_init(dev, NULL, msgs, num_msgs, addr);
1314 if (ret != 0) {
1315 i3c_stm32_clear_err(dev, false);
1316 LOG_ERR("Failed to initialize transfer messages, err=%d", ret);
1317 return ret;
1318 }
1319
1320 ret = i3c_stm32_transfer_begin(dev);
1321 if (ret != 0) {
1322 i3c_stm32_clear_err(dev, false);
1323 LOG_ERR("Failed to transfer messages, err=%d", ret);
1324 return ret;
1325 }
1326
1327 LL_I3C_EnableArbitrationHeader(i3c);
1328
1329 #ifdef CONFIG_I3C_STM32_DMA
1330 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo);
1331 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo);
1332
1333 i3c_stm32_end_dma_requests(dev);
1334 #endif
1335
1336 k_mutex_unlock(&data->bus_mutex);
1337
1338 return 0;
1339 }
1340
1341 #ifdef CONFIG_PM_DEVICE
i3c_stm32_suspend(const struct device * dev)1342 static int i3c_stm32_suspend(const struct device *dev)
1343 {
1344 int ret;
1345 const struct i3c_stm32_config *cfg = dev->config;
1346 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
1347
1348 /* Disable device clock. */
1349 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
1350 if (ret < 0) {
1351 LOG_ERR("failure disabling I3C clock");
1352 return ret;
1353 }
1354
1355 /* Move pins to sleep state */
1356 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
1357 if (ret == -ENOENT) {
1358 /* Warn but don't block suspend */
1359 LOG_WRN("I3C pinctrl sleep state not available");
1360 } else if (ret < 0) {
1361 return ret;
1362 }
1363
1364 return 0;
1365 }
1366
i3c_stm32_pm_action(const struct device * dev,enum pm_device_action action)1367 static int i3c_stm32_pm_action(const struct device *dev, enum pm_device_action action)
1368 {
1369 int err;
1370
1371 switch (action) {
1372 case PM_DEVICE_ACTION_RESUME:
1373 err = i3c_stm32_activate(dev);
1374 break;
1375 case PM_DEVICE_ACTION_SUSPEND:
1376 err = i3c_stm32_suspend(dev);
1377 break;
1378 default:
1379 return -ENOTSUP;
1380 }
1381
1382 return err;
1383 }
1384 #endif
1385
1386 #ifdef CONFIG_I3C_STM32_DMA
i3c_stm32_dma_stream_config(const struct device * dev,struct i3c_stm32_dma_stream * dma_stream,uint64_t src_addr,uint64_t dst_addr)1387 static int i3c_stm32_dma_stream_config(const struct device *dev,
1388 struct i3c_stm32_dma_stream *dma_stream, uint64_t src_addr,
1389 uint64_t dst_addr)
1390 {
1391 if (dma_stream->dma_dev != NULL) {
1392 if (!device_is_ready(dma_stream->dma_dev)) {
1393 return -ENODEV;
1394 }
1395 }
1396
1397 memset(&dma_stream->blk_cfg, 0, sizeof(dma_stream->blk_cfg));
1398
1399 dma_stream->blk_cfg.source_address = src_addr;
1400
1401 dma_stream->blk_cfg.dest_address = dst_addr;
1402
1403 if (dma_stream->src_addr_increment) {
1404 dma_stream->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
1405 } else {
1406 dma_stream->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
1407 }
1408
1409 if (dma_stream->dst_addr_increment) {
1410 dma_stream->blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
1411 } else {
1412 dma_stream->blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
1413 }
1414
1415 dma_stream->blk_cfg.source_reload_en = 0;
1416 dma_stream->blk_cfg.dest_reload_en = 0;
1417 dma_stream->blk_cfg.fifo_mode_control = dma_stream->fifo_threshold;
1418
1419 dma_stream->dma_cfg.head_block = &dma_stream->blk_cfg;
1420 dma_stream->dma_cfg.user_data = (void *)dev;
1421
1422 return 0;
1423 }
1424
1425 /* Initializes the I3C DMA */
i3c_stm32_init_dma(const struct device * dev)1426 static int i3c_stm32_init_dma(const struct device *dev)
1427 {
1428 struct i3c_stm32_data *data = dev->data;
1429 int err;
1430 const struct i3c_stm32_config *config = dev->config;
1431 I3C_TypeDef *i3c = config->i3c;
1432
1433 /*Configure DMA RX */
1434 err = i3c_stm32_dma_stream_config(
1435 dev, &data->dma_rx, LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_RECEIVE_BYTE),
1436 0);
1437 if (err != 0) {
1438 return err;
1439 }
1440
1441 /*Configure DMA RS */
1442 err = i3c_stm32_dma_stream_config(dev, &data->dma_rs,
1443 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_STATUS), 0);
1444 if (err != 0) {
1445 return err;
1446 }
1447
1448 /*Configure DMA TX */
1449 err = i3c_stm32_dma_stream_config(
1450 dev, &data->dma_tx, 0,
1451 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE));
1452 if (err != 0) {
1453 return err;
1454 }
1455
1456 /*Configure DMA TC */
1457 err = i3c_stm32_dma_stream_config(dev, &data->dma_tc, 0,
1458 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_CONTROL));
1459 if (err != 0) {
1460 return err;
1461 }
1462
1463 return err;
1464 }
1465 #endif
1466
i3c_stm32_controller_init(const struct device * dev)1467 static void i3c_stm32_controller_init(const struct device *dev)
1468 {
1469 struct i3c_stm32_data *data = dev->data;
1470 const struct i3c_stm32_config *config = dev->config;
1471 I3C_TypeDef *i3c = config->i3c;
1472
1473 /* Configure FIFO */
1474 LL_I3C_SetRxFIFOThreshold(i3c, LL_I3C_RXFIFO_THRESHOLD_1_4);
1475 LL_I3C_SetTxFIFOThreshold(i3c, LL_I3C_TXFIFO_THRESHOLD_1_4);
1476 LL_I3C_EnableControlFIFO(i3c);
1477 LL_I3C_EnableStatusFIFO(i3c);
1478
1479 /* I3C Initialization */
1480 LL_I3C_SetMode(i3c, LL_I3C_MODE_CONTROLLER);
1481 LL_I3C_SetStallTime(i3c, 0x00);
1482 LL_I3C_DisableStallACK(i3c);
1483 LL_I3C_DisableStallParityCCC(i3c);
1484 LL_I3C_DisableStallParityData(i3c);
1485 LL_I3C_DisableStallTbit(i3c);
1486 LL_I3C_DisableHighKeeperSDA(i3c);
1487 LL_I3C_SetControllerActivityState(i3c, LL_I3C_OWN_ACTIVITY_STATE_0);
1488
1489 LL_I3C_Enable(i3c);
1490
1491 LL_I3C_EnableIT_FC(i3c);
1492 LL_I3C_EnableIT_CFNF(i3c);
1493 LL_I3C_EnableIT_SFNE(i3c);
1494 LL_I3C_EnableIT_RXFNE(i3c);
1495 LL_I3C_EnableIT_TXFNF(i3c);
1496 LL_I3C_EnableIT_ERR(i3c);
1497 LL_I3C_EnableIT_WKP(i3c);
1498
1499 #ifdef CONFIG_I3C_USE_IBI
1500 LL_I3C_EnableIT_IBI(i3c);
1501 LL_I3C_EnableIT_HJ(i3c);
1502 #endif
1503
1504 /* Bus will be idle initially */
1505 data->msg_state = STM32_I3C_MSG_IDLE;
1506 data->sf_state = STM32_I3C_SF_IDLE;
1507 data->target_id = 0;
1508 #ifdef CONFIG_I3C_USE_IBI
1509 data->ibi_payload = 0;
1510 data->ibi_payload_size = 0;
1511 data->ibi_target_addr = 0;
1512 #endif
1513 }
1514
1515 /* Initializes the I3C device and I3C bus */
i3c_stm32_init(const struct device * dev)1516 static int i3c_stm32_init(const struct device *dev)
1517 {
1518 const struct i3c_stm32_config *config = dev->config;
1519 struct i3c_stm32_data *data = dev->data;
1520 I3C_TypeDef *i3c = config->i3c;
1521 int ret;
1522
1523 #ifdef CONFIG_I3C_STM32_DMA
1524 ret = i3c_stm32_init_dma(dev);
1525
1526 if (ret != 0) {
1527 LOG_ERR("Failed to init I3C DMA, err=%d", ret);
1528 return ret;
1529 }
1530 #endif
1531
1532 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1533
1534 /* initialize mutex used when multiple transfers
1535 * are taking place to guarantee that each one is
1536 * atomic and has exclusive access to the I3C bus.
1537 */
1538 k_mutex_init(&data->bus_mutex);
1539
1540 /* initialize semaphore used when multiple ibi requests are taking place */
1541 #ifdef CONFIG_I3C_USE_IBI
1542 k_sem_init(&data->ibi_lock_sem, 1, 1);
1543 #endif
1544 ret = i3c_addr_slots_init(dev);
1545 if (ret != 0) {
1546 LOG_ERR("Addr slots init fail, err=%d", ret);
1547 return ret;
1548 }
1549
1550 config->irq_config_func(dev);
1551 i3c_stm32_configure(dev, I3C_CONFIG_CONTROLLER, &data->drv_data.ctrl_config);
1552 i3c_stm32_controller_init(dev);
1553
1554 /* Perform bus initialization only if there are devices that already exist on the bus */
1555 if (config->drv_cfg.dev_list.num_i3c > 0) {
1556 ret = i3c_bus_init(dev, &config->drv_cfg.dev_list);
1557 if (ret != 0) {
1558 LOG_ERR("Failed to do i3c bus init, err=%d", ret);
1559 return ret;
1560 }
1561 }
1562
1563 #ifdef CONFIG_I3C_USE_IBI
1564 LL_I3C_EnableHJAck(i3c);
1565 #endif
1566
1567 return 0;
1568 }
1569
i3c_stm32_event_isr_tx(const struct device * dev)1570 static void i3c_stm32_event_isr_tx(const struct device *dev)
1571 {
1572 const struct i3c_stm32_config *config = dev->config;
1573 struct i3c_stm32_data *data = dev->data;
1574 I3C_TypeDef *i3c = config->i3c;
1575
1576 switch (data->msg_state) {
1577 case STM32_I3C_MSG: {
1578 uint8_t *buf = NULL;
1579 size_t *offset = NULL;
1580 uint32_t len = 0;
1581
1582 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
1583
1584 if (i3c_stm32_fill_tx_fifo(dev, buf, len, offset)) {
1585 i3c_stm32_curr_msg_xfer_next(dev);
1586 }
1587
1588 break;
1589 }
1590 case STM32_I3C_MSG_DAA: {
1591 struct i3c_device_desc *target;
1592 uint8_t bcr;
1593 uint8_t dcr;
1594 uint8_t dyn_addr = 0;
1595 int ret;
1596
1597 bcr = (data->pid >> 8) & 0xFF;
1598 dcr = data->pid & 0xFF;
1599 data->pid >>= 16;
1600
1601 /* Find the device in the device list */
1602 ret = i3c_dev_list_daa_addr_helper(&data->drv_data.attached_dev.addr_slots,
1603 &config->drv_cfg.dev_list, data->pid, false,
1604 false, &target, &dyn_addr);
1605 if (ret != 0) {
1606 /* TODO: figure out what is the correct sequence to exit form this error
1607 * It is expected that a TX overrun error to occur which triggers err isr
1608 */
1609 LOG_ERR("No dynamic address could be assigned to target");
1610
1611 return;
1612 }
1613
1614 /* Put the new dynamic address in TX FIFO for transmission */
1615 LL_I3C_TransmitData8(i3c, dyn_addr);
1616
1617 if (target != NULL) {
1618 /* Update target descriptor */
1619 target->dynamic_addr = dyn_addr;
1620 target->bcr = bcr;
1621 target->dcr = dcr;
1622 }
1623
1624 /* Mark the address as used */
1625 i3c_addr_slots_mark_i3c(&data->drv_data.attached_dev.addr_slots, dyn_addr);
1626
1627 /* Mark the static address as free */
1628 if ((target != NULL) && (target->static_addr != 0) &&
1629 (dyn_addr != target->static_addr)) {
1630 i3c_addr_slots_mark_free(&data->drv_data.attached_dev.addr_slots, dyn_addr);
1631 }
1632
1633 break;
1634 }
1635 case STM32_I3C_MSG_CCC: {
1636 struct i3c_ccc_payload *payload = data->ccc_payload;
1637
1638 if (payload->ccc.num_xfer < payload->ccc.data_len) {
1639 LL_I3C_TransmitData8(i3c, payload->ccc.data[payload->ccc.num_xfer++]);
1640 }
1641 break;
1642 }
1643 case STM32_I3C_MSG_CCC_P2: {
1644 struct i3c_ccc_target_payload *target = data->ccc_target_payload;
1645
1646 if (target->num_xfer < target->data_len) {
1647 LL_I3C_TransmitData8(i3c, target->data[target->num_xfer++]);
1648
1649 /* After sending all bytes for current target, move on to the next target */
1650 if (target->num_xfer == target->data_len) {
1651 data->ccc_target_payload++;
1652 }
1653 }
1654 break;
1655 }
1656 default:
1657 break;
1658 }
1659 }
1660
i3c_stm32_event_isr_rx(const struct device * dev)1661 static void i3c_stm32_event_isr_rx(const struct device *dev)
1662 {
1663 const struct i3c_stm32_config *config = dev->config;
1664 struct i3c_stm32_data *data = dev->data;
1665 I3C_TypeDef *i3c = config->i3c;
1666
1667 switch (data->msg_state) {
1668 case STM32_I3C_MSG: {
1669 uint8_t *buf = NULL;
1670 size_t *offset = NULL;
1671 uint32_t len = 0;
1672
1673 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
1674 if (i3c_stm32_drain_rx_fifo(dev, buf, len, offset)) {
1675 i3c_stm32_curr_msg_xfer_next(dev);
1676 }
1677
1678 break;
1679 }
1680 case STM32_I3C_MSG_DAA: {
1681 data->pid <<= 8;
1682 data->pid |= LL_I3C_ReceiveData8(i3c);
1683
1684 data->daa_rx_rcv++;
1685
1686 /* After receiving 8 PID bytes from DAA, enable TXFNF interrupt to send the dynamic
1687 * address
1688 */
1689 if (data->daa_rx_rcv == 8) {
1690 LL_I3C_EnableIT_TXFNF(i3c);
1691 data->daa_rx_rcv = 0;
1692 }
1693 break;
1694 }
1695 case STM32_I3C_MSG_CCC_P2: {
1696 struct i3c_ccc_target_payload *target = data->ccc_target_payload;
1697
1698 if (target->num_xfer < target->data_len) {
1699 target->data[target->num_xfer++] = LL_I3C_ReceiveData8(i3c);
1700
1701 /* After receiving all bytes for current target, move on to the next target
1702 */
1703 if (target->num_xfer == target->data_len) {
1704 data->ccc_target_payload++;
1705 }
1706 }
1707 break;
1708 }
1709 default:
1710 break;
1711 }
1712 }
1713
i3c_stm32_event_isr_cf(const struct device * dev)1714 static void i3c_stm32_event_isr_cf(const struct device *dev)
1715 {
1716 const struct i3c_stm32_config *config = dev->config;
1717 struct i3c_stm32_data *data = dev->data;
1718 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
1719 I3C_TypeDef *i3c = config->i3c;
1720
1721 switch (data->msg_state) {
1722 case STM32_I3C_MSG: {
1723 LL_I3C_ControllerHandleMessage(
1724 i3c, curr_msg->target_addr, i3c_stm32_curr_msg_control_get_len(dev),
1725 i3c_stm32_curr_msg_control_get_dir(dev), curr_msg->msg_type,
1726 i3c_stm32_curr_msg_control_get_end(dev));
1727
1728 i3c_stm32_curr_msg_control_next(dev);
1729 break;
1730 }
1731 case STM32_I3C_MSG_CCC:
1732 case STM32_I3C_MSG_CCC_P2: {
1733 struct i3c_ccc_payload *payload = data->ccc_payload;
1734 struct i3c_ccc_target_payload *target;
1735
1736 if (data->ccc_target_idx < payload->targets.num_targets) {
1737 target = &payload->targets.payloads[data->ccc_target_idx++];
1738
1739 LL_I3C_ControllerHandleMessage(
1740 i3c, target->addr, target->data_len,
1741 target->rnw ? LL_I3C_DIRECTION_READ : LL_I3C_DIRECTION_WRITE,
1742 LL_I3C_CONTROLLER_MTYPE_DIRECT,
1743 (data->ccc_target_idx == payload->targets.num_targets)
1744 ? LL_I3C_GENERATE_STOP
1745 : LL_I3C_GENERATE_RESTART);
1746
1747 /* Change state to second part of CCC communication */
1748 if (data->msg_state == STM32_I3C_MSG_CCC) {
1749 data->msg_state = STM32_I3C_MSG_CCC_P2;
1750 }
1751 }
1752 break;
1753 }
1754 default:
1755 break;
1756 }
1757 }
1758
1759 /* Handles the I3C event ISR */
i3c_stm32_event_isr(void * arg)1760 static void i3c_stm32_event_isr(void *arg)
1761 {
1762 const struct device *dev = (const struct device *)arg;
1763
1764 const struct i3c_stm32_config *config = dev->config;
1765 struct i3c_stm32_data *data = dev->data;
1766 I3C_TypeDef *i3c = config->i3c;
1767
1768 /* TX FIFO not full handler */
1769 if (LL_I3C_IsActiveFlag_TXFNF(i3c) && LL_I3C_IsEnabledIT_TXFNF(i3c)) {
1770 i3c_stm32_event_isr_tx(dev);
1771 }
1772
1773 /* RX FIFO not empty handler */
1774 if (LL_I3C_IsActiveFlag_RXFNE(i3c) && LL_I3C_IsEnabledIT_RXFNE(i3c)) {
1775 i3c_stm32_event_isr_rx(dev);
1776 }
1777
1778 /* Control FIFO not full handler */
1779 if (LL_I3C_IsActiveFlag_CFNF(i3c) && LL_I3C_IsEnabledIT_CFNF(i3c)) {
1780 i3c_stm32_event_isr_cf(dev);
1781 }
1782
1783 /* Status FIFO not empty handler */
1784 if (LL_I3C_IsActiveFlag_SFNE(i3c) && LL_I3C_IsEnabledIT_SFNE(i3c)) {
1785
1786 if (data->msg_state == STM32_I3C_MSG) {
1787 size_t num_xfer = LL_I3C_GetXferDataCount(i3c);
1788
1789 i3c_stm32_curr_msg_status_update_num_xfer(dev, num_xfer);
1790 i3c_stm32_curr_msg_status_next(dev);
1791 } else {
1792 /* Read and discard the status FIFO word since it will not be used */
1793 uint32_t status_reg = i3c->SR;
1794
1795 ARG_UNUSED(status_reg);
1796 }
1797 }
1798
1799 /* Target read early termination flag (only used during CCC commands)*/
1800 if (LL_I3C_IsActiveFlag_RXTGTEND(i3c) && LL_I3C_IsEnabledIT_RXTGTEND(i3c)) {
1801 /* A target ended a read request early during a CCC command, move the ptr to the
1802 * next target
1803 */
1804 data->ccc_target_payload++;
1805 LL_I3C_ClearFlag_RXTGTEND(i3c);
1806 }
1807
1808 /* Frame complete handler */
1809 if (LL_I3C_IsActiveFlag_FC(i3c) && LL_I3C_IsEnabledIT_FC(i3c)) {
1810 LL_I3C_ClearFlag_FC(i3c);
1811 k_sem_give(&data->device_sync_sem);
1812
1813 (void)pm_device_runtime_put(dev);
1814 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1815
1816 /* Mark bus as idle after each frame complete */
1817 data->msg_state = STM32_I3C_MSG_IDLE;
1818 }
1819
1820 #ifdef CONFIG_I3C_USE_IBI
1821
1822 k_sem_take(&data->ibi_lock_sem, K_FOREVER);
1823
1824 if (LL_I3C_IsActiveFlag_IBI(i3c)) {
1825 /* Clear frame complete flag */
1826 LL_I3C_ClearFlag_IBI(i3c);
1827 data->ibi_payload = LL_I3C_GetIBIPayload(i3c);
1828 data->ibi_payload_size = LL_I3C_GetNbIBIAddData(i3c);
1829 data->ibi_target_addr = LL_I3C_GetIBITargetAddr(i3c);
1830 if ((data->ibi_payload == 0) && (data->ibi_payload_size == 0) &&
1831 (data->ibi_target_addr == 0)) {
1832 LOG_ERR("Invalid Payload\n");
1833 } else {
1834 LOG_INF("IBI done, payload received :%d,%d,%d\n", data->ibi_payload,
1835 data->ibi_payload_size, data->ibi_target_addr);
1836 if ((data->ibi_payload != 0) && (data->ibi_payload_size != 0)) {
1837 struct i3c_device_desc *target;
1838
1839 target = i3c_dev_list_i3c_addr_find(dev, data->ibi_target_addr);
1840
1841 if (target != NULL) {
1842 if (i3c_ibi_work_enqueue_target_irq(
1843 target, (uint8_t *)&data->ibi_payload,
1844 data->ibi_payload_size) != 0) {
1845 LOG_ERR("Error enqueue IBI IRQ work");
1846 }
1847 } else {
1848 LOG_ERR("IBI from unknown device addr 0x%x",
1849 data->ibi_target_addr);
1850 }
1851 }
1852 }
1853 }
1854
1855 if (LL_I3C_IsActiveFlag_HJ(i3c)) {
1856 int ret;
1857
1858 LL_I3C_ClearFlag_HJ(i3c);
1859
1860 ret = i3c_ibi_work_enqueue_hotjoin(dev);
1861 if (ret != 0) {
1862 LOG_ERR("IBI Failed to enqueue hotjoin work");
1863 }
1864 }
1865
1866 k_sem_give(&data->ibi_lock_sem);
1867
1868 #endif
1869
1870 if (LL_I3C_IsActiveFlag_WKP(i3c)) {
1871 LL_I3C_ClearFlag_WKP(i3c);
1872 }
1873 }
1874
1875 /* Handles the I3C error ISR */
i3c_stm32_error_isr(void * arg)1876 static void i3c_stm32_error_isr(void *arg)
1877 {
1878 const struct device *dev = (const struct device *)arg;
1879
1880 const struct i3c_stm32_config *config = dev->config;
1881 struct i3c_stm32_data *data = dev->data;
1882 I3C_TypeDef *i3c = config->i3c;
1883
1884 i3c_stm32_log_err_type(dev);
1885
1886 LL_I3C_ClearFlag_ERR(i3c);
1887
1888 data->msg_state = STM32_I3C_MSG_ERR;
1889
1890 k_sem_give(&data->device_sync_sem);
1891
1892 (void)pm_device_runtime_put(dev);
1893 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1894 }
1895
1896 #ifdef CONFIG_I3C_USE_IBI
1897
i3c_stm32_ibi_enable(const struct device * dev,struct i3c_device_desc * target)1898 int i3c_stm32_ibi_enable(const struct device *dev, struct i3c_device_desc *target)
1899 {
1900 int ret = 0;
1901 uint8_t idx;
1902 I3C_TypeDef *i3c;
1903 struct i3c_ccc_events i3c_events;
1904 struct i3c_stm32_data *data = dev->data;
1905 const struct i3c_stm32_config *config = dev->config;
1906
1907 i3c = config->i3c;
1908 if (!i3c_device_is_ibi_capable(target)) {
1909 return -EINVAL;
1910 }
1911
1912 if (data->ibi.num_addr >= ARRAY_SIZE(data->ibi.addr)) {
1913 /* No more free entries in the IBI table */
1914 LOG_ERR("%s: no more free space in the IBI table", __func__);
1915 return -ENOMEM;
1916 }
1917
1918 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) {
1919 if (data->ibi.addr[idx] == target->dynamic_addr) {
1920 LOG_ERR("%s: selected target is already in the list", __func__);
1921 return -EINVAL;
1922 }
1923 }
1924
1925 if (data->ibi.num_addr > 0) {
1926 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) {
1927 if (data->ibi.addr[idx] == 0U) {
1928 break;
1929 }
1930 }
1931
1932 if (idx >= ARRAY_SIZE(data->ibi.addr)) {
1933 LOG_ERR("Cannot support more IBIs");
1934 return -ENOTSUP;
1935 }
1936
1937 } else {
1938 idx = 0;
1939 }
1940
1941 data->ibi.addr[idx] = target->dynamic_addr;
1942 data->ibi.num_addr += 1U;
1943
1944 if (data->ibi.num_addr == 1U) {
1945 (void)pm_device_runtime_get(dev);
1946 }
1947
1948 /* Tell target to enable IBI */
1949 i3c_events.events = I3C_CCC_EVT_INTR;
1950 ret = i3c_ccc_do_events_set(target, true, &i3c_events);
1951 if (ret != 0) {
1952 LOG_ERR("Error sending IBI ENEC for 0x%02x (%d)", target->dynamic_addr, ret);
1953 }
1954
1955 /* Set I3C bus devices configuration */
1956 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr,
1957 LL_I3C_IBI_CAPABILITY,
1958 i3c_ibi_has_payload(target) ? LL_I3C_IBI_DATA_ENABLE
1959 : LL_I3C_IBI_DATA_DISABLE,
1960 LL_I3C_CR_NO_CAPABILITY);
1961
1962 return ret;
1963 }
1964
i3c_stm32_ibi_disable(const struct device * dev,struct i3c_device_desc * target)1965 int i3c_stm32_ibi_disable(const struct device *dev, struct i3c_device_desc *target)
1966 {
1967 int ret = 0;
1968 uint8_t idx;
1969 I3C_TypeDef *i3c;
1970 struct i3c_ccc_events i3c_events;
1971 struct i3c_stm32_data *data = dev->data;
1972 const struct i3c_stm32_config *config = dev->config;
1973
1974 i3c = config->i3c;
1975 if (!i3c_device_is_ibi_capable(target)) {
1976 return -EINVAL;
1977 }
1978
1979 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) {
1980 if (target->dynamic_addr == data->ibi.addr[idx]) {
1981 break;
1982 }
1983 }
1984
1985 if (idx == ARRAY_SIZE(data->ibi.addr)) {
1986 LOG_ERR("%s: target is not in list of registered addresses", __func__);
1987 return -ENODEV;
1988 }
1989
1990 data->ibi.addr[idx] = 0U;
1991 data->ibi.num_addr -= 1U;
1992
1993 if (data->ibi.num_addr == 0U) {
1994 (void)pm_device_runtime_put(dev);
1995 }
1996
1997 /* Tell target to disable IBI */
1998 i3c_events.events = I3C_CCC_EVT_INTR;
1999 ret = i3c_ccc_do_events_set(target, false, &i3c_events);
2000 if (ret != 0) {
2001 LOG_ERR("Error sending IBI DISEC for 0x%02x (%d)", target->dynamic_addr, ret);
2002 }
2003
2004 /* Set I3C bus devices configuration */
2005 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr,
2006 LL_I3C_IBI_NO_CAPABILITY,
2007 LL_I3C_IBI_DATA_DISABLE,
2008 LL_I3C_CR_NO_CAPABILITY);
2009
2010 return ret;
2011 }
2012
2013 #endif /* CONFIG_I3C_USE_IBI */
2014
2015 #ifdef CONFIG_I3C_STM32_DMA
i3c_stm32_tx_rx_msg_config(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2016 static void i3c_stm32_tx_rx_msg_config(const struct device *dma_dev, void *user_data,
2017 uint32_t channel, int status)
2018 {
2019 const struct device *dev = (const struct device *)user_data;
2020
2021 if (i3c_stm32_curr_msg_xfer_next(dev) != 0) {
2022 /* No more messages to transmit/receive */
2023 return;
2024 }
2025
2026 uint8_t *buf = NULL;
2027 size_t *offset = 0;
2028 uint32_t len = 0;
2029
2030 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
2031 i3c_stm32_dma_msg_config(dev, (uint32_t)buf, len);
2032 }
2033
i3c_stm32_dma_tx_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2034 static void i3c_stm32_dma_tx_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2035 int status)
2036 {
2037 i3c_stm32_tx_rx_msg_config(dma_dev, user_data, channel, status);
2038 }
2039
i3c_stm32_dma_rx_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2040 static void i3c_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2041 int status)
2042 {
2043 i3c_stm32_tx_rx_msg_config(dma_dev, user_data, channel, status);
2044 }
2045
i3c_stm32_dma_tc_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2046 static void i3c_stm32_dma_tc_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2047 int status)
2048 {
2049 }
2050
i3c_stm32_dma_rs_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2051 static void i3c_stm32_dma_rs_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2052 int status)
2053 {
2054 }
2055
2056 #endif
2057
2058 static DEVICE_API(i3c, i3c_stm32_driver_api) = {
2059 .i2c_api.configure = i3c_stm32_i2c_configure,
2060 .i2c_api.transfer = i3c_stm32_i2c_transfer,
2061 #ifdef CONFIG_I2C_RTIO
2062 .i2c_api.iodev_submit = i2c_iodev_submit_fallback,
2063 #endif
2064 .configure = i3c_stm32_configure,
2065 .config_get = i3c_stm32_config_get,
2066 .i3c_device_find = i3c_stm32_device_find,
2067 .i3c_xfers = i3c_stm32_i3c_transfer,
2068 .do_daa = i3c_stm32_do_daa,
2069 .do_ccc = i3c_stm32_do_ccc,
2070 #ifdef CONFIG_I3C_USE_IBI
2071 .ibi_enable = i3c_stm32_ibi_enable,
2072 .ibi_disable = i3c_stm32_ibi_disable,
2073 #endif
2074 #ifdef CONFIG_I3C_RTIO
2075 .iodev_submit = i3c_iodev_submit_fallback,
2076 #endif
2077 };
2078
2079 #ifdef CONFIG_I3C_STM32_DMA
2080 #define STM32_I3C_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \
2081 .dma_dev = DEVICE_DT_GET(STM32_DMA_CTLR(index, dir)), \
2082 .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
2083 .dma_cfg = \
2084 { \
2085 .dma_slot = STM32_DMA_SLOT(index, dir, slot), \
2086 .channel_direction = \
2087 STM32_DMA_CONFIG_DIRECTION(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2088 .channel_priority = \
2089 STM32_DMA_CONFIG_PRIORITY(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2090 .source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE( \
2091 STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2092 .dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE( \
2093 STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2094 .source_burst_length = 1, /* SINGLE transfer */ \
2095 .dest_burst_length = 1, \
2096 .block_count = 1, \
2097 .dma_callback = i3c_stm32_dma_##dir##_cb, \
2098 }, \
2099 .src_addr_increment = \
2100 STM32_DMA_CONFIG_##src_dev##_ADDR_INC(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2101 .dst_addr_increment = \
2102 STM32_DMA_CONFIG_##dest_dev##_ADDR_INC(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2103 .fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD(STM32_DMA_FEATURES(index, dir)),
2104
2105 #endif
2106
2107 #ifdef CONFIG_I3C_STM32_DMA
2108 #define STM32_I3C_DMA_CHANNEL(index, dir, DIR, src, dest) \
2109 .dma_##dir = {COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \
2110 (STM32_I3C_DMA_CHANNEL_INIT(index, dir, DIR, src, dest)), \
2111 (NULL))},
2112
2113 #else
2114 #define STM32_I3C_DMA_CHANNEL(index, dir, DIR, src, dest)
2115 #endif
2116
2117 #define STM32_I3C_IRQ_CONNECT_AND_ENABLE(index) \
2118 do { \
2119 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
2120 DT_INST_IRQ_BY_NAME(index, event, priority), i3c_stm32_event_isr, \
2121 DEVICE_DT_INST_GET(index), 0); \
2122 irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
2123 \
2124 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
2125 DT_INST_IRQ_BY_NAME(index, error, priority), i3c_stm32_error_isr, \
2126 DEVICE_DT_INST_GET(index), 0); \
2127 irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
2128 } while (false)
2129
2130 #define STM32_I3C_IRQ_HANDLER_DECL(index) \
2131 static void i3c_stm32_irq_config_func_##index(const struct device *dev)
2132
2133 #define STM32_I3C_IRQ_HANDLER_FUNCTION(index) .irq_config_func = i3c_stm32_irq_config_func_##index,
2134
2135 #define STM32_I3C_IRQ_HANDLER(index) \
2136 static void i3c_stm32_irq_config_func_##index(const struct device *dev) \
2137 { \
2138 STM32_I3C_IRQ_CONNECT_AND_ENABLE(index); \
2139 }
2140
2141 #define I3C_STM32_INIT(index) \
2142 STM32_I3C_IRQ_HANDLER_DECL(index); \
2143 \
2144 static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index); \
2145 PINCTRL_DT_INST_DEFINE(index); \
2146 static struct i3c_device_desc i3c_stm32_dev_arr_##index[] = \
2147 I3C_DEVICE_ARRAY_DT_INST(index); \
2148 static struct i3c_i2c_device_desc i3c_i2c_stm32_dev_arr_##index[] = \
2149 I3C_I2C_DEVICE_ARRAY_DT_INST(index); \
2150 \
2151 static const struct i3c_stm32_config i3c_stm32_cfg_##index = { \
2152 .i3c = (I3C_TypeDef *)DT_INST_REG_ADDR(index), \
2153 STM32_I3C_IRQ_HANDLER_FUNCTION(index).pclken = pclken_##index, \
2154 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
2155 .drv_cfg.dev_list.i3c = i3c_stm32_dev_arr_##index, \
2156 .drv_cfg.dev_list.num_i3c = ARRAY_SIZE(i3c_stm32_dev_arr_##index), \
2157 .drv_cfg.dev_list.i2c = i3c_i2c_stm32_dev_arr_##index, \
2158 .drv_cfg.dev_list.num_i2c = ARRAY_SIZE(i3c_i2c_stm32_dev_arr_##index), \
2159 }; \
2160 \
2161 static struct i3c_stm32_data i3c_stm32_data_##index = { \
2162 .drv_data.ctrl_config.scl.i2c = DT_INST_PROP_OR(index, i2c_scl_hz, 0), \
2163 .drv_data.ctrl_config.scl.i3c = DT_INST_PROP_OR(index, i3c_scl_hz, 0), \
2164 STM32_I3C_DMA_CHANNEL(index, rx, RX, PERIPHERAL, MEMORY) \
2165 STM32_I3C_DMA_CHANNEL(index, tx, TX, MEMORY, PERIPHERAL) \
2166 STM32_I3C_DMA_CHANNEL(index, tc, TC, MEMORY, PERIPHERAL) \
2167 STM32_I3C_DMA_CHANNEL(index, rs, RS, PERIPHERAL, MEMORY)}; \
2168 \
2169 PM_DEVICE_DT_INST_DEFINE(index, i3c_stm32_pm_action); \
2170 \
2171 DEVICE_DT_INST_DEFINE(index, &i3c_stm32_init, PM_DEVICE_DT_INST_GET(index), \
2172 &i3c_stm32_data_##index, &i3c_stm32_cfg_##index, POST_KERNEL, \
2173 CONFIG_I3C_CONTROLLER_INIT_PRIORITY, &i3c_stm32_driver_api); \
2174 \
2175 STM32_I3C_IRQ_HANDLER(index)
2176
2177 DT_INST_FOREACH_STATUS_OKAY(I3C_STM32_INIT)
2178
