1 /*
2 * Copyright 2020,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_flexspi_nor
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/drivers/flash.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/sys/util.h>
14 #include "spi_nor.h"
15 #include "jesd216.h"
16 #include "memc_mcux_flexspi.h"
17
18 #ifdef CONFIG_HAS_MCUX_CACHE
19 #include <fsl_cache.h>
20 #endif
21
22 #define NOR_WRITE_SIZE 1
23 #define NOR_ERASE_VALUE 0xff
24
25 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
26 static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
27 #endif
28
29 /*
30 * NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
31 * called while interacting with the flexspi MUST be relocated to SRAM or ITCM
32 * at runtime, so that the chip does not access the flexspi to read program
33 * instructions while it is being written to
34 *
35 * Additionally, no data used by this driver should be stored in flash.
36 */
37 #if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0)
38 #warning "Enabling flash driver logging and XIP mode simultaneously can cause \
39 read-while-write hazards. This configuration is not recommended."
40 #endif
41
42 LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
43
44 enum {
45 READ,
46 PAGE_PROGRAM,
47 READ_STATUS,
48 WRITE_ENABLE,
49 ERASE_SECTOR,
50 ERASE_BLOCK,
51 READ_ID,
52 READ_STATUS_REG,
53 ERASE_CHIP,
54 READ_JESD216,
55 /* Entries after this should be for scratch commands */
56 FLEXSPI_INSTR_PROG_END,
57 /* Used for temporary commands during initialization */
58 SCRATCH_CMD = FLEXSPI_INSTR_PROG_END,
59 SCRATCH_CMD2,
60 /* Must be last entry */
61 FLEXSPI_INSTR_END,
62 };
63
64 struct flash_flexspi_nor_config {
65 /* Note: don't use this controller reference in code. It is
66 * only used during init to copy the device structure from ROM
67 * into a RAM structure
68 */
69 const struct device *controller;
70 };
71
72 /* Device variables used in critical sections should be in this structure */
73 struct flash_flexspi_nor_data {
74 struct device controller;
75 flexspi_device_config_t config;
76 flexspi_port_t port;
77 bool legacy_poll;
78 uint64_t size;
79 struct flash_pages_layout layout;
80 struct flash_parameters flash_parameters;
81 };
82
83 /*
84 * FLEXSPI LUT buffer used during configuration. Stored in .data to avoid
85 * using too much stack
86 */
87 static uint32_t flexspi_probe_lut[FLEXSPI_INSTR_END][MEMC_FLEXSPI_CMD_PER_SEQ] = {0};
88
89 /* Initial LUT table */
90 static const uint32_t flash_flexspi_nor_base_lut[][MEMC_FLEXSPI_CMD_PER_SEQ] = {
91 /* 1S-1S-1S flash read command, should be compatible with all SPI nor flashes */
92 [READ] = {
93 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_READ,
94 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
95 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1,
96 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
97 },
98 [READ_JESD216] = {
99 /* Install read SFDP command */
100 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, JESD216_CMD_READ_SFDP,
101 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
102 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 8,
103 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x4),
104 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0,
105 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
106 },
107 /* Standard 1S-1S-1S flash write command, can be switched to 1S-1S-4S when QE is set */
108 [PAGE_PROGRAM] = {
109 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP,
110 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
111 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
112 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
113 },
114
115 [WRITE_ENABLE] = {
116 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WREN,
117 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
118 },
119
120 [ERASE_SECTOR] = {
121 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE,
122 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
123 },
124
125 [ERASE_BLOCK] = {
126 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE,
127 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
128 },
129
130 [ERASE_CHIP] = {
131 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_CE,
132 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
133 },
134
135 [READ_ID] = {
136 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDID,
137 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
138 },
139
140 [READ_STATUS_REG] = {
141 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
142 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
143 },
144 };
145
area_is_subregion(const struct device * dev,off_t offset,size_t size)146 static ALWAYS_INLINE bool area_is_subregion(const struct device *dev, off_t offset, size_t size)
147 {
148 struct flash_flexspi_nor_data *data = dev->data;
149
150 return ((offset >= 0) && (offset < data->size) &&
151 ((data->size - offset) >= size));
152 }
153
154 /* Helper so we can read flash ID without flash access for XIP */
flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data * data,uint8_t * vendor_id)155 static int flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data *data,
156 uint8_t *vendor_id)
157 {
158 uint32_t buffer = 0;
159 int ret;
160
161 flexspi_transfer_t transfer = {
162 .deviceAddress = 0,
163 .port = data->port,
164 .cmdType = kFLEXSPI_Read,
165 .SeqNumber = 1,
166 .seqIndex = READ_ID,
167 .data = &buffer,
168 .dataSize = 3,
169 };
170
171 LOG_DBG("Reading id");
172
173 ret = memc_flexspi_transfer(&data->controller, &transfer);
174 if (ret < 0) {
175 return ret;
176 }
177
178 memcpy(vendor_id, &buffer, 3);
179
180 return ret;
181 }
182
flash_flexspi_nor_read_id(const struct device * dev,uint8_t * vendor_id)183 static int flash_flexspi_nor_read_id(const struct device *dev, uint8_t *vendor_id)
184 {
185 struct flash_flexspi_nor_data *data = dev->data;
186
187 return flash_flexspi_nor_read_id_helper(data, vendor_id);
188 }
189
flash_flexspi_nor_read_status(struct flash_flexspi_nor_data * data,uint32_t * status)190 static int flash_flexspi_nor_read_status(struct flash_flexspi_nor_data *data,
191 uint32_t *status)
192 {
193 flexspi_transfer_t transfer = {
194 .deviceAddress = 0,
195 .port = data->port,
196 .cmdType = kFLEXSPI_Read,
197 .SeqNumber = 1,
198 .seqIndex = READ_STATUS_REG,
199 .data = status,
200 .dataSize = 1,
201 };
202
203 LOG_DBG("Reading status register");
204
205 return memc_flexspi_transfer(&data->controller, &transfer);
206 }
207
flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data * data)208 static int flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data *data)
209 {
210 flexspi_transfer_t transfer = {
211 .deviceAddress = 0,
212 .port = data->port,
213 .cmdType = kFLEXSPI_Command,
214 .SeqNumber = 1,
215 .seqIndex = WRITE_ENABLE,
216 .data = NULL,
217 .dataSize = 0,
218 };
219
220 LOG_DBG("Enabling write");
221
222 return memc_flexspi_transfer(&data->controller, &transfer);
223 }
224
flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data * data,off_t offset)225 static int flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data *data,
226 off_t offset)
227 {
228 flexspi_transfer_t transfer = {
229 .deviceAddress = offset,
230 .port = data->port,
231 .cmdType = kFLEXSPI_Command,
232 .SeqNumber = 1,
233 .seqIndex = ERASE_SECTOR,
234 .data = NULL,
235 .dataSize = 0,
236 };
237
238 LOG_DBG("Erasing sector at 0x%08zx", (ssize_t) offset);
239
240 return memc_flexspi_transfer(&data->controller, &transfer);
241 }
242
flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data * data,off_t offset)243 static int flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data *data,
244 off_t offset)
245 {
246 flexspi_transfer_t transfer = {
247 .deviceAddress = offset,
248 .port = data->port,
249 .cmdType = kFLEXSPI_Command,
250 .SeqNumber = 1,
251 .seqIndex = ERASE_BLOCK,
252 .data = NULL,
253 .dataSize = 0,
254 };
255
256 LOG_DBG("Erasing block at 0x%08zx", (ssize_t) offset);
257
258 return memc_flexspi_transfer(&data->controller, &transfer);
259 }
260
flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data * data)261 static int flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data *data)
262 {
263 flexspi_transfer_t transfer = {
264 .deviceAddress = 0,
265 .port = data->port,
266 .cmdType = kFLEXSPI_Command,
267 .SeqNumber = 1,
268 .seqIndex = ERASE_CHIP,
269 .data = NULL,
270 .dataSize = 0,
271 };
272
273 LOG_DBG("Erasing chip");
274
275 return memc_flexspi_transfer(&data->controller, &transfer);
276 }
277
flash_flexspi_nor_page_program(struct flash_flexspi_nor_data * data,off_t offset,const void * buffer,size_t len)278 static int flash_flexspi_nor_page_program(struct flash_flexspi_nor_data *data,
279 off_t offset, const void *buffer, size_t len)
280 {
281 flexspi_transfer_t transfer = {
282 .deviceAddress = offset,
283 .port = data->port,
284 .cmdType = kFLEXSPI_Write,
285 .SeqNumber = 1,
286 .seqIndex = PAGE_PROGRAM,
287 .data = (uint32_t *) buffer,
288 .dataSize = len,
289 };
290
291 LOG_DBG("Page programming %d bytes to 0x%08zx", len, (ssize_t) offset);
292
293 return memc_flexspi_transfer(&data->controller, &transfer);
294 }
295
flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data * data)296 static int flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data *data)
297 {
298 uint32_t status = 0;
299 int ret;
300
301 while (1) {
302 ret = flash_flexspi_nor_read_status(data, &status);
303 LOG_DBG("status: 0x%x", status);
304 if (ret) {
305 LOG_ERR("Could not read status");
306 return ret;
307 }
308
309 if (data->legacy_poll) {
310 if ((status & BIT(0)) == 0) {
311 break;
312 }
313 } else {
314 if (status & BIT(7)) {
315 break;
316 }
317 }
318 }
319
320 return 0;
321 }
322
flash_flexspi_nor_read(const struct device * dev,off_t offset,void * buffer,size_t len)323 static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
324 void *buffer, size_t len)
325 {
326 struct flash_flexspi_nor_data *data = dev->data;
327
328 if (!buffer) {
329 return -EINVAL;
330 }
331
332 if (!area_is_subregion(dev, offset, len)) {
333 return -EINVAL;
334 }
335
336 uint8_t *src = memc_flexspi_get_ahb_address(&data->controller,
337 data->port,
338 offset);
339
340 memcpy(buffer, src, len);
341
342 return 0;
343 }
344
flash_flexspi_nor_write(const struct device * dev,off_t offset,const void * buffer,size_t len)345 static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
346 const void *buffer, size_t len)
347 {
348 struct flash_flexspi_nor_data *data = dev->data;
349
350 if (!buffer) {
351 return -EINVAL;
352 }
353
354 if (!area_is_subregion(dev, offset, len)) {
355 return -EINVAL;
356 }
357
358 size_t size = len;
359 uint8_t *src = (uint8_t *) buffer;
360 int i;
361 unsigned int key = 0;
362
363 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
364 data->port,
365 offset);
366
367 if (memc_flexspi_is_running_xip(&data->controller)) {
368 /*
369 * ==== ENTER CRITICAL SECTION ====
370 * No flash access should be performed in critical section. All
371 * code and data accessed must reside in ram.
372 */
373 key = irq_lock();
374 memc_flexspi_wait_bus_idle(&data->controller);
375 }
376
377 while (len) {
378 /* If the offset isn't a multiple of the NOR page size, we first need
379 * to write the remaining part that fits, otherwise the write could
380 * be wrapped around within the same page
381 */
382 i = MIN(SPI_NOR_PAGE_SIZE - (offset % SPI_NOR_PAGE_SIZE), len);
383 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
384 memcpy(nor_write_buf, src, i);
385
386 /* As memcpy could cause an XIP access,
387 * we need to wait for XIP prefetch to be finished again
388 */
389 if (memc_flexspi_is_running_xip(&data->controller)) {
390 memc_flexspi_wait_bus_idle(&data->controller);
391 }
392 #endif
393 flash_flexspi_nor_write_enable(data);
394 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
395 flash_flexspi_nor_page_program(data, offset, nor_write_buf, i);
396 #else
397 flash_flexspi_nor_page_program(data, offset, src, i);
398 #endif
399 flash_flexspi_nor_wait_bus_busy(data);
400 memc_flexspi_reset(&data->controller);
401 src += i;
402 offset += i;
403 len -= i;
404 }
405
406 if (memc_flexspi_is_running_xip(&data->controller)) {
407 /* ==== EXIT CRITICAL SECTION ==== */
408 irq_unlock(key);
409 }
410
411 #ifdef CONFIG_HAS_MCUX_CACHE
412 DCACHE_InvalidateByRange((uint32_t) dst, size);
413 #endif
414
415 return 0;
416 }
417
flash_flexspi_nor_erase(const struct device * dev,off_t offset,size_t size)418 static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
419 size_t size)
420 {
421 struct flash_flexspi_nor_data *data = dev->data;
422
423 if (!area_is_subregion(dev, offset, size)) {
424 return -EINVAL;
425 }
426
427 const size_t num_sectors = size / SPI_NOR_SECTOR_SIZE;
428 const size_t num_blocks = size / SPI_NOR_BLOCK_SIZE;
429
430 int i;
431 unsigned int key = 0;
432
433 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
434 data->port,
435 offset);
436
437 if (offset % SPI_NOR_SECTOR_SIZE) {
438 LOG_ERR("Invalid offset");
439 return -EINVAL;
440 }
441
442 if (size % SPI_NOR_SECTOR_SIZE) {
443 LOG_ERR("Invalid size");
444 return -EINVAL;
445 }
446
447 if (memc_flexspi_is_running_xip(&data->controller)) {
448 /*
449 * ==== ENTER CRITICAL SECTION ====
450 * No flash access should be performed in critical section. All
451 * code and data accessed must reside in ram.
452 */
453 key = irq_lock();
454 memc_flexspi_wait_bus_idle(&data->controller);
455 }
456
457 if ((offset == 0) && (size == data->config.flashSize * KB(1))) {
458 flash_flexspi_nor_write_enable(data);
459 flash_flexspi_nor_erase_chip(data);
460 flash_flexspi_nor_wait_bus_busy(data);
461 memc_flexspi_reset(&data->controller);
462 } else if ((0 == (offset % SPI_NOR_BLOCK_SIZE)) && (0 == (size % SPI_NOR_BLOCK_SIZE))) {
463 for (i = 0; i < num_blocks; i++) {
464 flash_flexspi_nor_write_enable(data);
465 flash_flexspi_nor_erase_block(data, offset);
466 flash_flexspi_nor_wait_bus_busy(data);
467 memc_flexspi_reset(&data->controller);
468 offset += SPI_NOR_BLOCK_SIZE;
469 }
470 } else {
471 for (i = 0; i < num_sectors; i++) {
472 flash_flexspi_nor_write_enable(data);
473 flash_flexspi_nor_erase_sector(data, offset);
474 flash_flexspi_nor_wait_bus_busy(data);
475 memc_flexspi_reset(&data->controller);
476 offset += SPI_NOR_SECTOR_SIZE;
477 }
478 }
479
480 if (memc_flexspi_is_running_xip(&data->controller)) {
481 /* ==== EXIT CRITICAL SECTION ==== */
482 irq_unlock(key);
483 }
484
485 #ifdef CONFIG_HAS_MCUX_CACHE
486 DCACHE_InvalidateByRange((uint32_t) dst, size);
487 #endif
488
489 return 0;
490 }
491
flash_flexspi_nor_get_parameters(const struct device * dev)492 static const struct flash_parameters *flash_flexspi_nor_get_parameters(
493 const struct device *dev)
494 {
495 struct flash_flexspi_nor_data *data = dev->data;
496
497 return &data->flash_parameters;
498 }
499
flash_flexspi_nor_get_size(const struct device * dev,uint64_t * size)500 static int flash_flexspi_nor_get_size(const struct device *dev, uint64_t *size)
501 {
502 struct flash_flexspi_nor_data *data = dev->data;
503
504 *size = (uint64_t)data->size;
505
506 return 0;
507 }
508
509 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_flexspi_nor_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)510 static void flash_flexspi_nor_pages_layout(const struct device *dev,
511 const struct flash_pages_layout **layout, size_t *layout_size)
512 {
513 struct flash_flexspi_nor_data *data = dev->data;
514
515 *layout = &data->layout;
516 *layout_size = 1;
517 }
518 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
519
520
521 /*
522 * This function enables quad mode, when supported. Otherwise it
523 * returns an error.
524 * @param dev: Flexspi device
525 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
526 * @param qer: DW15 quad enable parameter
527 * @return 0 if quad mode was entered, or -ENOTSUP if quad mode is not supported
528 */
flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint8_t qer)529 static int flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data *data,
530 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
531 uint8_t qer)
532 {
533 int ret;
534 uint32_t buffer = 0;
535 uint16_t bit = 0;
536 uint8_t rd_size, wr_size;
537 flexspi_transfer_t transfer = {
538 .deviceAddress = 0,
539 .port = data->port,
540 .SeqNumber = 1,
541 .data = &buffer,
542 };
543 flexspi_device_config_t config = {
544 .flexspiRootClk = MHZ(50),
545 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
546 .ARDSeqNumber = 1,
547 .ARDSeqIndex = READ,
548 };
549
550 switch (qer) {
551 case JESD216_DW15_QER_VAL_NONE:
552 /* No init needed */
553 return 0;
554 case JESD216_DW15_QER_VAL_S2B1v1:
555 case JESD216_DW15_QER_VAL_S2B1v4:
556 /* Install read and write status command */
557 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
558 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
559 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
560 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
561 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
562 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
563
564 /* Set bit 1 of status register 2 */
565 bit = BIT(9);
566 rd_size = 2;
567 wr_size = 2;
568 break;
569 case JESD216_DW15_QER_VAL_S1B6:
570 /* Install read and write status command */
571 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
572 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
573 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
574 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
575 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
576 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
577
578 /* Set bit 6 of status register 1 */
579 bit = BIT(6);
580 rd_size = 1;
581 wr_size = 1;
582 break;
583 case JESD216_DW15_QER_VAL_S2B7:
584 /* Install read and write status command */
585 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
586 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3F,
587 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
588 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
589 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3E,
590 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
591
592 /* Set bit 7 of status register 2 */
593 bit = BIT(7);
594 rd_size = 1;
595 wr_size = 1;
596 break;
597 case JESD216_DW15_QER_VAL_S2B1v5:
598 /* Install read and write status command */
599 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
600 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
601 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
602 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
603 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
604 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
605
606 /* Set bit 1 of status register 2 */
607 bit = BIT(9);
608 rd_size = 1;
609 wr_size = 2;
610 break;
611 case JESD216_DW15_QER_VAL_S2B1v6:
612 /* Install read and write status command */
613 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
614 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
615 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
616 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
617 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR2,
618 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
619
620 /* Set bit 7 of status register 2 */
621 bit = BIT(7);
622 rd_size = 1;
623 wr_size = 1;
624 break;
625 default:
626 return -ENOTSUP;
627 }
628 ret = memc_flexspi_set_device_config(&data->controller,
629 &config,
630 (uint32_t *)flexspi_lut,
631 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
632 data->port);
633 if (ret < 0) {
634 return ret;
635 }
636 transfer.dataSize = rd_size;
637 transfer.seqIndex = SCRATCH_CMD;
638 transfer.cmdType = kFLEXSPI_Read;
639 /* Read status register */
640 ret = memc_flexspi_transfer(&data->controller, &transfer);
641 if (ret < 0) {
642 return ret;
643 }
644 /* Enable write */
645 ret = flash_flexspi_nor_write_enable(data);
646 if (ret < 0) {
647 return ret;
648 }
649 if (qer == JESD216_DW15_QER_VAL_S2B1v5) {
650 /* Left shift buffer by a byte */
651 buffer = buffer << 8;
652 }
653 buffer |= bit;
654 transfer.dataSize = wr_size;
655 transfer.seqIndex = SCRATCH_CMD2;
656 transfer.cmdType = kFLEXSPI_Write;
657 ret = memc_flexspi_transfer(&data->controller, &transfer);
658 if (ret < 0) {
659 return ret;
660 }
661
662 /* Wait for QE bit to complete programming */
663 return flash_flexspi_nor_wait_bus_busy(data);
664 }
665
666 /*
667 * This function enables 4 byte addressing, when supported. Otherwise it
668 * returns an error.
669 * @param dev: Flexspi device
670 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
671 * @param en4b: DW16 enable 4 byte mode parameter
672 * @return 0 if 4 byte mode was entered, or -ENOTSUP if 4 byte mode was not supported
673 */
flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint32_t en4b)674 static int flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data *data,
675 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
676 uint32_t en4b)
677 {
678 int ret;
679 uint32_t buffer = 0;
680 flexspi_transfer_t transfer = {
681 .deviceAddress = 0,
682 .port = data->port,
683 .SeqNumber = 1,
684 .data = &buffer,
685 };
686 flexspi_device_config_t config = {
687 .flexspiRootClk = MHZ(50),
688 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
689 .ARDSeqNumber = 1,
690 .ARDSeqIndex = READ,
691 };
692 if (en4b & BIT(6)) {
693 /* Flash is always in 4 byte mode. We just need to configure LUT */
694 return 0;
695 } else if (en4b & BIT(5)) {
696 /* Dedicated vendor instruction set, which we don't support. Exit here */
697 return -ENOTSUP;
698 } else if (en4b & BIT(4)) {
699 /* Set bit 0 of 16 bit configuration register */
700 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
701 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB5,
702 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
703 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
704 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB1,
705 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
706 ret = memc_flexspi_set_device_config(&data->controller,
707 &config,
708 (uint32_t *)flexspi_lut,
709 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
710 data->port);
711 if (ret < 0) {
712 return ret;
713 }
714 transfer.dataSize = 2;
715 transfer.seqIndex = SCRATCH_CMD;
716 transfer.cmdType = kFLEXSPI_Read;
717 /* Read config register */
718 ret = memc_flexspi_transfer(&data->controller, &transfer);
719 if (ret < 0) {
720 return ret;
721 }
722 buffer |= BIT(0);
723 /* Set config register */
724 transfer.seqIndex = SCRATCH_CMD2;
725 transfer.cmdType = kFLEXSPI_Read;
726 return memc_flexspi_transfer(&data->controller, &transfer);
727 } else if (en4b & BIT(1)) {
728 /* Issue write enable, then instruction 0xB7 */
729 flash_flexspi_nor_write_enable(data);
730 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
731 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
732 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
733 ret = memc_flexspi_set_device_config(&data->controller,
734 &config,
735 (uint32_t *)flexspi_lut,
736 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
737 data->port);
738 if (ret < 0) {
739 return ret;
740 }
741 transfer.dataSize = 0;
742 transfer.seqIndex = SCRATCH_CMD;
743 transfer.cmdType = kFLEXSPI_Command;
744 return memc_flexspi_transfer(&data->controller, &transfer);
745 } else if (en4b & BIT(0)) {
746 /* Issue instruction 0xB7 */
747 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
748 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
749 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
750 ret = memc_flexspi_set_device_config(&data->controller,
751 &config,
752 (uint32_t *)flexspi_lut,
753 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
754 data->port);
755 if (ret < 0) {
756 return ret;
757 }
758 transfer.dataSize = 0;
759 transfer.seqIndex = SCRATCH_CMD;
760 transfer.cmdType = kFLEXSPI_Command;
761 return memc_flexspi_transfer(&data->controller, &transfer);
762 }
763 /* Other methods not supported */
764 return -ENOTSUP;
765 }
766
767 /*
768 * This function configures the FlexSPI to manage the flash device
769 * based on values in SFDP header
770 * @param data: Flexspi device data
771 * @param header: SFDP header for flash
772 * @param bfp: basic flash parameters for flash
773 * @param flexspi_lut: LUT table, filled with READ LUT command
774 * @return 0 on success, or negative value on error
775 */
flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data * data,struct jesd216_sfdp_header * header,struct jesd216_bfp * bfp,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])776 static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
777 struct jesd216_sfdp_header *header,
778 struct jesd216_bfp *bfp,
779 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
780 {
781 struct jesd216_instr instr;
782 struct jesd216_bfp_dw16 dw16;
783 struct jesd216_bfp_dw15 dw15;
784 struct jesd216_bfp_dw14 dw14;
785 uint8_t addr_width;
786 uint8_t mode_cmd;
787 int ret;
788
789 /* Read DW14 to determine the polling method we should use while programming */
790 ret = jesd216_bfp_decode_dw14(&header->phdr[0], bfp, &dw14);
791 if (ret < 0) {
792 /* Default to legacy polling mode */
793 dw14.poll_options = 0x0;
794 }
795 if (dw14.poll_options & BIT(1)) {
796 /* Read instruction used for polling is 0x70 */
797 data->legacy_poll = false;
798 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
799 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x70,
800 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
801 } else {
802 /* Read instruction used for polling is 0x05 */
803 data->legacy_poll = true;
804 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
805 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
806 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
807 }
808
809 addr_width = jesd216_bfp_addrbytes(bfp) ==
810 JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B ? 32 : 24;
811
812 /* Check to see if we can enable 4 byte addressing */
813 ret = jesd216_bfp_decode_dw16(&header->phdr[0], bfp, &dw16);
814 if (ret == 0) {
815 /* Attempt to enable 4 byte addressing */
816 ret = flash_flexspi_nor_4byte_enable(data, flexspi_lut,
817 dw16.enter_4ba);
818 if (ret == 0) {
819 /* Use 4 byte address width */
820 addr_width = 32;
821 /* Update LUT for ERASE_SECTOR and ERASE_BLOCK to use 32 bit addr */
822 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
823 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
824 SPI_NOR_CMD_SE, kFLEXSPI_Command_RADDR_SDR,
825 kFLEXSPI_1PAD, addr_width);
826 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
827 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
828 SPI_NOR_CMD_BE, kFLEXSPI_Command_RADDR_SDR,
829 kFLEXSPI_1PAD, addr_width);
830 }
831 }
832 /* Extract the read command.
833 * Note- enhanced XIP not currently supported, nor is 4-4-4 mode.
834 */
835 if (jesd216_bfp_read_support(&header->phdr[0], bfp,
836 JESD216_MODE_144, &instr) > 0) {
837 LOG_DBG("Enable 144 mode");
838 /* Configure for 144 QUAD read mode */
839 if (instr.mode_clocks == 2) {
840 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
841 } else if (instr.mode_clocks == 1) {
842 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
843 } else if (instr.mode_clocks == 0) {
844 /* Just send dummy cycles during mode clock period */
845 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
846 } else {
847 return -ENOTSUP;
848 }
849 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
850 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
851 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, addr_width);
852 /* Note- we always set mode bits to 0x0 */
853 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
854 mode_cmd, kFLEXSPI_4PAD, 0x00,
855 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, instr.wait_states);
856 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
857 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04,
858 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
859 /* Read 1S-4S-4S enable method */
860 ret = jesd216_bfp_decode_dw15(&header->phdr[0], bfp, &dw15);
861 if (ret == 0) {
862 ret = flash_flexspi_nor_quad_enable(data, flexspi_lut,
863 dw15.qer);
864 if (ret == 0) {
865 /* Now, install 1S-1S-4S page program command */
866 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
867 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
868 SPI_NOR_CMD_PP_1_1_4, kFLEXSPI_Command_RADDR_SDR,
869 kFLEXSPI_1PAD, addr_width);
870 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
871 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD,
872 0x4, kFLEXSPI_Command_STOP,
873 kFLEXSPI_1PAD, 0x0);
874 }
875 }
876
877 } else if (jesd216_bfp_read_support(&header->phdr[0], bfp,
878 JESD216_MODE_122, &instr) > 0) {
879 LOG_DBG("Enable 122 mode");
880 if (instr.mode_clocks == 4) {
881 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
882 } else if (instr.mode_clocks == 2) {
883 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
884 } else if (instr.mode_clocks == 1) {
885 mode_cmd = kFLEXSPI_Command_MODE2_SDR;
886 } else if (instr.mode_clocks == 0) {
887 /* Just send dummy cycles during mode clock period */
888 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
889 } else {
890 return -ENOTSUP;
891 }
892 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
893 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
894 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_2PAD, addr_width);
895 /* Note- we always set mode bits to 0x0 */
896 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
897 mode_cmd, kFLEXSPI_2PAD, 0x0,
898 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_2PAD, instr.wait_states);
899 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
900 kFLEXSPI_Command_READ_SDR, kFLEXSPI_2PAD, 0x02,
901 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
902 /* Now, install 1S-1S-2S page program command */
903 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
904 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_2,
905 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
906 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
907 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_2PAD, 0x4,
908 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
909 }
910 /* Default to 111 mode if no support exists, leave READ/WRITE untouched */
911
912 return 0;
913 }
914
915 /* Helper so we can avoid flash access while performing SFDP probe */
flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data * dev_data,off_t offset,void * data,size_t len)916 static int flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data *dev_data,
917 off_t offset, void *data, size_t len)
918 {
919 flexspi_transfer_t transfer = {
920 .deviceAddress = offset,
921 .port = dev_data->port,
922 .cmdType = kFLEXSPI_Read,
923 .seqIndex = READ_JESD216,
924 .SeqNumber = 1,
925 .data = (uint32_t *)data,
926 .dataSize = len,
927 };
928
929 /* Get SFDP data */
930 return memc_flexspi_transfer(&dev_data->controller, &transfer);
931 }
932
933
934 #if defined(CONFIG_FLASH_JESD216_API)
935
flash_flexspi_nor_sfdp_read(const struct device * dev,off_t offset,void * data,size_t len)936 static int flash_flexspi_nor_sfdp_read(const struct device *dev,
937 off_t offset, void *data, size_t len)
938 {
939 struct flash_flexspi_nor_data *dev_data = dev->data;
940
941 return flash_flexspi_nor_sfdp_read_helper(dev_data, offset, data, len);
942 }
943
944 #endif
945
946 /* Helper to configure IS25 flash, by clearing read param bits */
flash_flexspi_nor_is25_clear_read_param(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint32_t * read_params)947 static int flash_flexspi_nor_is25_clear_read_param(struct flash_flexspi_nor_data *data,
948 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
949 uint32_t *read_params)
950 {
951 int ret;
952 /* Install Set Read Parameters (Volatile) command */
953 flexspi_transfer_t transfer = {
954 .deviceAddress = 0,
955 .port = data->port,
956 .seqIndex = SCRATCH_CMD,
957 .SeqNumber = 1,
958 .data = read_params,
959 .dataSize = 1,
960 .cmdType = kFLEXSPI_Write,
961 };
962 flexspi_device_config_t config = {
963 .flexspiRootClk = MHZ(50),
964 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
965 .ARDSeqNumber = 1,
966 .ARDSeqIndex = READ,
967 };
968
969 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
970 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC0,
971 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
972 ret = memc_flexspi_set_device_config(&data->controller,
973 &config,
974 (uint32_t *)flexspi_lut,
975 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
976 data->port);
977 if (ret < 0) {
978 return ret;
979 }
980 return memc_flexspi_transfer(&data->controller, &transfer);
981 }
982
983 /* Checks JEDEC ID of flash. If supported, installs custom LUT table */
flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])984 static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
985 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
986 {
987 int ret;
988 uint32_t vendor_id;
989 uint32_t read_params;
990
991 ret = flash_flexspi_nor_read_id_helper(data, (uint8_t *)&vendor_id);
992 if (ret < 0) {
993 return ret;
994 }
995
996 /* Switch on manufacturer and vendor ID */
997 switch (vendor_id & 0xFFFFFF) {
998 case 0x16609d: /* IS25LP032 flash, needs P[4:3] cleared with same method as IS25WP */
999 case 0x17609d: /* IS25LP064 */
1000 case 0x18609d: /* IS25LP128 */
1001 read_params = 0xE0U;
1002 ret = flash_flexspi_nor_is25_clear_read_param(data, flexspi_lut, &read_params);
1003 if (ret < 0) {
1004 while (1) {
1005 /*
1006 * Spin here, this flash won't configure correctly.
1007 * We can't print a warning, as we are unlikely to
1008 * be able to XIP at this point.
1009 */
1010 }
1011 }
1012 /* Still return an error- we want the JEDEC configuration to run */
1013 return -ENOTSUP;
1014 case 0x16709d: /* IS25WP032 */
1015 case 0x17709d: /* IS25WP064 */
1016 case 0x18709d: /* IS25WP128 */
1017 /*
1018 * IS25WP flash. We can support this flash with the JEDEC probe,
1019 * but we need to insure P[6:3] are at the default value
1020 */
1021 read_params = 0;
1022 ret = flash_flexspi_nor_is25_clear_read_param(data, flexspi_lut, &read_params);
1023 if (ret < 0) {
1024 while (1) {
1025 /*
1026 * Spin here, this flash won't configure correctly.
1027 * We can't print a warning, as we are unlikely to
1028 * be able to XIP at this point.
1029 */
1030 }
1031 }
1032 /* Still return an error- we want the JEDEC configuration to run */
1033 return -ENOTSUP;
1034 case 0x2040ef:
1035 /* W25Q512JV-IQ/IN flash, use 4 byte read/write */
1036 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1037 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1038 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1039 /* Flash needs 6 dummy cycles (at 104MHz) */
1040 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1041 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 6,
1042 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1043 /* Only 1S-1S-4S page program supported */
1044 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1045 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
1046 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1047 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1048 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1049 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1050 /* Update ERASE commands for 4 byte mode */
1051 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1052 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1053 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1054 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1055 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1056 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1057 /* Read instruction used for polling is 0x05 */
1058 data->legacy_poll = true;
1059 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1060 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1061 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1062 /* Device uses bit 1 of status reg 2 for QE */
1063 return flash_flexspi_nor_quad_enable(data, flexspi_lut,
1064 JESD216_DW15_QER_VAL_S2B1v5);
1065 case 0x2060ef:
1066 /* W25Q512NW-IQ/IN flash, use 4 byte read/write */
1067 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1068 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1069 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1070 /* Flash needs 8 dummy cycles (at 133MHz) */
1071 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1072 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
1073 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1074 /* Only 1S-1S-4S page program supported */
1075 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1076 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
1077 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1078 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1079 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1080 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1081 /* Update ERASE commands for 4 byte mode */
1082 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1083 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1084 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1085 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1086 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1087 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1088 /* Read instruction used for polling is 0x05 */
1089 data->legacy_poll = true;
1090 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1091 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1092 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1093 /* Device uses bit 1 of status reg 2 for QE */
1094 return flash_flexspi_nor_quad_enable(data, flexspi_lut,
1095 JESD216_DW15_QER_VAL_S2B1v5);
1096 case 0x3A25C2:
1097 /* MX25U51245G flash, use 4 byte read/write */
1098 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1099 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1100 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1101 /* Flash needs 10 dummy cycles */
1102 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1103 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 10,
1104 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1105 /* Only 1S-4S-4S page program supported */
1106 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1107 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_4_4_4B,
1108 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1109 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1110 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1111 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1112 /* Update ERASE commands for 4 byte mode */
1113 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1114 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1115 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1116 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1117 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1118 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1119 /* Read instruction used for polling is 0x05 */
1120 data->legacy_poll = true;
1121 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1122 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1123 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1124 /* Device uses bit 6 of status reg 1 for QE */
1125 return flash_flexspi_nor_quad_enable(data, flexspi_lut, JESD216_DW15_QER_VAL_S1B6);
1126 case 0x19ba20: /* MT25QL256 */
1127 case 0x20ba20: /* MT25QL512 */
1128 case 0x21ba20: /* MT25QL01G */
1129 case 0x22ba20: /* MT25QL02G */
1130 case 0x19bb20: /* MT25QU256 */
1131 case 0x20bb20: /* MT25QU512 */
1132 case 0x21bb20: /* MT25QU01G */
1133 case 0x22bb20: /* MT25QU02G */
1134 /* MT25Q flash with more than 32MB, use 4 byte read/write */
1135 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1136 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1137 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1138 /* Flash needs 10 dummy cycles */
1139 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1140 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 10,
1141 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1142 /* Update PROGRAM commands for 4 byte 1S-4S-4S mode */
1143 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1144 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_4_4_4B,
1145 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1146 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1147 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1148 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1149 /* Update ERASE commands for 4 byte mode */
1150 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1151 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1152 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1153 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1154 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1155 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1156 /* Read instruction used for polling is 0x05 */
1157 data->legacy_poll = true;
1158 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1159 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1160 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1161 /* Device has no QE bit, 1-4-4 and 1-1-4 is always enabled */
1162 return 0;
1163 default:
1164 return -ENOTSUP;
1165 }
1166 }
1167
1168 /* Probe parameters from flash SFDP header, and use them to configure the FlexSPI */
flash_flexspi_nor_probe(struct flash_flexspi_nor_data * data)1169 static int flash_flexspi_nor_probe(struct flash_flexspi_nor_data *data)
1170 {
1171 /* JESD216B defines up to 23 basic flash parameters */
1172 uint32_t param_buf[23];
1173 /* Space to store SFDP header and first parameter header */
1174 uint8_t sfdp_buf[JESD216_SFDP_SIZE(1)] __aligned(4);
1175 struct jesd216_bfp *bfp = (struct jesd216_bfp *)param_buf;
1176 struct jesd216_sfdp_header *header = (struct jesd216_sfdp_header *)sfdp_buf;
1177 int ret;
1178 unsigned int key = 0U;
1179
1180 flexspi_device_config_t config = {
1181 .flexspiRootClk = MHZ(50),
1182 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
1183 .ARDSeqNumber = 1,
1184 .ARDSeqIndex = READ,
1185 };
1186
1187 if (memc_flexspi_is_running_xip(&data->controller)) {
1188 /*
1189 * ==== ENTER CRITICAL SECTION ====
1190 * No flash access should be performed in critical section. All
1191 * code and data accessed must reside in ram.
1192 */
1193 key = irq_lock();
1194 memc_flexspi_wait_bus_idle(&data->controller);
1195 }
1196
1197 /* SFDP spec requires that we downclock the FlexSPI to 50MHz or less */
1198 ret = memc_flexspi_update_clock(&data->controller, &config,
1199 data->port, MHZ(50));
1200 if (ret < 0) {
1201 goto _exit;
1202 }
1203
1204 /* Setup initial LUT table and FlexSPI configuration */
1205 memcpy(flexspi_probe_lut, flash_flexspi_nor_base_lut,
1206 sizeof(flash_flexspi_nor_base_lut));
1207
1208 ret = memc_flexspi_set_device_config(&data->controller, &config,
1209 (uint32_t *)flexspi_probe_lut,
1210 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
1211 data->port);
1212 if (ret < 0) {
1213 goto _exit;
1214 }
1215
1216 /* First, check if the JEDEC ID of this flash has explicit support
1217 * in this driver
1218 */
1219 ret = flash_flexspi_nor_check_jedec(data, flexspi_probe_lut);
1220 if (ret == 0) {
1221 /* Flash was supported, SFDP probe not needed */
1222 goto _program_lut;
1223 }
1224
1225 ret = flash_flexspi_nor_sfdp_read_helper(data, 0, sfdp_buf, sizeof(sfdp_buf));
1226 if (ret < 0) {
1227 goto _exit;
1228 }
1229
1230 LOG_DBG("SFDP header magic: 0x%x", header->magic);
1231 if (jesd216_sfdp_magic(header) != JESD216_SFDP_MAGIC) {
1232 /* Header was read incorrectly */
1233 LOG_WRN("Invalid header, using legacy SPI mode");
1234 data->legacy_poll = true;
1235 goto _program_lut;
1236 }
1237
1238 if (header->phdr[0].len_dw > ARRAY_SIZE(param_buf)) {
1239 /* Not enough space to read parameter table */
1240 ret = -ENOBUFS;
1241 goto _exit;
1242 }
1243
1244 /* Read basic flash parameter table */
1245 ret = flash_flexspi_nor_sfdp_read_helper(data,
1246 jesd216_param_addr(&header->phdr[0]),
1247 param_buf,
1248 sizeof(uint32_t) * header->phdr[0].len_dw);
1249 if (ret < 0) {
1250 goto _exit;
1251 }
1252
1253 /* Configure flash */
1254 ret = flash_flexspi_nor_config_flash(data, header, bfp,
1255 flexspi_probe_lut);
1256 if (ret < 0) {
1257 goto _exit;
1258 }
1259
1260 _program_lut:
1261 /*
1262 * Update the FlexSPI with the config structure provided
1263 * from devicetree and the configured LUT
1264 */
1265 ret = memc_flexspi_set_device_config(&data->controller, &data->config,
1266 (uint32_t *)flexspi_probe_lut,
1267 FLEXSPI_INSTR_PROG_END * MEMC_FLEXSPI_CMD_PER_SEQ,
1268 data->port);
1269 if (ret < 0) {
1270 return ret;
1271 }
1272
1273 _exit:
1274 memc_flexspi_reset(&data->controller);
1275
1276 if (memc_flexspi_is_running_xip(&data->controller)) {
1277 /* ==== EXIT CRITICAL SECTION ==== */
1278 irq_unlock(key);
1279 }
1280
1281 return ret;
1282 }
1283
flash_flexspi_nor_init(const struct device * dev)1284 static int flash_flexspi_nor_init(const struct device *dev)
1285 {
1286 const struct flash_flexspi_nor_config *config = dev->config;
1287 struct flash_flexspi_nor_data *data = dev->data;
1288 uint32_t vendor_id;
1289
1290 /* First step- use ROM pointer to controller device to create
1291 * a copy of the device structure in RAM we can use while in
1292 * critical sections of code.
1293 */
1294 memcpy(&data->controller, config->controller, sizeof(struct device));
1295
1296 if (!device_is_ready(&data->controller)) {
1297 LOG_ERR("Controller device is not ready");
1298 return -ENODEV;
1299 }
1300
1301 if (flash_flexspi_nor_probe(data)) {
1302 if (memc_flexspi_is_running_xip(&data->controller)) {
1303 /* We can't continue from here- the LUT stored in
1304 * the FlexSPI will be invalid so we cannot XIP.
1305 * Instead, spin here
1306 */
1307 while (1) {
1308 /* Spin */
1309 }
1310 }
1311 LOG_ERR("SFDP probe failed");
1312 return -EIO;
1313 }
1314
1315 /* Set the FlexSPI to full clock speed */
1316 if (memc_flexspi_update_clock(&data->controller, &data->config,
1317 data->port, data->config.flexspiRootClk)) {
1318 LOG_ERR("Could not set flexspi clock speed");
1319 return -ENOTSUP;
1320 }
1321
1322
1323 memc_flexspi_reset(&data->controller);
1324
1325 if (flash_flexspi_nor_read_id(dev, (uint8_t *)&vendor_id)) {
1326 LOG_ERR("Could not read vendor id");
1327 return -EIO;
1328 }
1329 LOG_DBG("Vendor id: 0x%0x", vendor_id);
1330
1331 return 0;
1332 }
1333
1334 static DEVICE_API(flash, flash_flexspi_nor_api) = {
1335 .erase = flash_flexspi_nor_erase,
1336 .write = flash_flexspi_nor_write,
1337 .read = flash_flexspi_nor_read,
1338 .get_parameters = flash_flexspi_nor_get_parameters,
1339 .get_size = flash_flexspi_nor_get_size,
1340 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
1341 .page_layout = flash_flexspi_nor_pages_layout,
1342 #endif
1343 #if defined(CONFIG_FLASH_JESD216_API)
1344 .sfdp_read = flash_flexspi_nor_sfdp_read,
1345 .read_jedec_id = flash_flexspi_nor_read_id,
1346 #endif
1347 };
1348
1349 #define CONCAT3(x, y, z) x ## y ## z
1350
1351 #define CS_INTERVAL_UNIT(unit) \
1352 CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
1353
1354 #define AHB_WRITE_WAIT_UNIT(unit) \
1355 CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
1356
1357 #define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
1358 { \
1359 .flexspiRootClk = DT_INST_PROP(n, spi_max_frequency), \
1360 .flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
1361 .CSIntervalUnit = \
1362 CS_INTERVAL_UNIT( \
1363 DT_INST_PROP(n, cs_interval_unit)), \
1364 .CSInterval = DT_INST_PROP(n, cs_interval), \
1365 .CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
1366 .CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
1367 .dataValidTime = DT_INST_PROP(n, data_valid_time), \
1368 .columnspace = DT_INST_PROP(n, column_space), \
1369 .enableWordAddress = DT_INST_PROP(n, word_addressable), \
1370 .AWRSeqIndex = 0, \
1371 .AWRSeqNumber = 0, \
1372 .ARDSeqIndex = READ, \
1373 .ARDSeqNumber = 1, \
1374 .AHBWriteWaitUnit = \
1375 AHB_WRITE_WAIT_UNIT( \
1376 DT_INST_PROP(n, ahb_write_wait_unit)), \
1377 .AHBWriteWaitInterval = \
1378 DT_INST_PROP(n, ahb_write_wait_interval), \
1379 } \
1380
1381 #define FLASH_FLEXSPI_NOR(n) \
1382 static const struct flash_flexspi_nor_config \
1383 flash_flexspi_nor_config_##n = { \
1384 .controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
1385 }; \
1386 static struct flash_flexspi_nor_data \
1387 flash_flexspi_nor_data_##n = { \
1388 .config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
1389 .port = DT_INST_REG_ADDR(n), \
1390 .size = DT_INST_PROP(n, size) / 8, \
1391 .layout = { \
1392 .pages_count = DT_INST_PROP(n, size) / 8 \
1393 / SPI_NOR_SECTOR_SIZE, \
1394 .pages_size = SPI_NOR_SECTOR_SIZE, \
1395 }, \
1396 .flash_parameters = { \
1397 .write_block_size = NOR_WRITE_SIZE, \
1398 .erase_value = NOR_ERASE_VALUE, \
1399 }, \
1400 }; \
1401 \
1402 DEVICE_DT_INST_DEFINE(n, \
1403 flash_flexspi_nor_init, \
1404 NULL, \
1405 &flash_flexspi_nor_data_##n, \
1406 &flash_flexspi_nor_config_##n, \
1407 POST_KERNEL, \
1408 CONFIG_FLASH_INIT_PRIORITY, \
1409 &flash_flexspi_nor_api);
1410
1411 DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)
1412
