1 /*
2 * Copyright 2020,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_flexspi_nor
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/drivers/flash.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/sys/util.h>
14 #include "spi_nor.h"
15 #include "jesd216.h"
16 #include "memc_mcux_flexspi.h"
17
18 #ifdef CONFIG_HAS_MCUX_CACHE
19 #include <fsl_cache.h>
20 #endif
21
22 #define NOR_WRITE_SIZE 1
23 #define NOR_ERASE_VALUE 0xff
24
25 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
26 static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
27 #endif
28
29 /*
30 * NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
31 * called while interacting with the flexspi MUST be relocated to SRAM or ITCM
32 * at runtime, so that the chip does not access the flexspi to read program
33 * instructions while it is being written to
34 *
35 * Additionally, no data used by this driver should be stored in flash.
36 */
37 #if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0)
38 #warning "Enabling flash driver logging and XIP mode simultaneously can cause \
39 read-while-write hazards. This configuration is not recommended."
40 #endif
41
42 LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
43
44 enum {
45 READ,
46 PAGE_PROGRAM,
47 READ_STATUS,
48 WRITE_ENABLE,
49 ERASE_SECTOR,
50 ERASE_BLOCK,
51 READ_ID,
52 READ_STATUS_REG,
53 ERASE_CHIP,
54 READ_JESD216,
55 /* Entries after this should be for scratch commands */
56 FLEXSPI_INSTR_PROG_END,
57 /* Used for temporary commands during initialization */
58 SCRATCH_CMD = FLEXSPI_INSTR_PROG_END,
59 SCRATCH_CMD2,
60 /* Must be last entry */
61 FLEXSPI_INSTR_END,
62 };
63
64 struct flash_flexspi_nor_config {
65 /* Note: don't use this controller reference in code. It is
66 * only used during init to copy the device structure from ROM
67 * into a RAM structure
68 */
69 const struct device *controller;
70 };
71
72 /* Device variables used in critical sections should be in this structure */
73 struct flash_flexspi_nor_data {
74 struct device controller;
75 flexspi_device_config_t config;
76 flexspi_port_t port;
77 bool legacy_poll;
78 uint64_t size;
79 struct flash_pages_layout layout;
80 struct flash_parameters flash_parameters;
81 };
82
83 /*
84 * FLEXSPI LUT buffer used during configuration. Stored in .data to avoid
85 * using too much stack
86 */
87 static uint32_t flexspi_probe_lut[FLEXSPI_INSTR_END][MEMC_FLEXSPI_CMD_PER_SEQ] = {0};
88
89 /* Initial LUT table */
90 static const uint32_t flash_flexspi_nor_base_lut[][MEMC_FLEXSPI_CMD_PER_SEQ] = {
91 /* 1S-1S-1S flash read command, should be compatible with all SPI nor flashes */
92 [READ] = {
93 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_READ,
94 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
95 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1,
96 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
97 },
98 [READ_JESD216] = {
99 /* Install read SFDP command */
100 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, JESD216_CMD_READ_SFDP,
101 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
102 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 8,
103 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x4),
104 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0,
105 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
106 },
107 /* Standard 1S-1S-1S flash write command, can be switched to 1S-1S-4S when QE is set */
108 [PAGE_PROGRAM] = {
109 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP,
110 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
111 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
112 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
113 },
114
115 [WRITE_ENABLE] = {
116 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WREN,
117 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
118 },
119
120 [ERASE_SECTOR] = {
121 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE,
122 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
123 },
124
125 [ERASE_BLOCK] = {
126 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE,
127 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
128 },
129
130 [ERASE_CHIP] = {
131 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_CE,
132 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
133 },
134
135 [READ_ID] = {
136 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDID,
137 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
138 },
139
140 [READ_STATUS_REG] = {
141 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
142 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
143 },
144 };
145
146 /* Helper so we can read flash ID without flash access for XIP */
flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data * data,uint8_t * vendor_id)147 static int flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data *data,
148 uint8_t *vendor_id)
149 {
150 uint32_t buffer = 0;
151 int ret;
152
153 flexspi_transfer_t transfer = {
154 .deviceAddress = 0,
155 .port = data->port,
156 .cmdType = kFLEXSPI_Read,
157 .SeqNumber = 1,
158 .seqIndex = READ_ID,
159 .data = &buffer,
160 .dataSize = 3,
161 };
162
163 LOG_DBG("Reading id");
164
165 ret = memc_flexspi_transfer(&data->controller, &transfer);
166 if (ret < 0) {
167 return ret;
168 }
169
170 memcpy(vendor_id, &buffer, 3);
171
172 return ret;
173 }
174
flash_flexspi_nor_read_id(const struct device * dev,uint8_t * vendor_id)175 static int flash_flexspi_nor_read_id(const struct device *dev, uint8_t *vendor_id)
176 {
177 struct flash_flexspi_nor_data *data = dev->data;
178
179 return flash_flexspi_nor_read_id_helper(data, vendor_id);
180 }
181
flash_flexspi_nor_read_status(struct flash_flexspi_nor_data * data,uint32_t * status)182 static int flash_flexspi_nor_read_status(struct flash_flexspi_nor_data *data,
183 uint32_t *status)
184 {
185 flexspi_transfer_t transfer = {
186 .deviceAddress = 0,
187 .port = data->port,
188 .cmdType = kFLEXSPI_Read,
189 .SeqNumber = 1,
190 .seqIndex = READ_STATUS_REG,
191 .data = status,
192 .dataSize = 1,
193 };
194
195 LOG_DBG("Reading status register");
196
197 return memc_flexspi_transfer(&data->controller, &transfer);
198 }
199
flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data * data)200 static int flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data *data)
201 {
202 flexspi_transfer_t transfer = {
203 .deviceAddress = 0,
204 .port = data->port,
205 .cmdType = kFLEXSPI_Command,
206 .SeqNumber = 1,
207 .seqIndex = WRITE_ENABLE,
208 .data = NULL,
209 .dataSize = 0,
210 };
211
212 LOG_DBG("Enabling write");
213
214 return memc_flexspi_transfer(&data->controller, &transfer);
215 }
216
flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data * data,off_t offset)217 static int flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data *data,
218 off_t offset)
219 {
220 flexspi_transfer_t transfer = {
221 .deviceAddress = offset,
222 .port = data->port,
223 .cmdType = kFLEXSPI_Command,
224 .SeqNumber = 1,
225 .seqIndex = ERASE_SECTOR,
226 .data = NULL,
227 .dataSize = 0,
228 };
229
230 LOG_DBG("Erasing sector at 0x%08zx", (ssize_t) offset);
231
232 return memc_flexspi_transfer(&data->controller, &transfer);
233 }
234
flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data * data,off_t offset)235 static int flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data *data,
236 off_t offset)
237 {
238 flexspi_transfer_t transfer = {
239 .deviceAddress = offset,
240 .port = data->port,
241 .cmdType = kFLEXSPI_Command,
242 .SeqNumber = 1,
243 .seqIndex = ERASE_BLOCK,
244 .data = NULL,
245 .dataSize = 0,
246 };
247
248 LOG_DBG("Erasing block at 0x%08zx", (ssize_t) offset);
249
250 return memc_flexspi_transfer(&data->controller, &transfer);
251 }
252
flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data * data)253 static int flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data *data)
254 {
255 flexspi_transfer_t transfer = {
256 .deviceAddress = 0,
257 .port = data->port,
258 .cmdType = kFLEXSPI_Command,
259 .SeqNumber = 1,
260 .seqIndex = ERASE_CHIP,
261 .data = NULL,
262 .dataSize = 0,
263 };
264
265 LOG_DBG("Erasing chip");
266
267 return memc_flexspi_transfer(&data->controller, &transfer);
268 }
269
flash_flexspi_nor_page_program(struct flash_flexspi_nor_data * data,off_t offset,const void * buffer,size_t len)270 static int flash_flexspi_nor_page_program(struct flash_flexspi_nor_data *data,
271 off_t offset, const void *buffer, size_t len)
272 {
273 flexspi_transfer_t transfer = {
274 .deviceAddress = offset,
275 .port = data->port,
276 .cmdType = kFLEXSPI_Write,
277 .SeqNumber = 1,
278 .seqIndex = PAGE_PROGRAM,
279 .data = (uint32_t *) buffer,
280 .dataSize = len,
281 };
282
283 LOG_DBG("Page programming %d bytes to 0x%08zx", len, (ssize_t) offset);
284
285 return memc_flexspi_transfer(&data->controller, &transfer);
286 }
287
flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data * data)288 static int flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data *data)
289 {
290 uint32_t status = 0;
291 int ret;
292
293 while (1) {
294 ret = flash_flexspi_nor_read_status(data, &status);
295 LOG_DBG("status: 0x%x", status);
296 if (ret) {
297 LOG_ERR("Could not read status");
298 return ret;
299 }
300
301 if (data->legacy_poll) {
302 if ((status & BIT(0)) == 0) {
303 break;
304 }
305 } else {
306 if (status & BIT(7)) {
307 break;
308 }
309 }
310 }
311
312 return 0;
313 }
314
flash_flexspi_nor_read(const struct device * dev,off_t offset,void * buffer,size_t len)315 static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
316 void *buffer, size_t len)
317 {
318 struct flash_flexspi_nor_data *data = dev->data;
319 uint8_t *src = memc_flexspi_get_ahb_address(&data->controller,
320 data->port,
321 offset);
322
323 memcpy(buffer, src, len);
324
325 return 0;
326 }
327
flash_flexspi_nor_write(const struct device * dev,off_t offset,const void * buffer,size_t len)328 static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
329 const void *buffer, size_t len)
330 {
331 struct flash_flexspi_nor_data *data = dev->data;
332 size_t size = len;
333 uint8_t *src = (uint8_t *) buffer;
334 int i;
335 unsigned int key = 0;
336
337 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
338 data->port,
339 offset);
340
341 if (memc_flexspi_is_running_xip(&data->controller)) {
342 /*
343 * ==== ENTER CRITICAL SECTION ====
344 * No flash access should be performed in critical section. All
345 * code and data accessed must reside in ram.
346 */
347 key = irq_lock();
348 memc_flexspi_wait_bus_idle(&data->controller);
349 }
350
351 while (len) {
352 /* If the offset isn't a multiple of the NOR page size, we first need
353 * to write the remaining part that fits, otherwise the write could
354 * be wrapped around within the same page
355 */
356 i = MIN(SPI_NOR_PAGE_SIZE - (offset % SPI_NOR_PAGE_SIZE), len);
357 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
358 memcpy(nor_write_buf, src, i);
359
360 /* As memcpy could cause an XIP access,
361 * we need to wait for XIP prefetch to be finished again
362 */
363 if (memc_flexspi_is_running_xip(&data->controller)) {
364 memc_flexspi_wait_bus_idle(&data->controller);
365 }
366 #endif
367 flash_flexspi_nor_write_enable(data);
368 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
369 flash_flexspi_nor_page_program(data, offset, nor_write_buf, i);
370 #else
371 flash_flexspi_nor_page_program(data, offset, src, i);
372 #endif
373 flash_flexspi_nor_wait_bus_busy(data);
374 memc_flexspi_reset(&data->controller);
375 src += i;
376 offset += i;
377 len -= i;
378 }
379
380 if (memc_flexspi_is_running_xip(&data->controller)) {
381 /* ==== EXIT CRITICAL SECTION ==== */
382 irq_unlock(key);
383 }
384
385 #ifdef CONFIG_HAS_MCUX_CACHE
386 DCACHE_InvalidateByRange((uint32_t) dst, size);
387 #endif
388
389 return 0;
390 }
391
flash_flexspi_nor_erase(const struct device * dev,off_t offset,size_t size)392 static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
393 size_t size)
394 {
395 struct flash_flexspi_nor_data *data = dev->data;
396 const size_t num_sectors = size / SPI_NOR_SECTOR_SIZE;
397 const size_t num_blocks = size / SPI_NOR_BLOCK_SIZE;
398
399 int i;
400 unsigned int key = 0;
401
402 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
403 data->port,
404 offset);
405
406 if (offset % SPI_NOR_SECTOR_SIZE) {
407 LOG_ERR("Invalid offset");
408 return -EINVAL;
409 }
410
411 if (size % SPI_NOR_SECTOR_SIZE) {
412 LOG_ERR("Invalid size");
413 return -EINVAL;
414 }
415
416 if (memc_flexspi_is_running_xip(&data->controller)) {
417 /*
418 * ==== ENTER CRITICAL SECTION ====
419 * No flash access should be performed in critical section. All
420 * code and data accessed must reside in ram.
421 */
422 key = irq_lock();
423 memc_flexspi_wait_bus_idle(&data->controller);
424 }
425
426 if ((offset == 0) && (size == data->config.flashSize * KB(1))) {
427 flash_flexspi_nor_write_enable(data);
428 flash_flexspi_nor_erase_chip(data);
429 flash_flexspi_nor_wait_bus_busy(data);
430 memc_flexspi_reset(&data->controller);
431 } else if ((0 == (offset % SPI_NOR_BLOCK_SIZE)) && (0 == (size % SPI_NOR_BLOCK_SIZE))) {
432 for (i = 0; i < num_blocks; i++) {
433 flash_flexspi_nor_write_enable(data);
434 flash_flexspi_nor_erase_block(data, offset);
435 flash_flexspi_nor_wait_bus_busy(data);
436 memc_flexspi_reset(&data->controller);
437 offset += SPI_NOR_BLOCK_SIZE;
438 }
439 } else {
440 for (i = 0; i < num_sectors; i++) {
441 flash_flexspi_nor_write_enable(data);
442 flash_flexspi_nor_erase_sector(data, offset);
443 flash_flexspi_nor_wait_bus_busy(data);
444 memc_flexspi_reset(&data->controller);
445 offset += SPI_NOR_SECTOR_SIZE;
446 }
447 }
448
449 if (memc_flexspi_is_running_xip(&data->controller)) {
450 /* ==== EXIT CRITICAL SECTION ==== */
451 irq_unlock(key);
452 }
453
454 #ifdef CONFIG_HAS_MCUX_CACHE
455 DCACHE_InvalidateByRange((uint32_t) dst, size);
456 #endif
457
458 return 0;
459 }
460
flash_flexspi_nor_get_parameters(const struct device * dev)461 static const struct flash_parameters *flash_flexspi_nor_get_parameters(
462 const struct device *dev)
463 {
464 struct flash_flexspi_nor_data *data = dev->data;
465
466 return &data->flash_parameters;
467 }
468
flash_flexspi_nor_get_size(const struct device * dev,uint64_t * size)469 static int flash_flexspi_nor_get_size(const struct device *dev, uint64_t *size)
470 {
471 struct flash_flexspi_nor_data *data = dev->data;
472
473 *size = (uint64_t)data->size;
474
475 return 0;
476 }
477
478 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_flexspi_nor_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)479 static void flash_flexspi_nor_pages_layout(const struct device *dev,
480 const struct flash_pages_layout **layout, size_t *layout_size)
481 {
482 struct flash_flexspi_nor_data *data = dev->data;
483
484 *layout = &data->layout;
485 *layout_size = 1;
486 }
487 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
488
489
490 /*
491 * This function enables quad mode, when supported. Otherwise it
492 * returns an error.
493 * @param dev: Flexspi device
494 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
495 * @param qer: DW15 quad enable parameter
496 * @return 0 if quad mode was entered, or -ENOTSUP if quad mode is not supported
497 */
flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint8_t qer)498 static int flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data *data,
499 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
500 uint8_t qer)
501 {
502 int ret;
503 uint32_t buffer = 0;
504 uint16_t bit = 0;
505 uint8_t rd_size, wr_size;
506 flexspi_transfer_t transfer = {
507 .deviceAddress = 0,
508 .port = data->port,
509 .SeqNumber = 1,
510 .data = &buffer,
511 };
512 flexspi_device_config_t config = {
513 .flexspiRootClk = MHZ(50),
514 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
515 .ARDSeqNumber = 1,
516 .ARDSeqIndex = READ,
517 };
518
519 switch (qer) {
520 case JESD216_DW15_QER_VAL_NONE:
521 /* No init needed */
522 return 0;
523 case JESD216_DW15_QER_VAL_S2B1v1:
524 case JESD216_DW15_QER_VAL_S2B1v4:
525 /* Install read and write status command */
526 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
527 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
528 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
529 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
530 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
531 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
532
533 /* Set bit 1 of status register 2 */
534 bit = BIT(9);
535 rd_size = 2;
536 wr_size = 2;
537 break;
538 case JESD216_DW15_QER_VAL_S1B6:
539 /* Install read and write status command */
540 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
541 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
542 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
543 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
544 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
545 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
546
547 /* Set bit 6 of status register 1 */
548 bit = BIT(6);
549 rd_size = 1;
550 wr_size = 1;
551 break;
552 case JESD216_DW15_QER_VAL_S2B7:
553 /* Install read and write status command */
554 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
555 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3F,
556 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
557 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
558 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3E,
559 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
560
561 /* Set bit 7 of status register 2 */
562 bit = BIT(7);
563 rd_size = 1;
564 wr_size = 1;
565 break;
566 case JESD216_DW15_QER_VAL_S2B1v5:
567 /* Install read and write status command */
568 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
569 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
570 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
571 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
572 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
573 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
574
575 /* Set bit 1 of status register 2 */
576 bit = BIT(9);
577 rd_size = 1;
578 wr_size = 2;
579 break;
580 case JESD216_DW15_QER_VAL_S2B1v6:
581 /* Install read and write status command */
582 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
583 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
584 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
585 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
586 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR2,
587 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
588
589 /* Set bit 7 of status register 2 */
590 bit = BIT(7);
591 rd_size = 1;
592 wr_size = 1;
593 break;
594 default:
595 return -ENOTSUP;
596 }
597 ret = memc_flexspi_set_device_config(&data->controller,
598 &config,
599 (uint32_t *)flexspi_lut,
600 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
601 data->port);
602 if (ret < 0) {
603 return ret;
604 }
605 transfer.dataSize = rd_size;
606 transfer.seqIndex = SCRATCH_CMD;
607 transfer.cmdType = kFLEXSPI_Read;
608 /* Read status register */
609 ret = memc_flexspi_transfer(&data->controller, &transfer);
610 if (ret < 0) {
611 return ret;
612 }
613 /* Enable write */
614 ret = flash_flexspi_nor_write_enable(data);
615 if (ret < 0) {
616 return ret;
617 }
618 if (qer == JESD216_DW15_QER_VAL_S2B1v5) {
619 /* Left shift buffer by a byte */
620 buffer = buffer << 8;
621 }
622 buffer |= bit;
623 transfer.dataSize = wr_size;
624 transfer.seqIndex = SCRATCH_CMD2;
625 transfer.cmdType = kFLEXSPI_Write;
626 ret = memc_flexspi_transfer(&data->controller, &transfer);
627 if (ret < 0) {
628 return ret;
629 }
630
631 /* Wait for QE bit to complete programming */
632 return flash_flexspi_nor_wait_bus_busy(data);
633 }
634
635 /*
636 * This function enables 4 byte addressing, when supported. Otherwise it
637 * returns an error.
638 * @param dev: Flexspi device
639 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
640 * @param en4b: DW16 enable 4 byte mode parameter
641 * @return 0 if 4 byte mode was entered, or -ENOTSUP if 4 byte mode was not supported
642 */
flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint32_t en4b)643 static int flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data *data,
644 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
645 uint32_t en4b)
646 {
647 int ret;
648 uint32_t buffer = 0;
649 flexspi_transfer_t transfer = {
650 .deviceAddress = 0,
651 .port = data->port,
652 .SeqNumber = 1,
653 .data = &buffer,
654 };
655 flexspi_device_config_t config = {
656 .flexspiRootClk = MHZ(50),
657 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
658 .ARDSeqNumber = 1,
659 .ARDSeqIndex = READ,
660 };
661 if (en4b & BIT(6)) {
662 /* Flash is always in 4 byte mode. We just need to configure LUT */
663 return 0;
664 } else if (en4b & BIT(5)) {
665 /* Dedicated vendor instruction set, which we don't support. Exit here */
666 return -ENOTSUP;
667 } else if (en4b & BIT(4)) {
668 /* Set bit 0 of 16 bit configuration register */
669 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
670 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB5,
671 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
672 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
673 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB1,
674 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
675 ret = memc_flexspi_set_device_config(&data->controller,
676 &config,
677 (uint32_t *)flexspi_lut,
678 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
679 data->port);
680 if (ret < 0) {
681 return ret;
682 }
683 transfer.dataSize = 2;
684 transfer.seqIndex = SCRATCH_CMD;
685 transfer.cmdType = kFLEXSPI_Read;
686 /* Read config register */
687 ret = memc_flexspi_transfer(&data->controller, &transfer);
688 if (ret < 0) {
689 return ret;
690 }
691 buffer |= BIT(0);
692 /* Set config register */
693 transfer.seqIndex = SCRATCH_CMD2;
694 transfer.cmdType = kFLEXSPI_Read;
695 return memc_flexspi_transfer(&data->controller, &transfer);
696 } else if (en4b & BIT(1)) {
697 /* Issue write enable, then instruction 0xB7 */
698 flash_flexspi_nor_write_enable(data);
699 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
700 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
701 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
702 ret = memc_flexspi_set_device_config(&data->controller,
703 &config,
704 (uint32_t *)flexspi_lut,
705 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
706 data->port);
707 if (ret < 0) {
708 return ret;
709 }
710 transfer.dataSize = 0;
711 transfer.seqIndex = SCRATCH_CMD;
712 transfer.cmdType = kFLEXSPI_Command;
713 return memc_flexspi_transfer(&data->controller, &transfer);
714 } else if (en4b & BIT(0)) {
715 /* Issue instruction 0xB7 */
716 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
717 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
718 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
719 ret = memc_flexspi_set_device_config(&data->controller,
720 &config,
721 (uint32_t *)flexspi_lut,
722 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
723 data->port);
724 if (ret < 0) {
725 return ret;
726 }
727 transfer.dataSize = 0;
728 transfer.seqIndex = SCRATCH_CMD;
729 transfer.cmdType = kFLEXSPI_Command;
730 return memc_flexspi_transfer(&data->controller, &transfer);
731 }
732 /* Other methods not supported */
733 return -ENOTSUP;
734 }
735
736 /*
737 * This function configures the FlexSPI to manage the flash device
738 * based on values in SFDP header
739 * @param data: Flexspi device data
740 * @param header: SFDP header for flash
741 * @param bfp: basic flash parameters for flash
742 * @param flexspi_lut: LUT table, filled with READ LUT command
743 * @return 0 on success, or negative value on error
744 */
flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data * data,struct jesd216_sfdp_header * header,struct jesd216_bfp * bfp,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])745 static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
746 struct jesd216_sfdp_header *header,
747 struct jesd216_bfp *bfp,
748 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
749 {
750 struct jesd216_instr instr;
751 struct jesd216_bfp_dw16 dw16;
752 struct jesd216_bfp_dw15 dw15;
753 struct jesd216_bfp_dw14 dw14;
754 uint8_t addr_width;
755 uint8_t mode_cmd;
756 int ret;
757
758 /* Read DW14 to determine the polling method we should use while programming */
759 ret = jesd216_bfp_decode_dw14(&header->phdr[0], bfp, &dw14);
760 if (ret < 0) {
761 /* Default to legacy polling mode */
762 dw14.poll_options = 0x0;
763 }
764 if (dw14.poll_options & BIT(1)) {
765 /* Read instruction used for polling is 0x70 */
766 data->legacy_poll = false;
767 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
768 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x70,
769 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
770 } else {
771 /* Read instruction used for polling is 0x05 */
772 data->legacy_poll = true;
773 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
774 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
775 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
776 }
777
778 addr_width = jesd216_bfp_addrbytes(bfp) ==
779 JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B ? 32 : 24;
780
781 /* Check to see if we can enable 4 byte addressing */
782 ret = jesd216_bfp_decode_dw16(&header->phdr[0], bfp, &dw16);
783 if (ret == 0) {
784 /* Attempt to enable 4 byte addressing */
785 ret = flash_flexspi_nor_4byte_enable(data, flexspi_lut,
786 dw16.enter_4ba);
787 if (ret == 0) {
788 /* Use 4 byte address width */
789 addr_width = 32;
790 /* Update LUT for ERASE_SECTOR and ERASE_BLOCK to use 32 bit addr */
791 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
792 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
793 SPI_NOR_CMD_SE, kFLEXSPI_Command_RADDR_SDR,
794 kFLEXSPI_1PAD, addr_width);
795 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
796 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
797 SPI_NOR_CMD_BE, kFLEXSPI_Command_RADDR_SDR,
798 kFLEXSPI_1PAD, addr_width);
799 }
800 }
801 /* Extract the read command.
802 * Note- enhanced XIP not currently supported, nor is 4-4-4 mode.
803 */
804 if (jesd216_bfp_read_support(&header->phdr[0], bfp,
805 JESD216_MODE_144, &instr) > 0) {
806 LOG_DBG("Enable 144 mode");
807 /* Configure for 144 QUAD read mode */
808 if (instr.mode_clocks == 2) {
809 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
810 } else if (instr.mode_clocks == 1) {
811 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
812 } else if (instr.mode_clocks == 0) {
813 /* Just send dummy cycles during mode clock period */
814 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
815 } else {
816 return -ENOTSUP;
817 }
818 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
819 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
820 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, addr_width);
821 /* Note- we always set mode bits to 0x0 */
822 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
823 mode_cmd, kFLEXSPI_4PAD, 0x00,
824 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, instr.wait_states);
825 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
826 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04,
827 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
828 /* Read 1S-4S-4S enable method */
829 ret = jesd216_bfp_decode_dw15(&header->phdr[0], bfp, &dw15);
830 if (ret == 0) {
831 ret = flash_flexspi_nor_quad_enable(data, flexspi_lut,
832 dw15.qer);
833 if (ret == 0) {
834 /* Now, install 1S-1S-4S page program command */
835 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
836 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
837 SPI_NOR_CMD_PP_1_1_4, kFLEXSPI_Command_RADDR_SDR,
838 kFLEXSPI_1PAD, addr_width);
839 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
840 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD,
841 0x4, kFLEXSPI_Command_STOP,
842 kFLEXSPI_1PAD, 0x0);
843 }
844 }
845
846 } else if (jesd216_bfp_read_support(&header->phdr[0], bfp,
847 JESD216_MODE_122, &instr) > 0) {
848 LOG_DBG("Enable 122 mode");
849 if (instr.mode_clocks == 4) {
850 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
851 } else if (instr.mode_clocks == 2) {
852 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
853 } else if (instr.mode_clocks == 1) {
854 mode_cmd = kFLEXSPI_Command_MODE2_SDR;
855 } else if (instr.mode_clocks == 0) {
856 /* Just send dummy cycles during mode clock period */
857 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
858 } else {
859 return -ENOTSUP;
860 }
861 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
862 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
863 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_2PAD, addr_width);
864 /* Note- we always set mode bits to 0x0 */
865 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
866 mode_cmd, kFLEXSPI_2PAD, 0x0,
867 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_2PAD, instr.wait_states);
868 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
869 kFLEXSPI_Command_READ_SDR, kFLEXSPI_2PAD, 0x02,
870 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
871 /* Now, install 1S-1S-2S page program command */
872 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
873 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_2,
874 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
875 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
876 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_2PAD, 0x4,
877 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
878 }
879 /* Default to 111 mode if no support exists, leave READ/WRITE untouched */
880
881 return 0;
882 }
883
884 /* Helper so we can avoid flash access while performing SFDP probe */
flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data * dev_data,off_t offset,void * data,size_t len)885 static int flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data *dev_data,
886 off_t offset, void *data, size_t len)
887 {
888 flexspi_transfer_t transfer = {
889 .deviceAddress = offset,
890 .port = dev_data->port,
891 .cmdType = kFLEXSPI_Read,
892 .seqIndex = READ_JESD216,
893 .SeqNumber = 1,
894 .data = (uint32_t *)data,
895 .dataSize = len,
896 };
897
898 /* Get SFDP data */
899 return memc_flexspi_transfer(&dev_data->controller, &transfer);
900 }
901
902
903 #if defined(CONFIG_FLASH_JESD216_API)
904
flash_flexspi_nor_sfdp_read(const struct device * dev,off_t offset,void * data,size_t len)905 static int flash_flexspi_nor_sfdp_read(const struct device *dev,
906 off_t offset, void *data, size_t len)
907 {
908 struct flash_flexspi_nor_data *dev_data = dev->data;
909
910 return flash_flexspi_nor_sfdp_read_helper(dev_data, offset, data, len);
911 }
912
913 #endif
914
915 /* Helper to configure IS25 flash, by clearing read param bits */
flash_flexspi_nor_is25_clear_read_param(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint32_t * read_params)916 static int flash_flexspi_nor_is25_clear_read_param(struct flash_flexspi_nor_data *data,
917 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
918 uint32_t *read_params)
919 {
920 int ret;
921 /* Install Set Read Parameters (Volatile) command */
922 flexspi_transfer_t transfer = {
923 .deviceAddress = 0,
924 .port = data->port,
925 .seqIndex = SCRATCH_CMD,
926 .SeqNumber = 1,
927 .data = read_params,
928 .dataSize = 1,
929 .cmdType = kFLEXSPI_Write,
930 };
931 flexspi_device_config_t config = {
932 .flexspiRootClk = MHZ(50),
933 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
934 .ARDSeqNumber = 1,
935 .ARDSeqIndex = READ,
936 };
937
938 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
939 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC0,
940 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
941 ret = memc_flexspi_set_device_config(&data->controller,
942 &config,
943 (uint32_t *)flexspi_lut,
944 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
945 data->port);
946 if (ret < 0) {
947 return ret;
948 }
949 return memc_flexspi_transfer(&data->controller, &transfer);
950 }
951
952 /* Checks JEDEC ID of flash. If supported, installs custom LUT table */
flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])953 static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
954 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
955 {
956 int ret;
957 uint32_t vendor_id;
958 uint32_t read_params;
959
960 ret = flash_flexspi_nor_read_id_helper(data, (uint8_t *)&vendor_id);
961 if (ret < 0) {
962 return ret;
963 }
964
965 /* Switch on manufacturer and vendor ID */
966 switch (vendor_id & 0xFFFFFF) {
967 case 0x16609d: /* IS25LP032 flash, needs P[4:3] cleared with same method as IS25WP */
968 case 0x17609d: /* IS25LP064 */
969 case 0x18609d: /* IS25LP128 */
970 read_params = 0xE0U;
971 ret = flash_flexspi_nor_is25_clear_read_param(data, flexspi_lut, &read_params);
972 if (ret < 0) {
973 while (1) {
974 /*
975 * Spin here, this flash won't configure correctly.
976 * We can't print a warning, as we are unlikely to
977 * be able to XIP at this point.
978 */
979 }
980 }
981 /* Still return an error- we want the JEDEC configuration to run */
982 return -ENOTSUP;
983 case 0x16709d: /* IS25WP032 */
984 case 0x17709d: /* IS25WP064 */
985 case 0x18709d: /* IS25WP128 */
986 /*
987 * IS25WP flash. We can support this flash with the JEDEC probe,
988 * but we need to insure P[6:3] are at the default value
989 */
990 read_params = 0;
991 ret = flash_flexspi_nor_is25_clear_read_param(data, flexspi_lut, &read_params);
992 if (ret < 0) {
993 while (1) {
994 /*
995 * Spin here, this flash won't configure correctly.
996 * We can't print a warning, as we are unlikely to
997 * be able to XIP at this point.
998 */
999 }
1000 }
1001 /* Still return an error- we want the JEDEC configuration to run */
1002 return -ENOTSUP;
1003 case 0x2040ef:
1004 /* W25Q512JV-IQ/IN flash, use 4 byte read/write */
1005 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1006 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1007 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1008 /* Flash needs 6 dummy cycles (at 104MHz) */
1009 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1010 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 6,
1011 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1012 /* Only 1S-1S-4S page program supported */
1013 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1014 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
1015 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1016 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1017 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1018 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1019 /* Update ERASE commands for 4 byte mode */
1020 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1021 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1022 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1023 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1024 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1025 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1026 /* Read instruction used for polling is 0x05 */
1027 data->legacy_poll = true;
1028 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1029 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1030 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1031 /* Device uses bit 1 of status reg 2 for QE */
1032 return flash_flexspi_nor_quad_enable(data, flexspi_lut,
1033 JESD216_DW15_QER_VAL_S2B1v5);
1034 case 0x2060ef:
1035 /* W25Q512NW-IQ/IN flash, use 4 byte read/write */
1036 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1037 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1038 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1039 /* Flash needs 8 dummy cycles (at 133MHz) */
1040 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1041 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
1042 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1043 /* Only 1S-1S-4S page program supported */
1044 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1045 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
1046 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1047 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1048 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1049 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1050 /* Update ERASE commands for 4 byte mode */
1051 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1052 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1053 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1054 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1055 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1056 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1057 /* Read instruction used for polling is 0x05 */
1058 data->legacy_poll = true;
1059 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1060 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1061 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1062 /* Device uses bit 1 of status reg 2 for QE */
1063 return flash_flexspi_nor_quad_enable(data, flexspi_lut,
1064 JESD216_DW15_QER_VAL_S2B1v5);
1065 case 0x3A25C2:
1066 /* MX25U51245G flash, use 4 byte read/write */
1067 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1068 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1069 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1070 /* Flash needs 10 dummy cycles */
1071 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1072 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 10,
1073 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1074 /* Only 1S-4S-4S page program supported */
1075 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1076 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_4_4_4B,
1077 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1078 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1079 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1080 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1081 /* Update ERASE commands for 4 byte mode */
1082 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1083 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1084 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1085 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1086 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1087 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1088 /* Read instruction used for polling is 0x05 */
1089 data->legacy_poll = true;
1090 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1091 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1092 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1093 /* Device uses bit 6 of status reg 1 for QE */
1094 return flash_flexspi_nor_quad_enable(data, flexspi_lut, JESD216_DW15_QER_VAL_S1B6);
1095 case 0x19ba20: /* MT25QL256 */
1096 case 0x20ba20: /* MT25QL512 */
1097 case 0x21ba20: /* MT25QL01G */
1098 case 0x22ba20: /* MT25QL02G */
1099 case 0x19bb20: /* MT25QU256 */
1100 case 0x20bb20: /* MT25QU512 */
1101 case 0x21bb20: /* MT25QU01G */
1102 case 0x22bb20: /* MT25QU02G */
1103 /* MT25Q flash with more than 32MB, use 4 byte read/write */
1104 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
1105 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
1106 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1107 /* Flash needs 10 dummy cycles */
1108 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
1109 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 10,
1110 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
1111 /* Update PROGRAM commands for 4 byte 1S-4S-4S mode */
1112 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
1113 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_4_4_4B,
1114 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
1115 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
1116 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
1117 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
1118 /* Update ERASE commands for 4 byte mode */
1119 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
1120 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
1121 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
1122 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
1123 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
1124 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
1125 /* Read instruction used for polling is 0x05 */
1126 data->legacy_poll = true;
1127 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
1128 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
1129 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
1130 /* Device has no QE bit, 1-4-4 and 1-1-4 is always enabled */
1131 return 0;
1132 default:
1133 return -ENOTSUP;
1134 }
1135 }
1136
1137 /* Probe parameters from flash SFDP header, and use them to configure the FlexSPI */
flash_flexspi_nor_probe(struct flash_flexspi_nor_data * data)1138 static int flash_flexspi_nor_probe(struct flash_flexspi_nor_data *data)
1139 {
1140 /* JESD216B defines up to 23 basic flash parameters */
1141 uint32_t param_buf[23];
1142 /* Space to store SFDP header and first parameter header */
1143 uint8_t sfdp_buf[JESD216_SFDP_SIZE(1)] __aligned(4);
1144 struct jesd216_bfp *bfp = (struct jesd216_bfp *)param_buf;
1145 struct jesd216_sfdp_header *header = (struct jesd216_sfdp_header *)sfdp_buf;
1146 int ret;
1147 unsigned int key = 0U;
1148
1149 flexspi_device_config_t config = {
1150 .flexspiRootClk = MHZ(50),
1151 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
1152 .ARDSeqNumber = 1,
1153 .ARDSeqIndex = READ,
1154 };
1155
1156 if (memc_flexspi_is_running_xip(&data->controller)) {
1157 /*
1158 * ==== ENTER CRITICAL SECTION ====
1159 * No flash access should be performed in critical section. All
1160 * code and data accessed must reside in ram.
1161 */
1162 key = irq_lock();
1163 memc_flexspi_wait_bus_idle(&data->controller);
1164 }
1165
1166 /* SFDP spec requires that we downclock the FlexSPI to 50MHz or less */
1167 ret = memc_flexspi_update_clock(&data->controller, &config,
1168 data->port, MHZ(50));
1169 if (ret < 0) {
1170 goto _exit;
1171 }
1172
1173 /* Setup initial LUT table and FlexSPI configuration */
1174 memcpy(flexspi_probe_lut, flash_flexspi_nor_base_lut,
1175 sizeof(flash_flexspi_nor_base_lut));
1176
1177 ret = memc_flexspi_set_device_config(&data->controller, &config,
1178 (uint32_t *)flexspi_probe_lut,
1179 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
1180 data->port);
1181 if (ret < 0) {
1182 goto _exit;
1183 }
1184
1185 /* First, check if the JEDEC ID of this flash has explicit support
1186 * in this driver
1187 */
1188 ret = flash_flexspi_nor_check_jedec(data, flexspi_probe_lut);
1189 if (ret == 0) {
1190 /* Flash was supported, SFDP probe not needed */
1191 goto _program_lut;
1192 }
1193
1194 ret = flash_flexspi_nor_sfdp_read_helper(data, 0, sfdp_buf, sizeof(sfdp_buf));
1195 if (ret < 0) {
1196 goto _exit;
1197 }
1198
1199 LOG_DBG("SFDP header magic: 0x%x", header->magic);
1200 if (jesd216_sfdp_magic(header) != JESD216_SFDP_MAGIC) {
1201 /* Header was read incorrectly */
1202 LOG_WRN("Invalid header, using legacy SPI mode");
1203 data->legacy_poll = true;
1204 goto _program_lut;
1205 }
1206
1207 if (header->phdr[0].len_dw > ARRAY_SIZE(param_buf)) {
1208 /* Not enough space to read parameter table */
1209 ret = -ENOBUFS;
1210 goto _exit;
1211 }
1212
1213 /* Read basic flash parameter table */
1214 ret = flash_flexspi_nor_sfdp_read_helper(data,
1215 jesd216_param_addr(&header->phdr[0]),
1216 param_buf,
1217 sizeof(uint32_t) * header->phdr[0].len_dw);
1218 if (ret < 0) {
1219 goto _exit;
1220 }
1221
1222 /* Configure flash */
1223 ret = flash_flexspi_nor_config_flash(data, header, bfp,
1224 flexspi_probe_lut);
1225 if (ret < 0) {
1226 goto _exit;
1227 }
1228
1229 _program_lut:
1230 /*
1231 * Update the FlexSPI with the config structure provided
1232 * from devicetree and the configured LUT
1233 */
1234 ret = memc_flexspi_set_device_config(&data->controller, &data->config,
1235 (uint32_t *)flexspi_probe_lut,
1236 FLEXSPI_INSTR_PROG_END * MEMC_FLEXSPI_CMD_PER_SEQ,
1237 data->port);
1238 if (ret < 0) {
1239 return ret;
1240 }
1241
1242 _exit:
1243 memc_flexspi_reset(&data->controller);
1244
1245 if (memc_flexspi_is_running_xip(&data->controller)) {
1246 /* ==== EXIT CRITICAL SECTION ==== */
1247 irq_unlock(key);
1248 }
1249
1250 return ret;
1251 }
1252
flash_flexspi_nor_init(const struct device * dev)1253 static int flash_flexspi_nor_init(const struct device *dev)
1254 {
1255 const struct flash_flexspi_nor_config *config = dev->config;
1256 struct flash_flexspi_nor_data *data = dev->data;
1257 uint32_t vendor_id;
1258
1259 /* First step- use ROM pointer to controller device to create
1260 * a copy of the device structure in RAM we can use while in
1261 * critical sections of code.
1262 */
1263 memcpy(&data->controller, config->controller, sizeof(struct device));
1264
1265 if (!device_is_ready(&data->controller)) {
1266 LOG_ERR("Controller device is not ready");
1267 return -ENODEV;
1268 }
1269
1270 if (flash_flexspi_nor_probe(data)) {
1271 if (memc_flexspi_is_running_xip(&data->controller)) {
1272 /* We can't continue from here- the LUT stored in
1273 * the FlexSPI will be invalid so we cannot XIP.
1274 * Instead, spin here
1275 */
1276 while (1) {
1277 /* Spin */
1278 }
1279 }
1280 LOG_ERR("SFDP probe failed");
1281 return -EIO;
1282 }
1283
1284 /* Set the FlexSPI to full clock speed */
1285 if (memc_flexspi_update_clock(&data->controller, &data->config,
1286 data->port, data->config.flexspiRootClk)) {
1287 LOG_ERR("Could not set flexspi clock speed");
1288 return -ENOTSUP;
1289 }
1290
1291
1292 memc_flexspi_reset(&data->controller);
1293
1294 if (flash_flexspi_nor_read_id(dev, (uint8_t *)&vendor_id)) {
1295 LOG_ERR("Could not read vendor id");
1296 return -EIO;
1297 }
1298 LOG_DBG("Vendor id: 0x%0x", vendor_id);
1299
1300 return 0;
1301 }
1302
1303 static DEVICE_API(flash, flash_flexspi_nor_api) = {
1304 .erase = flash_flexspi_nor_erase,
1305 .write = flash_flexspi_nor_write,
1306 .read = flash_flexspi_nor_read,
1307 .get_parameters = flash_flexspi_nor_get_parameters,
1308 .get_size = flash_flexspi_nor_get_size,
1309 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
1310 .page_layout = flash_flexspi_nor_pages_layout,
1311 #endif
1312 #if defined(CONFIG_FLASH_JESD216_API)
1313 .sfdp_read = flash_flexspi_nor_sfdp_read,
1314 .read_jedec_id = flash_flexspi_nor_read_id,
1315 #endif
1316 };
1317
1318 #define CONCAT3(x, y, z) x ## y ## z
1319
1320 #define CS_INTERVAL_UNIT(unit) \
1321 CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
1322
1323 #define AHB_WRITE_WAIT_UNIT(unit) \
1324 CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
1325
1326 #define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
1327 { \
1328 .flexspiRootClk = DT_INST_PROP(n, spi_max_frequency), \
1329 .flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
1330 .CSIntervalUnit = \
1331 CS_INTERVAL_UNIT( \
1332 DT_INST_PROP(n, cs_interval_unit)), \
1333 .CSInterval = DT_INST_PROP(n, cs_interval), \
1334 .CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
1335 .CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
1336 .dataValidTime = DT_INST_PROP(n, data_valid_time), \
1337 .columnspace = DT_INST_PROP(n, column_space), \
1338 .enableWordAddress = DT_INST_PROP(n, word_addressable), \
1339 .AWRSeqIndex = 0, \
1340 .AWRSeqNumber = 0, \
1341 .ARDSeqIndex = READ, \
1342 .ARDSeqNumber = 1, \
1343 .AHBWriteWaitUnit = \
1344 AHB_WRITE_WAIT_UNIT( \
1345 DT_INST_PROP(n, ahb_write_wait_unit)), \
1346 .AHBWriteWaitInterval = \
1347 DT_INST_PROP(n, ahb_write_wait_interval), \
1348 } \
1349
1350 #define FLASH_FLEXSPI_NOR(n) \
1351 static const struct flash_flexspi_nor_config \
1352 flash_flexspi_nor_config_##n = { \
1353 .controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
1354 }; \
1355 static struct flash_flexspi_nor_data \
1356 flash_flexspi_nor_data_##n = { \
1357 .config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
1358 .port = DT_INST_REG_ADDR(n), \
1359 .size = DT_INST_PROP(n, size) / 8, \
1360 .layout = { \
1361 .pages_count = DT_INST_PROP(n, size) / 8 \
1362 / SPI_NOR_SECTOR_SIZE, \
1363 .pages_size = SPI_NOR_SECTOR_SIZE, \
1364 }, \
1365 .flash_parameters = { \
1366 .write_block_size = NOR_WRITE_SIZE, \
1367 .erase_value = NOR_ERASE_VALUE, \
1368 }, \
1369 }; \
1370 \
1371 DEVICE_DT_INST_DEFINE(n, \
1372 flash_flexspi_nor_init, \
1373 NULL, \
1374 &flash_flexspi_nor_data_##n, \
1375 &flash_flexspi_nor_config_##n, \
1376 POST_KERNEL, \
1377 CONFIG_FLASH_INIT_PRIORITY, \
1378 &flash_flexspi_nor_api);
1379
1380 DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)
1381
