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Searched defs:width (Results 1 – 10 of 10) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_crypto_core_crc_v2.c200 uint32_t width, in Cy_Crypto_Core_V2_Crc_CalcInit()
257 cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V2_Crc_CalcStart()
332 cy_en_crypto_status_t Cy_Crypto_Core_V2_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V2_Crc_CalcFinish()
382 uint32_t width, in Cy_Crypto_Core_V2_Crc_Calc()
Dcy_crypto_core_crc_v1.c202 uint32_t width, in Cy_Crypto_Core_V1_Crc_CalcInit()
260 cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcStart(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V1_Crc_CalcStart()
336 cy_en_crypto_status_t Cy_Crypto_Core_V1_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t … in Cy_Crypto_Core_V1_Crc_CalcFinish()
382 uint32_t width, in Cy_Crypto_Core_V1_Crc_Calc()
Dcy_sd_host.c290 #define CY_SD_HOST_IS_SD_BUS_WIDTH_VALID(width) ((CY_SD_HOST_BUS_WIDTH_1_BIT == (width)) ||… argument
293 #define CY_SD_HOST_IS_EMMC_BUS_WIDTH_VALID(width) ((CY_SD_HOST_BUS_WIDTH_1_BIT == (width)) ||… argument
297 #define CY_SD_HOST_IS_BUS_WIDTH_VALID(width, cardType) ((CY_SD_HOST_EMMC == (cardType)) ? \ argument
1817 cy_en_sd_host_bus_width_t width, in Cy_SD_Host_SetBusWidth()
4363 cy_en_sd_host_bus_width_t width) in Cy_SD_Host_SetHostBusWidth()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_crypto_core_crc.h281 uint32_t width, in Cy_Crypto_Core_Crc_CalcInit()
329 … uint32_t width, uint32_t lfsrInitState) in Cy_Crypto_Core_Crc_CalcStart()
408 …_en_crypto_status_t Cy_Crypto_Core_Crc_CalcFinish(CRYPTO_Type *base, uint32_t width, uint32_t *crc) in Cy_Crypto_Core_Crc_CalcFinish()
457 uint32_t width, uint32_t *crc, in Cy_Crypto_Core_Crc_Calc()
Dcy_scb_uart.h964 #define CY_SCB_UART_IS_DATA_WIDTH_VALID(width) ( ((width) >= 5UL) && ((width) <= 9UL) ) argument
969 #define CY_SCB_UART_IS_RX_BREAK_WIDTH_VALID(base, width) ( ((width) >= (_FLD2VAL(SCB_RX_CTRL_DAT… argument
971 #define CY_SCB_UART_IS_TX_BREAK_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 16UL)… argument
973 #define CY_SCB_UART_IS_MUTLI_PROC_VALID(mp, mode, width, parity) ( (mp) ? ((CY_SCB_UART_STANDARD… argument
Dcy_scb_spi.h916 #define CY_SCB_SPI_IS_DATA_WIDTH_VALID(width) ( ((width) >= 4UL) && ((width) <= 32UL) ) argument
Dcy_smif.h764 #define CY_SMIF_TXFR_WIDTH_VALID(width) ((CY_SMIF_WIDTH_SINGLE == (width)) || \ argument
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_pwm.c472 …uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->tcpwm.clock_hz / _CYHAL_PWM_US_PER_SEC… in cyhal_pwm_set_period() local
489 uint32_t width = (uint32_t)(duty_cycle * 0.01f * period); in cyhal_pwm_set_duty_cycle() local
/hal_infineon-latest/mtb-hal-cat1/include/
Dcyhal_crc.h104 uint32_t width; //!< Bit width of the CRC member
/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_crc_impl.h41 #define _cyhal_crc_calcinit(base, width, polynomial, data_reverse, data_xor, rem_reverse, rem_xor, … argument