1 /*
2 * Copyright 2023 Renesas Electronics Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #define DT_DRV_COMPAT renesas_smartbond_regulator
7
8 #include <stdint.h>
9
10 #include <zephyr/drivers/regulator.h>
11 #include <zephyr/logging/log.h>
12 #include <zephyr/sys/linear_range.h>
13 #include <zephyr/pm/pm.h>
14 #include <zephyr/pm/device.h>
15 #include <DA1469xAB.h>
16 #include <zephyr/devicetree.h>
17
18 LOG_MODULE_REGISTER(regulator_da1469x, CONFIG_REGULATOR_LOG_LEVEL);
19
20 #define DCDC_REQUESTED (DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Msk |\
21 DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Msk)
22
23 #define DA1469X_LDO_3V0_MODE_VBAT BIT(8)
24 #define DA1469X_LDO_3V0_MODE_VBUS BIT(9)
25
26 #define PLL_FREQ DT_PROP(DT_NODELABEL(pll), clock_frequency)
27 #define PLL_VDD_UV 1200000
28
29 static const struct linear_range curren_ranges[] = {
30 LINEAR_RANGE_INIT(30000, 30000, 0, 31),
31 };
32
33 static const struct linear_range vdd_clamp_ranges[] = {
34 LINEAR_RANGE_INIT(706000, 0, 15, 15),
35 LINEAR_RANGE_INIT(798000, 0, 14, 14),
36 LINEAR_RANGE_INIT(828000, 0, 13, 13),
37 LINEAR_RANGE_INIT(861000, 0, 11, 11),
38 LINEAR_RANGE_INIT(862000, 0, 12, 12),
39 LINEAR_RANGE_INIT(889000, 0, 10, 10),
40 LINEAR_RANGE_INIT(918000, 0, 9, 9),
41 LINEAR_RANGE_INIT(946000, 0, 3, 3),
42 LINEAR_RANGE_INIT(952000, 0, 8, 8),
43 LINEAR_RANGE_INIT(978000, 0, 2, 2),
44 LINEAR_RANGE_INIT(1005000, 0, 1, 1),
45 LINEAR_RANGE_INIT(1030000, 0, 7, 7),
46 LINEAR_RANGE_INIT(1037000, 0, 0, 0),
47 LINEAR_RANGE_INIT(1058000, 0, 6, 6),
48 LINEAR_RANGE_INIT(1089000, 0, 5, 5),
49 LINEAR_RANGE_INIT(1120000, 0, 4, 4),
50 };
51
52 static const struct linear_range vdd_ranges[] = {
53 LINEAR_RANGE_INIT(900000, 100000, 0, 3),
54 };
55
56 static const struct linear_range vdd_sleep_ranges[] = {
57 LINEAR_RANGE_INIT(750000, 50000, 0, 3),
58 };
59
60 static const struct linear_range v14_ranges[] = {
61 LINEAR_RANGE_INIT(1200000, 50000, 0, 7),
62 };
63
64 static const struct linear_range v30_ranges[] = {
65 LINEAR_RANGE_INIT(3000000, 300000, 0, 1),
66 };
67
68 static const struct linear_range v18_ranges[] = {
69 LINEAR_RANGE_INIT(1200000, 600000, 0, 1),
70 };
71
72 static const struct linear_range v18p_ranges[] = {
73 LINEAR_RANGE_INIT(1800000, 0, 0, 0),
74 };
75
76 enum da1469x_rail {
77 VDD_CLAMP,
78 VDD_SLEEP,
79 VDD,
80 V14,
81 V18,
82 V18P,
83 V30,
84 };
85
86 struct dcdc_regs {
87 uint32_t v18;
88 uint32_t v18p;
89 uint32_t vdd;
90 uint32_t v14;
91 uint32_t ctrl1;
92 };
93
94 static struct dcdc_regs dcdc_state;
95
96 struct regulator_da1469x_desc {
97 const struct linear_range *voltage_ranges;
98 const struct linear_range *current_ranges;
99 uint8_t voltage_range_count;
100 /* Bit from POWER_CTRL_REG that can be used for enabling rail */
101 uint32_t enable_mask;
102 uint32_t voltage_idx_mask;
103 volatile uint32_t *dcdc_register;
104 uint32_t *dcdc_register_shadow;
105 };
106
107 static const struct regulator_da1469x_desc vdd_desc = {
108 .voltage_ranges = vdd_ranges,
109 .current_ranges = curren_ranges,
110 .voltage_range_count = ARRAY_SIZE(vdd_ranges),
111 .enable_mask = CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk,
112 .voltage_idx_mask = CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Msk,
113 .dcdc_register = &DCDC->DCDC_VDD_REG,
114 .dcdc_register_shadow = &dcdc_state.vdd,
115 };
116
117 static const struct regulator_da1469x_desc vdd_sleep_desc = {
118 .voltage_ranges = vdd_sleep_ranges,
119 .voltage_range_count = ARRAY_SIZE(vdd_sleep_ranges),
120 .enable_mask = CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk,
121 .voltage_idx_mask = CRG_TOP_POWER_CTRL_REG_VDD_SLEEP_LEVEL_Msk,
122 };
123
124 static const struct regulator_da1469x_desc vdd_clamp_desc = {
125 .voltage_ranges = vdd_clamp_ranges,
126 .voltage_range_count = ARRAY_SIZE(vdd_clamp_ranges),
127 .enable_mask = 0,
128 .voltage_idx_mask = CRG_TOP_POWER_CTRL_REG_VDD_CLAMP_LEVEL_Msk,
129 };
130
131 static const struct regulator_da1469x_desc v14_desc = {
132 .voltage_ranges = v14_ranges,
133 .current_ranges = curren_ranges,
134 .voltage_range_count = ARRAY_SIZE(v14_ranges),
135 .enable_mask = CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk,
136 .voltage_idx_mask = CRG_TOP_POWER_CTRL_REG_V14_LEVEL_Msk,
137 .dcdc_register = &DCDC->DCDC_V14_REG,
138 .dcdc_register_shadow = &dcdc_state.v14,
139 };
140
141 static const struct regulator_da1469x_desc v18_desc = {
142 .voltage_ranges = v18_ranges,
143 .current_ranges = curren_ranges,
144 .voltage_range_count = ARRAY_SIZE(v18_ranges),
145 .enable_mask = CRG_TOP_POWER_CTRL_REG_LDO_1V8_ENABLE_Msk |
146 CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Msk,
147 .voltage_idx_mask = CRG_TOP_POWER_CTRL_REG_V18_LEVEL_Msk,
148 .dcdc_register = &DCDC->DCDC_V18_REG,
149 .dcdc_register_shadow = &dcdc_state.v18,
150 };
151
152 static const struct regulator_da1469x_desc v18p_desc = {
153 .voltage_ranges = v18p_ranges,
154 .current_ranges = curren_ranges,
155 .voltage_range_count = ARRAY_SIZE(v18p_ranges),
156 .enable_mask = CRG_TOP_POWER_CTRL_REG_LDO_1V8P_ENABLE_Msk |
157 CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Msk,
158 .voltage_idx_mask = 0,
159 .dcdc_register = &DCDC->DCDC_V18P_REG,
160 .dcdc_register_shadow = &dcdc_state.v18p,
161 };
162
163 static const struct regulator_da1469x_desc v30_desc = {
164 .voltage_ranges = v30_ranges,
165 .voltage_range_count = ARRAY_SIZE(v30_ranges),
166 .enable_mask = CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Msk |
167 CRG_TOP_POWER_CTRL_REG_LDO_3V0_MODE_Msk,
168 .voltage_idx_mask = CRG_TOP_POWER_CTRL_REG_V30_LEVEL_Msk,
169 };
170
171 #define DA1469X_LDO_VDD_CLAMP_RET 0
172 #define DA1469X_LDO_VDD_SLEEP_RET 0
173 #define DA1469X_LDO_VDD_RET CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk
174 #define DA1469X_LDO_V14_RET 0
175 #define DA1469X_LDO_V18_RET CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Msk
176 #define DA1469X_LDO_V18P_RET CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Msk
177 #define DA1469X_LDO_V30_RET CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Msk
178
179 struct regulator_da1469x_config {
180 struct regulator_common_config common;
181 enum da1469x_rail rail;
182 const struct regulator_da1469x_desc *desc;
183 uint32_t power_bits;
184 uint32_t dcdc_bits;
185 };
186
187 struct regulator_da1469x_data {
188 struct regulator_common_data common;
189 };
190
regulator_da1469x_enable(const struct device * dev)191 static int regulator_da1469x_enable(const struct device *dev)
192 {
193 const struct regulator_da1469x_config *config = dev->config;
194 uint32_t reg_val;
195
196 if (config->desc->enable_mask & config->power_bits) {
197 reg_val = CRG_TOP->POWER_CTRL_REG & ~(config->desc->enable_mask);
198 reg_val |= config->power_bits & config->desc->enable_mask;
199 CRG_TOP->POWER_CTRL_REG |= reg_val;
200 }
201
202 if (config->desc->dcdc_register) {
203 reg_val = *config->desc->dcdc_register &
204 ~(DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Msk |
205 DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Msk);
206 reg_val |= config->dcdc_bits;
207 *config->desc->dcdc_register_shadow = reg_val;
208 *config->desc->dcdc_register = reg_val;
209 }
210
211 /*
212 * Enable DCDC if:
213 * 1. it was not already enabled, and
214 * 2. VBAT is above minimal value
215 * 3. Just turned on rail requested DCDC
216 */
217 if (((DCDC->DCDC_CTRL1_REG & DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk) == 0) &&
218 (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk) &&
219 config->dcdc_bits & DCDC_REQUESTED) {
220 DCDC->DCDC_CTRL1_REG |= DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk;
221 dcdc_state.ctrl1 = DCDC->DCDC_CTRL1_REG;
222 }
223
224 return 0;
225 }
226
regulator_da1469x_disable(const struct device * dev)227 static int regulator_da1469x_disable(const struct device *dev)
228 {
229 const struct regulator_da1469x_config *config = dev->config;
230 uint32_t reg_val;
231
232 if (config->desc->enable_mask & config->power_bits) {
233 CRG_TOP->POWER_CTRL_REG &= ~(config->desc->enable_mask &
234 config->power_bits);
235 }
236 if (config->desc->dcdc_register) {
237 reg_val = *config->desc->dcdc_register &
238 ~(DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Msk |
239 DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Msk);
240 *config->desc->dcdc_register_shadow = reg_val;
241 *config->desc->dcdc_register = reg_val;
242 }
243
244 /* Turn off DCDC if it's no longer requested by any rail */
245 if ((DCDC->DCDC_CTRL1_REG & DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk) &&
246 (DCDC->DCDC_VDD_REG & DCDC_REQUESTED) == 0 &&
247 (DCDC->DCDC_V14_REG & DCDC_REQUESTED) == 0 &&
248 (DCDC->DCDC_V18_REG & DCDC_REQUESTED) == 0 &&
249 (DCDC->DCDC_V18P_REG & DCDC_REQUESTED) == 0) {
250 DCDC->DCDC_CTRL1_REG &= ~DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk;
251 dcdc_state.ctrl1 = DCDC->DCDC_CTRL1_REG;
252 }
253
254 return 0;
255 }
256
regulator_da1469x_count_voltages(const struct device * dev)257 static unsigned int regulator_da1469x_count_voltages(const struct device *dev)
258 {
259 const struct regulator_da1469x_config *config = dev->config;
260
261 return linear_range_group_values_count(config->desc->voltage_ranges,
262 config->desc->voltage_range_count);
263 }
264
regulator_da1469x_list_voltage(const struct device * dev,unsigned int idx,int32_t * volt_uv)265 static int regulator_da1469x_list_voltage(const struct device *dev,
266 unsigned int idx,
267 int32_t *volt_uv)
268 {
269 const struct regulator_da1469x_config *config = dev->config;
270
271 if (config->desc->voltage_ranges) {
272 return linear_range_group_get_value(config->desc->voltage_ranges,
273 config->desc->voltage_range_count,
274 idx, volt_uv);
275 }
276
277 return -ENOTSUP;
278 }
279
regulator_da1469x_set_voltage(const struct device * dev,int32_t min_uv,int32_t max_uv)280 static int regulator_da1469x_set_voltage(const struct device *dev, int32_t min_uv,
281 int32_t max_uv)
282 {
283 int ret;
284 const struct regulator_da1469x_config *config = dev->config;
285 uint16_t idx;
286 uint32_t mask;
287
288 if ((SystemCoreClock == PLL_FREQ) && (config->rail == VDD)) {
289 /* PLL requires that VDD be @1.2V */
290 if (max_uv < PLL_VDD_UV) {
291 return -EPERM;
292 }
293 /*
294 * The get index API should select the min voltage;
295 * make sure the correct voltage is applied.
296 */
297 if (min_uv < PLL_VDD_UV) {
298 min_uv = PLL_VDD_UV;
299 }
300 }
301
302 ret = linear_range_group_get_win_index(config->desc->voltage_ranges,
303 config->desc->voltage_range_count,
304 min_uv, max_uv, &idx);
305
306 if (ret == 0) {
307 mask = config->desc->voltage_idx_mask;
308 /*
309 * Mask is 0 for V18.
310 * Setting value 1.8V is accepted since range is valid and already checked.
311 */
312 if (mask) {
313 CRG_TOP->POWER_CTRL_REG = (CRG_TOP->POWER_CTRL_REG & ~mask) |
314 FIELD_PREP(mask, idx);
315 }
316 }
317
318 return ret;
319 }
320
regulator_da1469x_get_voltage(const struct device * dev,int32_t * volt_uv)321 static int regulator_da1469x_get_voltage(const struct device *dev,
322 int32_t *volt_uv)
323 {
324 const struct regulator_da1469x_config *config = dev->config;
325 uint16_t idx;
326
327 if (config->desc->voltage_idx_mask) {
328 idx = FIELD_GET(config->desc->voltage_idx_mask, CRG_TOP->POWER_CTRL_REG);
329 } else {
330 idx = 0;
331 }
332
333 return linear_range_group_get_value(config->desc->voltage_ranges,
334 config->desc->voltage_range_count, idx, volt_uv);
335 }
336
regulator_da1469x_set_current_limit(const struct device * dev,int32_t min_ua,int32_t max_ua)337 static int regulator_da1469x_set_current_limit(const struct device *dev,
338 int32_t min_ua, int32_t max_ua)
339 {
340 const struct regulator_da1469x_config *config = dev->config;
341 int ret;
342 uint16_t idx;
343 uint32_t reg_val;
344
345 if (config->desc->current_ranges == NULL) {
346 return -ENOTSUP;
347 }
348
349 ret = linear_range_group_get_win_index(config->desc->current_ranges,
350 1,
351 min_ua, max_ua, &idx);
352 if (ret) {
353 return ret;
354 }
355
356 /* All registers have same bits layout */
357 reg_val = *config->desc->dcdc_register & ~(DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk |
358 DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk |
359 DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Msk);
360 reg_val |= FIELD_PREP(DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk, idx);
361 reg_val |= FIELD_PREP(DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk, idx);
362 reg_val |= FIELD_PREP(DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Msk, idx);
363 *config->desc->dcdc_register_shadow = reg_val;
364 *config->desc->dcdc_register = reg_val;
365
366 return ret;
367 }
368
regulator_da1469x_get_current_limit(const struct device * dev,int32_t * curr_ua)369 static int regulator_da1469x_get_current_limit(const struct device *dev,
370 int32_t *curr_ua)
371 {
372 const struct regulator_da1469x_config *config = dev->config;
373 int ret;
374 uint16_t idx;
375
376 if (config->desc->current_ranges == NULL) {
377 return -ENOTSUP;
378 }
379 idx = FIELD_GET(DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk,
380 *config->desc->dcdc_register);
381 ret = linear_range_group_get_value(config->desc->current_ranges, 1, idx, curr_ua);
382
383 return ret;
384 }
385
386 static DEVICE_API(regulator, regulator_da1469x_api) = {
387 .enable = regulator_da1469x_enable,
388 .disable = regulator_da1469x_disable,
389 .count_voltages = regulator_da1469x_count_voltages,
390 .list_voltage = regulator_da1469x_list_voltage,
391 .set_voltage = regulator_da1469x_set_voltage,
392 .get_voltage = regulator_da1469x_get_voltage,
393 .set_current_limit = regulator_da1469x_set_current_limit,
394 .get_current_limit = regulator_da1469x_get_current_limit,
395 };
396
regulator_da1469x_init(const struct device * dev)397 static int regulator_da1469x_init(const struct device *dev)
398 {
399 const struct regulator_da1469x_config *config = dev->config;
400
401 regulator_common_data_init(dev);
402
403 if ((config->rail == V30) &&
404 (config->power_bits & CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Msk)) {
405 CRG_TOP->POWER_CTRL_REG |= CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Msk;
406 }
407
408 return regulator_common_init(dev, 0);
409 }
410
411 #if defined(CONFIG_PM_DEVICE)
regulator_da1469x_pm_action(const struct device * dev,enum pm_device_action action)412 static int regulator_da1469x_pm_action(const struct device *dev,
413 enum pm_device_action action)
414 {
415 const struct regulator_da1469x_config *config = dev->config;
416 int ret = 0;
417
418 switch (action) {
419 case PM_DEVICE_ACTION_RESUME:
420 if (config->desc->dcdc_register) {
421 *config->desc->dcdc_register = *config->desc->dcdc_register_shadow;
422 if ((CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk) &&
423 (*config->desc->dcdc_register_shadow & DCDC_REQUESTED)) {
424 DCDC->DCDC_CTRL1_REG = dcdc_state.ctrl1;
425 }
426 }
427 break;
428 case PM_DEVICE_ACTION_SUSPEND:
429 /*
430 * Shadow register is saved on each regulator API call, there is no need
431 * to save it here.
432 */
433 break;
434 default:
435 ret = -ENOTSUP;
436 }
437
438 return ret;
439 }
440 #endif
441
442 #define REGULATOR_DA1469X_DEFINE(node, id, rail_id) \
443 static struct regulator_da1469x_data data_##id; \
444 \
445 static const struct regulator_da1469x_config config_##id = { \
446 .common = REGULATOR_DT_COMMON_CONFIG_INIT(node), \
447 .desc = &id ## _desc, \
448 .power_bits = \
449 (DT_PROP(node, renesas_regulator_v30_clamp) * \
450 CRG_TOP_POWER_CTRL_REG_CLAMP_3V0_VBAT_ENABLE_Msk) | \
451 (DT_PROP(node, renesas_regulator_v30_vbus) * \
452 DA1469X_LDO_3V0_MODE_VBAT) | \
453 (DT_PROP(node, renesas_regulator_v30_vbat) * \
454 DA1469X_LDO_3V0_MODE_VBUS) | \
455 (DT_PROP(node, renesas_regulator_sleep_ldo) * \
456 (DA1469X_LDO_ ## rail_id ##_RET)) | \
457 (DT_PROP(node, renesas_regulator_v30_ref_bandgap) * \
458 CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Msk), \
459 .dcdc_bits = \
460 (DT_PROP(node, renesas_regulator_dcdc_vbat_high) * \
461 DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Msk) | \
462 (DT_PROP(node, renesas_regulator_dcdc_vbat_low) * \
463 DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Msk), \
464 .rail = rail_id, \
465 }; \
466 PM_DEVICE_DT_DEFINE(node, regulator_da1469x_pm_action); \
467 DEVICE_DT_DEFINE(node, regulator_da1469x_init, \
468 PM_DEVICE_DT_GET(node), \
469 &data_##id, \
470 &config_##id, PRE_KERNEL_1, \
471 CONFIG_REGULATOR_DA1469X_INIT_PRIORITY, \
472 ®ulator_da1469x_api);
473
474 #define REGULATOR_DA1469X_DEFINE_COND(inst, child, source) \
475 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
476 (REGULATOR_DA1469X_DEFINE( \
477 DT_INST_CHILD(inst, child), child, source)), \
478 ())
479
480 #define REGULATOR_DA1469X_DEFINE_ALL(inst) \
481 REGULATOR_DA1469X_DEFINE_COND(inst, vdd_clamp, VDD_CLAMP) \
482 REGULATOR_DA1469X_DEFINE_COND(inst, vdd_sleep, VDD_SLEEP) \
483 REGULATOR_DA1469X_DEFINE_COND(inst, vdd, VDD) \
484 REGULATOR_DA1469X_DEFINE_COND(inst, v14, V14) \
485 REGULATOR_DA1469X_DEFINE_COND(inst, v18, V18) \
486 REGULATOR_DA1469X_DEFINE_COND(inst, v18p, V18P) \
487 REGULATOR_DA1469X_DEFINE_COND(inst, v30, V30) \
488
489 DT_INST_FOREACH_STATUS_OKAY(REGULATOR_DA1469X_DEFINE_ALL)
490
