1/* 2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved. 3 * Copyright (c) 2019-2020 Jyunlin Chen <jyunlin.chen@ite.com.tw> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9#include <zephyr/dt-bindings/dt-util.h> 10#include <zephyr/dt-bindings/adc/adc.h> 11#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h> 12#include <zephyr/dt-bindings/interrupt-controller/it8xxx2-wuc.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h> 15#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h> 16#include <zephyr/dt-bindings/pwm/pwm.h> 17#include <zephyr/dt-bindings/pwm/it8xxx2_pwm.h> 18#include <zephyr/dt-bindings/sensor/it8xxx2_vcmp.h> 19#include <zephyr/dt-bindings/sensor/it8xxx2_tach.h> 20#include <zephyr/dt-bindings/gpio/gpio.h> 21#include "ite/it8xxx2-wuc-map.dtsi" 22 23/ { 24 #address-cells = <1>; 25 #size-cells = <1>; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 cpu0: cpu@0 { 31 compatible = "ite,riscv-ite", "riscv"; 32 riscv,isa = "rv32imafc_zifencei"; 33 device_type = "cpu"; 34 reg = <0>; 35 cpu-power-states = <&standby>; 36 }; 37 38 power-states { 39 standby: standby { 40 compatible = "zephyr,power-state"; 41 power-state-name = "standby"; 42 min-residency-us = <500>; 43 }; 44 }; 45 }; 46 47 soc { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges; 51 52 bbram: bb-ram@f02200 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 compatible = "ite,it8xxx2-bbram"; 56 status = "okay"; 57 reg = <0x00f02200 0xc0>; 58 }; 59 flashctrl: flash-controller@f01000 { 60 compatible = "ite,it8xxx2-flash-controller"; 61 reg = <0x00f01000 0x100>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 65 flash0: flash@80000000 { 66 compatible = "soc-nv-flash"; 67 reg = <0x80000000 DT_SIZE_M(1)>; 68 erase-block-size = <4096>; 69 write-block-size = <4>; 70 }; 71 }; 72 73 sram0: memory@80100000 { 74 compatible = "mmio-sram"; 75 reg = <0x80100000 DT_SIZE_K(60)>; 76 }; 77 ilm: ilm@f01040 { 78 compatible = "ite,it8xxx2-ilm"; 79 reg = <0xf01040 3 /* SCAR0 */ 80 0xf01043 3 81 0xf01046 3 82 0xf01049 3 83 0xf0104c 3 /* SCAR4 */ 84 0xf01081 3 /* SCAR5 */ 85 0xf01084 3 86 0xf01087 3 87 0xf0108a 3 88 0xf0108d 3 89 0xf01090 3 90 0xf01093 3 91 0xf01096 3 /* SCAR12 */ 92 0xf010b0 3 /* SCAR13 */ 93 0xf010b3 3 94 0xf010b6 3 95 0xf010b9 3 96 0xf010bc 3 97 0xf010bf 3 98 0xf010c2 3 99 0xf010c5 3 100 0xf010c8 3 101 0xf010cb 3 102 0xf010ce 3>; /* SCAR23 */ 103 }; 104 105 uart1: uart@f02700 { 106 compatible = "ns16550"; 107 reg = <0x00f02700 0x0020>; 108 status = "disabled"; 109 current-speed = <115200>; 110 clock-frequency = <1843200>; 111 interrupts = <38 IRQ_TYPE_EDGE_RISING>; 112 interrupt-parent = <&intc>; 113 reg-shift = <0>; 114 }; 115 uart2: uart@f02800 { 116 compatible = "ns16550"; 117 reg = <0x00f02800 0x0020>; 118 status = "disabled"; 119 current-speed = <460800>; 120 clock-frequency = <1843200>; 121 interrupts = <39 IRQ_TYPE_EDGE_RISING>; 122 interrupt-parent = <&intc>; 123 reg-shift = <0>; 124 }; 125 126 ite_uart1_wrapper: uartwrapper@f02720 { 127 compatible = "ite,it8xxx2-uart"; 128 reg = <0x00f02720 0x0020>; 129 status = "disabled"; 130 port-num = <1>; 131 gpios = <&gpiob 0 0>; 132 uart-dev = <&uart1>; 133 }; 134 135 ite_uart2_wrapper: uartwrapper@f02820 { 136 compatible = "ite,it8xxx2-uart"; 137 reg = <0x00f02820 0x0020>; 138 status = "disabled"; 139 port-num = <2>; 140 gpios = <&gpioh 1 0>; 141 uart-dev = <&uart2>; 142 }; 143 144 timer: timer@f01f10 { 145 compatible = "ite,it8xxx2-timer"; 146 reg = <0x00f01f10 0x0052>; 147 interrupts = <IT8XXX2_IRQ_TIMER3 IRQ_TYPE_EDGE_RISING /* Event timer */ 148 IT8XXX2_IRQ_TIMER4 IRQ_TYPE_EDGE_RISING /* Free run timer */ 149 IT8XXX2_IRQ_TIMER5 IRQ_TYPE_EDGE_RISING /* Busy wait low */ 150 IT8XXX2_IRQ_TIMER6 IRQ_TYPE_EDGE_RISING /* Busy wait high */ 151 IT8XXX2_IRQ_TIMER7 IRQ_TYPE_EDGE_RISING 152 IT8XXX2_IRQ_TIMER8 IRQ_TYPE_EDGE_RISING>; 153 interrupt-parent = <&intc>; 154 }; 155 156 gpioa: gpio@f01601 { 157 compatible = "ite,it8xxx2-gpio"; 158 reg = <0x00f01601 1 /* GPDR (set) */ 159 0x00f01610 8 /* GPCR */ 160 0x00f01661 1 /* GPDMR (get) */ 161 0x00f01671 1>; /* GPOTR */ 162 ngpios = <8>; 163 gpio-controller; 164 interrupts = <IT8XXX2_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH 165 IT8XXX2_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH 166 IT8XXX2_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH 167 IT8XXX2_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH 168 IT8XXX2_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH 169 IT8XXX2_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH 170 IT8XXX2_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH 171 IT8XXX2_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-parent = <&intc>; 173 #gpio-cells = <2>; 174 }; 175 176 gpiob: gpio@f01602 { 177 compatible = "ite,it8xxx2-gpio"; 178 reg = <0x00f01602 1 /* GPDR (set) */ 179 0x00f01618 8 /* GPCR */ 180 0x00f01662 1 /* GPDMR (get) */ 181 0x00f01672 1>; /* GPOTR */ 182 ngpios = <8>; 183 gpio-controller; 184 interrupts = <IT8XXX2_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH 185 IT8XXX2_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH 186 IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH 187 IT8XXX2_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH 188 IT8XXX2_IRQ_WU94 IRQ_TYPE_LEVEL_HIGH 189 IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH 190 IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH 191 IT8XXX2_IRQ_WU106 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-parent = <&intc>; 193 wakeup-source; /* WUI53 */ 194 #gpio-cells = <2>; 195 }; 196 197 gpioc: gpio@f01603 { 198 compatible = "ite,it8xxx2-gpio"; 199 reg = <0x00f01603 1 /* GPDR (set) */ 200 0x00f01620 8 /* GPCR */ 201 0x00f01663 1 /* GPDMR (get) */ 202 0x00f01673 1>; /* GPOTR */ 203 ngpios = <8>; 204 gpio-controller; 205 interrupts = <IT8XXX2_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH 206 IT8XXX2_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH 207 IT8XXX2_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH 208 IT8XXX2_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH 209 IT8XXX2_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH 210 IT8XXX2_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH 211 IT8XXX2_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH 212 IT8XXX2_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-parent = <&intc>; 214 #gpio-cells = <2>; 215 }; 216 217 gpiod: gpio@f01604 { 218 compatible = "ite,it8xxx2-gpio"; 219 reg = <0x00f01604 1 /* GPDR (set) */ 220 0x00f01628 8 /* GPCR */ 221 0x00f01664 1 /* GPDMR (get) */ 222 0x00f01674 1>; /* GPOTR */ 223 ngpios = <8>; 224 gpio-controller; 225 interrupts = <IT8XXX2_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH 226 IT8XXX2_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH 227 IT8XXX2_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH 228 IT8XXX2_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH 229 IT8XXX2_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH 230 IT8XXX2_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH 231 IT8XXX2_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH 232 IT8XXX2_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-parent = <&intc>; 234 #gpio-cells = <2>; 235 }; 236 237 gpioe: gpio@f01605 { 238 compatible = "ite,it8xxx2-gpio"; 239 reg = <0x00f01605 1 /* GPDR (set) */ 240 0x00f01630 8 /* GPCR */ 241 0x00f01665 1 /* GPDMR (get) */ 242 0x00f01675 1>; /* GPOTR */ 243 ngpios = <8>; 244 gpio-controller; 245 interrupts = <IT8XXX2_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH 246 IT8XXX2_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH 247 IT8XXX2_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH 248 IT8XXX2_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH 249 IT8XXX2_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH 250 IT8XXX2_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH 251 IT8XXX2_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH 252 IT8XXX2_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-parent = <&intc>; 254 #gpio-cells = <2>; 255 }; 256 257 gpiof: gpio@f01606 { 258 compatible = "ite,it8xxx2-gpio"; 259 reg = <0x00f01606 1 /* GPDR (set) */ 260 0x00f01638 8 /* GPCR */ 261 0x00f01666 1 /* GPDMR (get) */ 262 0x00f01676 1>; /* GPOTR */ 263 ngpios = <8>; 264 gpio-controller; 265 interrupts = <IT8XXX2_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH 266 IT8XXX2_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH 267 IT8XXX2_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH 268 IT8XXX2_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH 269 IT8XXX2_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH 270 IT8XXX2_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH 271 IT8XXX2_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH 272 IT8XXX2_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-parent = <&intc>; 274 #gpio-cells = <2>; 275 }; 276 277 gpiog: gpio@f01607 { 278 compatible = "ite,it8xxx2-gpio"; 279 reg = <0x00f01607 1 /* GPDR (set) */ 280 0x00f01640 8 /* GPCR */ 281 0x00f01667 1 /* GPDMR (get) */ 282 0x00f01677 1>; /* GPOTR */ 283 ngpios = <8>; 284 gpio-controller; 285 interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH 286 IT8XXX2_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH 287 IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH 288 IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH 289 IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH 290 IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH 291 IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH 292 IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-parent = <&intc>; 294 #gpio-cells = <2>; 295 }; 296 297 gpioh: gpio@f01608 { 298 compatible = "ite,it8xxx2-gpio"; 299 reg = <0x00f01608 1 /* GPDR (set) */ 300 0x00f01648 8 /* GPCR */ 301 0x00f01668 1 /* GPDMR (get) */ 302 0x00f01678 1>; /* GPOTR */ 303 ngpios = <8>; 304 gpio-controller; 305 interrupts = <IT8XXX2_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH 306 IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH 307 IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH 308 IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH 309 IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH 310 IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH 311 IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH 312 0 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-parent = <&intc>; 314 wakeup-source; /* WUI17 */ 315 #gpio-cells = <2>; 316 }; 317 318 gpioi: gpio@f01609 { 319 compatible = "ite,it8xxx2-gpio"; 320 reg = <0x00f01609 1 /* GPDR (set) */ 321 0x00f01650 8 /* GPCR */ 322 0x00f01669 1 /* GPDMR (get) */ 323 0x00f01679 1>; /* GPOTR */ 324 ngpios = <8>; 325 gpio-controller; 326 interrupts = <IT8XXX2_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH 327 IT8XXX2_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH 328 IT8XXX2_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH 329 IT8XXX2_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH 330 IT8XXX2_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH 331 IT8XXX2_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH 332 IT8XXX2_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH 333 IT8XXX2_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>; 334 interrupt-parent = <&intc>; 335 #gpio-cells = <2>; 336 }; 337 338 gpioj: gpio@f0160a { 339 compatible = "ite,it8xxx2-gpio"; 340 reg = <0x00f0160a 1 /* GPDR (set) */ 341 0x00f01658 8 /* GPCR */ 342 0x00f0166a 1 /* GPDMR (get) */ 343 0x00f0167a 1>; /* GPOTR */ 344 ngpios = <8>; 345 gpio-controller; 346 interrupts = <IT8XXX2_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH 347 IT8XXX2_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH 348 IT8XXX2_IRQ_WU130 IRQ_TYPE_LEVEL_HIGH 349 IT8XXX2_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH 350 IT8XXX2_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH 351 IT8XXX2_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH 352 IT8XXX2_IRQ_WU134 IRQ_TYPE_LEVEL_HIGH 353 IT8XXX2_IRQ_WU135 IRQ_TYPE_LEVEL_HIGH>; 354 interrupt-parent = <&intc>; 355 #gpio-cells = <2>; 356 }; 357 358 gpiok: gpio@f0160b { 359 compatible = "ite,it8xxx2-gpio"; 360 reg = <0x00f0160b 1 /* GPDR (set) */ 361 0x00f01690 8 /* GPCR */ 362 0x00f0166b 1 /* GPDMR (get) */ 363 0x00f0167b 1>; /* GPOTR */ 364 ngpios = <8>; 365 gpio-controller; 366 interrupts = <IT8XXX2_IRQ_WU50 IRQ_TYPE_LEVEL_HIGH 367 IT8XXX2_IRQ_WU51 IRQ_TYPE_LEVEL_HIGH 368 IT8XXX2_IRQ_WU52 IRQ_TYPE_LEVEL_HIGH 369 IT8XXX2_IRQ_WU53 IRQ_TYPE_LEVEL_HIGH 370 IT8XXX2_IRQ_WU54 IRQ_TYPE_LEVEL_HIGH 371 IT8XXX2_IRQ_WU55 IRQ_TYPE_LEVEL_HIGH 372 IT8XXX2_IRQ_WU56 IRQ_TYPE_LEVEL_HIGH 373 IT8XXX2_IRQ_WU57 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-parent = <&intc>; 375 #gpio-cells = <2>; 376 }; 377 378 gpiol: gpio@f0160c { 379 compatible = "ite,it8xxx2-gpio"; 380 reg = <0x00f0160c 1 /* GPDR (set) */ 381 0x00f01698 8 /* GPCR */ 382 0x00f0166c 1 /* GPDMR (get) */ 383 0x00f0167c 1>; /* GPOTR */ 384 ngpios = <8>; 385 gpio-controller; 386 interrupts = <IT8XXX2_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH 387 IT8XXX2_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH 388 IT8XXX2_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH 389 IT8XXX2_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH 390 IT8XXX2_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH 391 IT8XXX2_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH 392 IT8XXX2_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH 393 IT8XXX2_IRQ_WU143 IRQ_TYPE_LEVEL_HIGH>; 394 interrupt-parent = <&intc>; 395 #gpio-cells = <2>; 396 }; 397 398 gpiom: gpio@f0160d { 399 compatible = "ite,it8xxx2-gpio"; 400 reg = <0x00f0160d 1 /* GPDR (set) */ 401 0x00f016a0 8 /* GPCR */ 402 0x00f0166d 1 /* GPDMR (get) */ 403 0x00f0167d 1>; /* GPOTR */ 404 ngpios = <7>; 405 gpio-controller; 406 interrupts = <IT8XXX2_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH 407 IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH 408 IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH 409 IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH 410 IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH 411 IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH 412 IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH 413 0 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-parent = <&intc>; 415 #gpio-cells = <2>; 416 }; 417 418 espi0: espi@f03100 { 419 compatible = "ite,it8xxx2-espi"; 420 reg = <0x00f03100 0xd8 /* eSPI slave */ 421 0x00f03200 0x9a /* eSPI VW */ 422 0x00f03300 0xd0 /* eSPI Queue 0 */ 423 0x00f03400 0xc0 /* eSPI Queue 1 */ 424 0x00f01200 6 /* EC2I bridge */ 425 0x00f01300 11 /* Host KBC */ 426 0x00f01500 0x100 /* Host PMC */ 427 0x00f01000 0xd1>; /* SMFI */ 428 interrupts = <IT8XXX2_IRQ_ESPI IRQ_TYPE_LEVEL_HIGH 429 IT8XXX2_IRQ_ESPI_VW IRQ_TYPE_LEVEL_HIGH 430 IT8XXX2_IRQ_KBC_IBF IRQ_TYPE_LEVEL_HIGH 431 IT8XXX2_IRQ_KBC_OBE IRQ_TYPE_LEVEL_HIGH 432 IT8XXX2_IRQ_PMC1_IBF IRQ_TYPE_LEVEL_HIGH 433 IT8XXX2_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH 434 IT8XXX2_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH 435 IT8XXX2_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH>; 436 interrupt-parent = <&intc>; 437 wucctrl = <&wuc_wu42>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 status = "disabled"; 441 }; 442 443 spi0: spi@f02600 { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 compatible = "ite,it8xxx2-sspi"; 447 reg = <0x00f02600 0x40>; 448 interrupt-parent = <&intc>; 449 interrupts = <37 IRQ_TYPE_EDGE_RISING>; 450 clock-frequency = <115200>; 451 }; 452 spi1: spi@f02640 { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 compatible = "ite,it8xxx2-sspi"; 456 reg = <0x00f02640 0x40>; 457 interrupts = <37 IRQ_TYPE_EDGE_RISING>; 458 interrupt-parent = <&intc>; 459 status = "okay"; 460 }; 461 shi0: shi@f03a00 { 462 compatible = "ite,it8xxx2-shi"; 463 reg = <0x00f03a00 0x30>; 464 interrupts = <171 0>; 465 interrupt-parent = <&intc>; 466 status = "disabled"; 467 buffer-rx-size = <256>; 468 buffer-tx-size = <256>; 469 }; 470 adc0: adc@f01900 { 471 compatible = "ite,it8xxx2-adc"; 472 reg = <0xf01900 0x45>; 473 interrupts = <8 IRQ_TYPE_NONE>; 474 interrupt-parent = <&intc>; 475 status = "disabled"; 476 #io-channel-cells = <1>; 477 }; 478 vcmp0: vcmp@f01946 { 479 compatible = "ite,it8xxx2-vcmp"; 480 reg = <0xf01946 0x01 /* VCMP0CTL */ 481 0xf01977 0x01 /* VCMP0CSELM */ 482 0xf01937 0x01 /* VCMPSCP */ 483 0xf01947 0x01 /* VCMP0THRDATM */ 484 0xf01948 0x01 /* VCMP0THRDATL */ 485 0xf01945 0x01 /* VCMPSTS */ 486 0xf0196d 0x01>; /* VCMPSTS2 */ 487 interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>; 488 interrupt-parent = <&intc>; 489 vcmp-ch = <VCMP_CHANNEL_0>; 490 status = "disabled"; 491 }; 492 vcmp1: vcmp@f01949 { 493 compatible = "ite,it8xxx2-vcmp"; 494 reg = <0xf01949 0x01 /* VCMP1CTL */ 495 0xf01978 0x01 /* VCMP1CSELM */ 496 0xf01937 0x01 /* VCMPSCP */ 497 0xf0194a 0x01 /* VCMP1THRDATM */ 498 0xf0194b 0x01 /* VCMP1THRDATL */ 499 0xf01945 0x01 /* VCMPSTS */ 500 0xf0196d 0x01>; /* VCMPSTS2 */ 501 interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-parent = <&intc>; 503 vcmp-ch = <VCMP_CHANNEL_1>; 504 status = "disabled"; 505 }; 506 vcmp2: vcmp@f0194c { 507 compatible = "ite,it8xxx2-vcmp"; 508 reg = <0xf0194c 0x01 /* VCMP2CTL */ 509 0xf01979 0x01 /* VCMP2CSELM */ 510 0xf01937 0x01 /* VCMPSCP */ 511 0xf0194d 0x01 /* VCMP2THRDATM */ 512 0xf0194e 0x01 /* VCMP2THRDATL */ 513 0xf01945 0x01 /* VCMPSTS */ 514 0xf0196d 0x01>; /* VCMPSTS2 */ 515 interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-parent = <&intc>; 517 vcmp-ch = <VCMP_CHANNEL_2>; 518 status = "disabled"; 519 }; 520 vcmp3: vcmp@f0196e { 521 compatible = "ite,it8xxx2-vcmp"; 522 reg = <0xf0196e 0x01 /* VCMP3CTL */ 523 0xf0197a 0x01 /* VCMP3CSELM */ 524 0xf01937 0x01 /* VCMPSCP */ 525 0xf0196f 0x01 /* VCMP3THRDATM */ 526 0xf01970 0x01 /* VCMP3THRDATL */ 527 0xf01945 0x01 /* VCMPSTS */ 528 0xf0196d 0x01>; /* VCMPSTS2 */ 529 interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-parent = <&intc>; 531 vcmp-ch = <VCMP_CHANNEL_3>; 532 status = "disabled"; 533 }; 534 vcmp4: vcmp@f01971 { 535 compatible = "ite,it8xxx2-vcmp"; 536 reg = <0xf01971 0x01 /* VCMP4CTL */ 537 0xf0197b 0x01 /* VCMP4CSELM */ 538 0xf01937 0x01 /* VCMPSCP */ 539 0xf01972 0x01 /* VCMP4THRDATM */ 540 0xf01973 0x01 /* VCMP4THRDATL */ 541 0xf01945 0x01 /* VCMPSTS */ 542 0xf0196d 0x01>; /* VCMPSTS2 */ 543 interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>; 544 interrupt-parent = <&intc>; 545 vcmp-ch = <VCMP_CHANNEL_4>; 546 status = "disabled"; 547 }; 548 vcmp5: vcmp@f01974 { 549 compatible = "ite,it8xxx2-vcmp"; 550 reg = <0xf01974 0x01 /* VCMP5CTL */ 551 0xf0197c 0x01 /* VCMP5CSELM */ 552 0xf01937 0x01 /* VCMPSCP */ 553 0xf01975 0x01 /* VCMP5THRDATM */ 554 0xf01976 0x01 /* VCMP5THRDATL */ 555 0xf01945 0x01 /* VCMPSTS */ 556 0xf0196d 0x01>; /* VCMPSTS2 */ 557 interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>; 558 interrupt-parent = <&intc>; 559 vcmp-ch = <VCMP_CHANNEL_5>; 560 status = "disabled"; 561 }; 562 563 ecpm: clock-controller@f01e00 { 564 compatible = "ite,it8xxx2-ecpm"; 565 reg = <0x00f01e00 0x11>; 566 reg-names = "ecpm"; 567 }; 568 prs: pwmprs@f01800 { 569 compatible = "ite,it8xxx2-pwmprs"; 570 reg = <0x00f01800 1>; 571 }; 572 pwm0: pwm@f01802 { 573 compatible = "ite,it8xxx2-pwm"; 574 reg = <0x00f01802 1 /* DCR */ 575 0x00f0180c 1 /* PCSSG */ 576 0x00f0180f 1 /* PCSG */ 577 0x00f0180a 1>; /* PWMPOL */ 578 channel = <PWM_CHANNEL_0>; 579 status = "disabled"; 580 pwmctrl = <&prs>; 581 #pwm-cells = <3>; 582 }; 583 pwm1: pwm@f01803 { 584 compatible = "ite,it8xxx2-pwm"; 585 reg = <0x00f01803 1 /* DCR */ 586 0x00f0180c 1 /* PCSSG */ 587 0x00f0180f 1 /* PCSG */ 588 0x00f0180a 1>; /* PWMPOL */ 589 channel = <PWM_CHANNEL_1>; 590 status = "disabled"; 591 pwmctrl = <&prs>; 592 #pwm-cells = <3>; 593 }; 594 pwm2: pwm@f01804 { 595 compatible = "ite,it8xxx2-pwm"; 596 reg = <0x00f01804 1 /* DCR */ 597 0x00f0180c 1 /* PCSSG */ 598 0x00f0180f 1 /* PCSG */ 599 0x00f0180a 1>; /* PWMPOL */ 600 channel = <PWM_CHANNEL_2>; 601 status = "disabled"; 602 pwmctrl = <&prs>; 603 #pwm-cells = <3>; 604 }; 605 pwm3: pwm@f01805 { 606 compatible = "ite,it8xxx2-pwm"; 607 reg = <0x00f01805 1 /* DCR */ 608 0x00f0180c 1 /* PCSSG */ 609 0x00f0180f 1 /* PCSG */ 610 0x00f0180a 1>; /* PWMPOL */ 611 channel = <PWM_CHANNEL_3>; 612 status = "disabled"; 613 pwmctrl = <&prs>; 614 #pwm-cells = <3>; 615 }; 616 pwm4: pwm@f01806 { 617 compatible = "ite,it8xxx2-pwm"; 618 reg = <0x00f01806 1 /* DCR */ 619 0x00f0180d 1 /* PCSSG */ 620 0x00f0180f 1 /* PCSG */ 621 0x00f0180a 1>; /* PWMPOL */ 622 channel = <PWM_CHANNEL_4>; 623 status = "disabled"; 624 pwmctrl = <&prs>; 625 #pwm-cells = <3>; 626 }; 627 pwm5: pwm@f01807 { 628 compatible = "ite,it8xxx2-pwm"; 629 reg = <0x00f01807 1 /* DCR */ 630 0x00f0180d 1 /* PCSSG */ 631 0x00f0180f 1 /* PCSG */ 632 0x00f0180a 1>; /* PWMPOL */ 633 channel = <PWM_CHANNEL_5>; 634 status = "disabled"; 635 pwmctrl = <&prs>; 636 #pwm-cells = <3>; 637 }; 638 pwm6: pwm@f01808 { 639 compatible = "ite,it8xxx2-pwm"; 640 reg = <0x00f01808 1 /* DCR */ 641 0x00f0180d 1 /* PCSSG */ 642 0x00f0180f 1 /* PCSG */ 643 0x00f0180a 1>; /* PWMPOL */ 644 channel = <PWM_CHANNEL_6>; 645 status = "disabled"; 646 pwmctrl = <&prs>; 647 #pwm-cells = <3>; 648 }; 649 pwm7: pwm@f01809 { 650 compatible = "ite,it8xxx2-pwm"; 651 reg = <0x00f01809 1 /* DCR */ 652 0x00f0180d 1 /* PCSSG */ 653 0x00f0180f 1 /* PCSG */ 654 0x00f0180a 1>; /* PWMPOL */ 655 channel = <PWM_CHANNEL_7>; 656 status = "disabled"; 657 pwmctrl = <&prs>; 658 #pwm-cells = <3>; 659 }; 660 tach0: tach@f0181e { 661 compatible = "ite,it8xxx2-tach"; 662 reg = <0x00f0181e 1 /* F1TLRR */ 663 0x00f0181f 1 /* F1TMRR */ 664 0x00f01848 1>; /* TSWCTLR */ 665 dvs-bit = <BIT(3)>; 666 chsel-bit = <BIT(2)>; 667 status = "disabled"; 668 }; 669 tach1: tach@f01820 { 670 compatible = "ite,it8xxx2-tach"; 671 reg = <0x00f01820 1 /* F2TLRR */ 672 0x00f01821 1 /* F2TMRR */ 673 0x00f01848 1>; /* TSWCTLR */ 674 dvs-bit = <BIT(1)>; 675 chsel-bit = <BIT(0)>; 676 status = "disabled"; 677 }; 678 679 gctrl: general-control@f02000 { 680 compatible = "ite,it8xxx2-gctrl"; 681 reg = <0x00f02000 0x100>; 682 }; 683 684 peci0: peci@f02c00 { 685 compatible = "ite,it8xxx2-peci"; 686 reg = <0x00f02c00 15>; 687 #address-cells=<1>; 688 #size-cells = <0>; 689 interrupt-parent = <&intc>; 690 interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; 691 status = "disabled"; 692 }; 693 694 kbd: kbd@f01d00 { 695 compatible = "ite,it8xxx2-kbd"; 696 reg = <0x00f01d00 0x29>; 697 interrupt-parent = <&intc>; 698 interrupts = <IT8XXX2_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH>; 699 status = "disabled"; 700 wucctrl = <&wuc_wu30 /* KSI[0] */ 701 &wuc_wu31 /* KSI[1] */ 702 &wuc_wu32 /* KSI[2] */ 703 &wuc_wu33 /* KSI[3] */ 704 &wuc_wu34 /* KSI[4] */ 705 &wuc_wu35 /* KSI[5] */ 706 &wuc_wu36 /* KSI[6] */ 707 &wuc_wu37>; /* KSI[7] */ 708 kso16-gpios = <&gpioc 3 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; 709 kso17-gpios = <&gpioc 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; 710 }; 711 712 usbpd0: usbpd@f03700 { 713 compatible = "ite,it8xxx2-usbpd"; 714 reg = <0x00f03700 0x100>; 715 status = "disabled"; 716 }; 717 718 usbpd1: usbpd@f03800 { 719 compatible = "ite,it8xxx2-usbpd"; 720 reg = <0x00f03800 0x100>; 721 status = "disabled"; 722 }; 723 }; 724}; 725
