1/*
2 * Copyright (c) 2024-2025 Silicon Laboratories Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h>
9
10/ {
11	chosen {
12		zephyr,entropy = &rng0;
13		zephyr,flash = &flash0;
14		zephyr,flash-controller = &flashctrl0;
15	};
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "arm,cortex-m4f";
23			reg = <0>;
24		};
25	};
26
27	sram0: memory@0 {
28		compatible = "mmio-sram";
29		reg = <0x00000000 DT_SIZE_K(191)>;
30	};
31
32	bt_hci0: bt_hci {
33		compatible = "silabs,siwx91x-bt-hci";
34		status = "disabled";
35	};
36
37	wifi0: wifi {
38		compatible = "silabs,siwx91x-wifi";
39		status = "disabled";
40	};
41
42	soc {
43		clock0: clock@46000000 {
44			compatible = "silabs,siwx91x-clock";
45			reg = <0x46000000 0x100>,
46			      <0x46000800 0x100>,
47			      <0x24041400 0x100>,
48			      <0x24048000 0x200>;
49			#clock-cells = <1>;
50			status = "okay";
51		};
52
53		pinctrl0: pinctrl@46130000 {
54			compatible = "silabs,siwx91x-pinctrl";
55			reg = <0x46130000 0x1000>;
56		};
57
58		flashctrl0: flash-controller@12000000 {
59			compatible = "silabs,siwx91x-flash-controller";
60			reg = <0x12000000 0x200>;
61			#address-cells = <1>;
62			#size-cells = <1>;
63
64			flash0: flash@8202000 {
65				compatible = "soc-nv-flash";
66				write-block-size = <1>;
67				erase-block-size = <4096>;
68			};
69		};
70
71		ulpuart: uart@24041800 {
72			compatible = "ns16550";
73			reg = <0x24041800 0x1000>;
74			interrupts = <12 0>;
75			reg-shift = <2>;
76			clocks = <&clock0 SIWX91X_CLK_ULP_UART>;
77			current-speed = <115200>;
78			status = "disabled";
79		};
80
81		uart0: uart@44000000 {
82			compatible = "ns16550";
83			reg = <0x44000000 0x1000>;
84			interrupts = <38 0>;
85			reg-shift = <2>;
86			clocks = <&clock0 SIWX91X_CLK_UART0>;
87			current-speed = <115200>;
88			status = "disabled";
89		};
90
91		uart1: uart@45020000 {
92			compatible = "ns16550";
93			reg = <0x45020000 0x1000>;
94			interrupts = <39 0>;
95			reg-shift = <2>;
96			clocks = <&clock0 SIWX91X_CLK_UART1>;
97			current-speed = <115200>;
98			status = "disabled";
99		};
100
101		rng0: rng@45090000 {
102			compatible = "silabs,siwx91x-rng";
103			reg = <0x45090000 0x8>;
104		};
105
106		egpio0: egpio@46130000 {
107			compatible = "silabs,siwx91x-gpio";
108			reg = <0x46130000 0x1260>;
109			interrupts = <52 0>, <53 0>, <54 0>, <55 0>,
110				     <56 0>, <57 0>, <58 0>, <59 0>;
111			interrupt-names = "PIN0", "PIN1", "PIN2", "PIN3",
112					  "PIN4", "PIN5", "PIN6", "PIN7";
113
114			#address-cells = <1>;
115			#size-cells = <0>;
116
117			gpioa: gpio@0 {
118				compatible = "silabs,siwx91x-gpio-port";
119				reg = <0>;
120				gpio-controller;
121				#gpio-cells = <2>;
122				ngpios = <16>;
123				gpio-reserved-ranges = <0 6>;
124				silabs,pads = [
125					ff ff ff ff  ff ff 01 02  03 04 05 06  07 ff ff 08
126				];
127				status = "okay";
128			};
129
130			gpiob: gpio@1 {
131				compatible = "silabs,siwx91x-gpio-port";
132				reg = <1>;
133				gpio-controller;
134				#gpio-cells = <2>;
135				ngpios = <16>;
136				silabs,pads = [
137					ff ff ff ff  ff ff ff ff  ff 00 00 00  00 00 00 09
138				];
139				status = "okay";
140			};
141
142			gpioc: gpio@2 {
143				compatible = "silabs,siwx91x-gpio-port";
144				reg = <2>;
145				gpio-controller;
146				#gpio-cells = <2>;
147				ngpios = <16>;
148				silabs,pads = [
149					09 09 09 ff  ff ff ff ff  ff ff ff ff  ff ff 0a 0b
150				];
151				status = "okay";
152			};
153
154			gpiod: gpio@3 {
155				compatible = "silabs,siwx91x-gpio-port";
156				reg = <3>;
157				gpio-controller;
158				#gpio-cells = <2>;
159				ngpios = <10>;
160				silabs,pads = [
161					0c 0d 0e 0f  10 11 12 13  14 15 ff ff  ff ff ff ff
162				];
163				status = "okay";
164			};
165		};
166
167		egpio1: egpio@2404c000 {
168			compatible = "silabs,siwx91x-gpio";
169			reg = <0x2404C000 0x1260>;
170			interrupts = <18 0>;
171			interrupt-names = "ULP";
172			silabs,ulp;
173
174			#address-cells = <1>;
175			#size-cells = <0>;
176
177			ulpgpio: ulpgpio@0 {
178				compatible = "silabs,siwx91x-gpio-port";
179				reg = <0>;
180				gpio-controller;
181				#gpio-cells = <2>;
182				ngpios = <12>;
183				gpio-reserved-ranges = <3 1>;
184				silabs,pads = [
185					16 17 18 19  1a 1b 1c 1d  1e 1f 20 21  ff ff ff ff
186				];
187				status = "okay";
188			};
189		};
190
191		uulpgpio: uulpgpio@24048600 {
192			compatible = "silabs,siwx91x-gpio-uulp";
193			reg = <0x24048600 0x30>, <0x12080000 0x18>;
194			reg-names = "ret", "int";
195			interrupts = <21 0>;
196			interrupt-names = "UULP";
197
198			gpio-controller;
199			#gpio-cells = <2>;
200			ngpios = <5>;
201			status = "okay";
202		};
203
204		ulpi2c: i2c@24040000 {
205			compatible = "snps,designware-i2c";
206			#address-cells = <1>;
207			#size-cells = <0>;
208			reg = <0x24040000 0x100>;
209			interrupts = <13 0>;
210			interrupt-names = "i2c2";
211			clocks = <&clock0 SIWX91X_CLK_ULP_I2C>;
212			status = "disabled";
213		};
214
215		i2c0: i2c@44010000 {
216			compatible = "snps,designware-i2c";
217			#address-cells = <1>;
218			#size-cells = <0>;
219			reg = <0x44010000 0x100>;
220			interrupts = <42 0>;
221			interrupt-names = "i2c0";
222			clocks = <&clock0 SIWX91X_CLK_I2C0>;
223			status = "disabled";
224		};
225
226		i2c1: i2c@47040000 {
227			compatible = "snps,designware-i2c";
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0x47040000 0x100>;
231			interrupts = <61 0>;
232			interrupt-names = "i2c1";
233			clocks = <&clock0 SIWX91X_CLK_I2C1>;
234			status = "disabled";
235		};
236
237		dma0: dma@44030000 {
238			compatible = "silabs,siwx91x-dma";
239			#address-cells = <1>;
240			#size-cells = <0>;
241			reg = <0x44030000 0x82C>;
242			interrupts = <33 0>;
243			interrupt-names = "dma0";
244			clocks = <&clock0 SIWX91X_CLK_DMA0>;
245			silabs,sram-desc-addr = <0x2fc00>;
246			#dma-cells = < 1>;
247			dma-channels = <32>;
248			status = "disabled";
249		};
250
251		ulpdma: dma@24078000 {
252			compatible = "silabs,siwx91x-dma";
253			#address-cells = <1>;
254			#size-cells = <0>;
255			reg = <0x24078000 0x82C>;
256			interrupts = <10 0>;
257			interrupt-names = "ulpdma";
258			clocks = <&clock0 SIWX91X_CLK_ULP_DMA>;
259			silabs,sram-desc-addr = <0x24061c00>;
260			#dma-cells = < 1>;
261			dma-channels = <12>;
262			status = "disabled";
263		};
264
265		pwm: pwm@47070000 {
266			compatible = "silabs,siwx91x-pwm";
267			#address-cells = <1>;
268			#size-cells = <0>;
269			reg = <0x47070000 0x14C>;
270			interrupts = <48 0>;
271			interrupt-names = "pwm";
272			clocks = <&clock0 SIWX91X_CLK_PWM>;
273			#pwm-cells = <2>;
274			silabs,ch_prescaler = <64 64 64 64>;
275			status = "disabled";
276		};
277
278		watchdog: wdt@24048300 {
279			compatible = "silabs,siwx91x-wdt";
280			#address-cells = <1>;
281			#size-cells = <0>;
282			reg = <0x24048300 0x1C>;
283			interrupts = <20 0>;
284			interrupt-names = "watchdog";
285			clocks = <&clock0 SIWX91X_CLK_WATCHDOG>;
286			status = "disabled";
287		};
288	};
289};
290
291&nvic {
292	arm,num-irq-priority-bits = <6>;
293};
294