1 /*
2 * Copyright (c) 2023 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file udc_stm32.c
9 * @brief STM32 USB device controller (UDC) driver
10 */
11
12 #include <soc.h>
13 #include <stm32_ll_bus.h>
14 #include <stm32_ll_pwr.h>
15 #include <stm32_ll_rcc.h>
16 #include <stm32_ll_system.h>
17 #include <string.h>
18 #include <zephyr/irq.h>
19 #include <zephyr/drivers/gpio.h>
20 #include <zephyr/drivers/pinctrl.h>
21 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
22 #include <zephyr/sys/util.h>
23
24 #include "udc_common.h"
25
26 #include "stm32_hsem.h"
27
28 #include <zephyr/logging/log.h>
29 LOG_MODULE_REGISTER(udc_stm32, CONFIG_UDC_DRIVER_LOG_LEVEL);
30
31 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
32 #define DT_DRV_COMPAT st_stm32_otghs
33 #define UDC_STM32_IRQ_NAME otghs
34 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
35 #define DT_DRV_COMPAT st_stm32_otgfs
36 #define UDC_STM32_IRQ_NAME otgfs
37 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
38 #define DT_DRV_COMPAT st_stm32_usb
39 #define UDC_STM32_IRQ_NAME usb
40 #endif
41
42 #define UDC_STM32_IRQ DT_INST_IRQ_BY_NAME(0, UDC_STM32_IRQ_NAME, irq)
43 #define UDC_STM32_IRQ_PRI DT_INST_IRQ_BY_NAME(0, UDC_STM32_IRQ_NAME, priority)
44
45 struct udc_stm32_data {
46 PCD_HandleTypeDef pcd;
47 const struct device *dev;
48 uint32_t irq;
49 uint32_t occupied_mem;
50 void (*pcd_prepare)(const struct device *dev);
51 int (*clk_enable)(void);
52 int (*clk_disable)(void);
53 };
54
55 struct udc_stm32_config {
56 uint32_t num_endpoints;
57 uint32_t pma_offset;
58 uint32_t dram_size;
59 uint16_t ep0_mps;
60 uint16_t ep_mps;
61 };
62
udc_stm32_lock(const struct device * dev)63 static int udc_stm32_lock(const struct device *dev)
64 {
65 return udc_lock_internal(dev, K_FOREVER);
66 }
67
udc_stm32_unlock(const struct device * dev)68 static int udc_stm32_unlock(const struct device *dev)
69 {
70 return udc_unlock_internal(dev);
71 }
72
73 #define hpcd2data(hpcd) CONTAINER_OF(hpcd, struct udc_stm32_data, pcd);
74
HAL_PCD_ResetCallback(PCD_HandleTypeDef * hpcd)75 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
76 {
77 struct udc_stm32_data *priv = hpcd2data(hpcd);
78 const struct device *dev = priv->dev;
79 const struct udc_stm32_config *cfg = dev->config;
80 struct udc_ep_config *ep;
81
82 /* Re-Enable control endpoints */
83 ep = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
84 if (ep && ep->stat.enabled) {
85 HAL_PCD_EP_Open(&priv->pcd, USB_CONTROL_EP_OUT, cfg->ep0_mps,
86 EP_TYPE_CTRL);
87 }
88
89 ep = udc_get_ep_cfg(dev, USB_CONTROL_EP_IN);
90 if (ep && ep->stat.enabled) {
91 HAL_PCD_EP_Open(&priv->pcd, USB_CONTROL_EP_IN, cfg->ep0_mps,
92 EP_TYPE_CTRL);
93 }
94
95 udc_submit_event(priv->dev, UDC_EVT_RESET, 0);
96 }
97
HAL_PCD_ConnectCallback(PCD_HandleTypeDef * hpcd)98 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
99 {
100 struct udc_stm32_data *priv = hpcd2data(hpcd);
101
102 udc_submit_event(priv->dev, UDC_EVT_VBUS_READY, 0);
103 }
104
HAL_PCD_DisconnectCallback(PCD_HandleTypeDef * hpcd)105 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
106 {
107 struct udc_stm32_data *priv = hpcd2data(hpcd);
108
109 udc_submit_event(priv->dev, UDC_EVT_VBUS_REMOVED, 0);
110 }
111
HAL_PCD_SuspendCallback(PCD_HandleTypeDef * hpcd)112 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
113 {
114 struct udc_stm32_data *priv = hpcd2data(hpcd);
115
116 udc_set_suspended(priv->dev, true);
117 udc_submit_event(priv->dev, UDC_EVT_SUSPEND, 0);
118 }
119
HAL_PCD_ResumeCallback(PCD_HandleTypeDef * hpcd)120 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
121 {
122 struct udc_stm32_data *priv = hpcd2data(hpcd);
123
124 udc_set_suspended(priv->dev, false);
125 udc_submit_event(priv->dev, UDC_EVT_RESUME, 0);
126 }
127
usbd_ctrl_feed_dout(const struct device * dev,const size_t length)128 static int usbd_ctrl_feed_dout(const struct device *dev, const size_t length)
129 {
130 struct udc_stm32_data *priv = udc_get_private(dev);
131 struct udc_ep_config *cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
132 struct net_buf *buf;
133
134 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, length);
135 if (buf == NULL) {
136 return -ENOMEM;
137 }
138
139 net_buf_put(&cfg->fifo, buf);
140
141 HAL_PCD_EP_Receive(&priv->pcd, cfg->addr, buf->data, buf->size);
142
143 return 0;
144 }
145
HAL_PCD_SetupStageCallback(PCD_HandleTypeDef * hpcd)146 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
147 {
148 struct udc_stm32_data *priv = hpcd2data(hpcd);
149 struct usb_setup_packet *setup = (void *)priv->pcd.Setup;
150 const struct device *dev = priv->dev;
151 struct net_buf *buf;
152 int err;
153
154 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT,
155 sizeof(struct usb_setup_packet));
156 if (buf == NULL) {
157 LOG_ERR("Failed to allocate for setup");
158 return;
159 }
160
161 udc_ep_buf_set_setup(buf);
162 memcpy(buf->data, setup, 8);
163 net_buf_add(buf, 8);
164
165 udc_ctrl_update_stage(dev, buf);
166
167 if (!buf->len) {
168 return;
169 }
170
171 if (setup->bRequest == USB_SREQ_SET_ADDRESS) {
172 /* HAL requires we set the address before submitting status */
173 HAL_PCD_SetAddress(&priv->pcd, setup->wValue);
174 }
175
176 if (udc_ctrl_stage_is_data_out(dev)) {
177 /* Allocate and feed buffer for data OUT stage */
178 err = usbd_ctrl_feed_dout(dev, udc_data_stage_length(buf));
179 if (err == -ENOMEM) {
180 udc_submit_ep_event(dev, buf, err);
181 }
182 } else if (udc_ctrl_stage_is_data_in(dev)) {
183 udc_ctrl_submit_s_in_status(dev);
184 } else {
185 udc_ctrl_submit_s_status(dev);
186 }
187 }
188
HAL_PCD_SOFCallback(PCD_HandleTypeDef * hpcd)189 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
190 {
191 struct udc_stm32_data *priv = hpcd2data(hpcd);
192
193 udc_submit_event(priv->dev, UDC_EVT_SOF, 0);
194 }
195
udc_stm32_tx(const struct device * dev,uint8_t ep,struct net_buf * buf)196 static int udc_stm32_tx(const struct device *dev, uint8_t ep,
197 struct net_buf *buf)
198 {
199 struct udc_stm32_data *priv = udc_get_private(dev);
200 const struct udc_stm32_config *cfg = dev->config;
201 uint8_t *data; uint32_t len;
202 HAL_StatusTypeDef status;
203
204 LOG_DBG("TX ep 0x%02x len %u", ep, buf->len);
205
206 if (udc_ep_is_busy(dev, ep)) {
207 return 0;
208 }
209
210 data = buf->data;
211 len = buf->len;
212
213 if (ep == USB_CONTROL_EP_IN) {
214 len = MIN(cfg->ep0_mps, buf->len);
215 }
216
217 buf->data += len;
218 buf->len -= len;
219
220 status = HAL_PCD_EP_Transmit(&priv->pcd, ep, data, len);
221 if (status != HAL_OK) {
222 LOG_ERR("HAL_PCD_EP_Transmit failed(0x%02x), %d", ep, (int)status);
223 return -EIO;
224 }
225
226 udc_ep_set_busy(dev, ep, true);
227
228 if (ep == USB_CONTROL_EP_IN && len > 0) {
229 /* Wait for an empty package from the host.
230 * This also flushes the TX FIFO to the host.
231 */
232 usbd_ctrl_feed_dout(dev, 0);
233 }
234
235 return 0;
236 }
237
udc_stm32_rx(const struct device * dev,uint8_t ep,struct net_buf * buf)238 static int udc_stm32_rx(const struct device *dev, uint8_t ep,
239 struct net_buf *buf)
240 {
241 struct udc_stm32_data *priv = udc_get_private(dev);
242 HAL_StatusTypeDef status;
243
244 LOG_DBG("RX ep 0x%02x len %u", ep, buf->size);
245
246 if (udc_ep_is_busy(dev, ep)) {
247 return 0;
248 }
249
250 status = HAL_PCD_EP_Receive(&priv->pcd, ep, buf->data, buf->size);
251 if (status != HAL_OK) {
252 LOG_ERR("HAL_PCD_EP_Receive failed(0x%02x), %d", ep, (int)status);
253 return -EIO;
254 }
255
256 udc_ep_set_busy(dev, ep, true);
257
258 return 0;
259 }
260
HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)261 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
262 {
263 uint32_t rx_count = HAL_PCD_EP_GetRxCount(hpcd, epnum);
264 struct udc_stm32_data *priv = hpcd2data(hpcd);
265 const struct device *dev = priv->dev;
266 uint8_t ep = epnum | USB_EP_DIR_OUT;
267 struct net_buf *buf;
268
269 LOG_DBG("DataOut ep 0x%02x", ep);
270
271 udc_ep_set_busy(dev, ep, false);
272
273 buf = udc_buf_get(dev, ep);
274 if (unlikely(buf == NULL)) {
275 LOG_ERR("ep 0x%02x queue is empty", ep);
276 return;
277 }
278
279 net_buf_add(buf, rx_count);
280
281 if (ep == USB_CONTROL_EP_OUT) {
282 if (udc_ctrl_stage_is_status_out(dev)) {
283 udc_ctrl_update_stage(dev, buf);
284 udc_ctrl_submit_status(dev, buf);
285 } else {
286 udc_ctrl_update_stage(dev, buf);
287 }
288
289 if (udc_ctrl_stage_is_status_in(dev)) {
290 udc_ctrl_submit_s_out_status(dev, buf);
291 }
292 } else {
293 udc_submit_ep_event(dev, buf, 0);
294 }
295
296 buf = udc_buf_peek(dev, ep);
297 if (buf) {
298 udc_stm32_rx(dev, ep, buf);
299 }
300 }
301
HAL_PCD_DataInStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)302 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
303 {
304 struct udc_stm32_data *priv = hpcd2data(hpcd);
305 const struct device *dev = priv->dev;
306 uint8_t ep = epnum | USB_EP_DIR_IN;
307 struct net_buf *buf;
308
309 LOG_DBG("DataIn ep 0x%02x", ep);
310
311 udc_ep_set_busy(dev, ep, false);
312
313 buf = udc_buf_peek(dev, ep);
314 if (unlikely(buf == NULL)) {
315 return;
316 }
317
318 if (ep == USB_CONTROL_EP_IN && buf->len) {
319 const struct udc_stm32_config *cfg = dev->config;
320 uint32_t len = MIN(cfg->ep0_mps, buf->len);
321
322 HAL_PCD_EP_Transmit(&priv->pcd, ep, buf->data, len);
323
324 buf->len -= len;
325 buf->data += len;
326
327 return;
328 }
329
330 if (udc_ep_buf_has_zlp(buf) && ep != USB_CONTROL_EP_IN) {
331 udc_ep_buf_clear_zlp(buf);
332 HAL_PCD_EP_Transmit(&priv->pcd, ep, buf->data, 0);
333
334 return;
335 }
336
337 udc_buf_get(dev, ep);
338
339 if (ep == USB_CONTROL_EP_IN) {
340 if (udc_ctrl_stage_is_status_in(dev) ||
341 udc_ctrl_stage_is_no_data(dev)) {
342 /* Status stage finished, notify upper layer */
343 udc_ctrl_submit_status(dev, buf);
344 }
345
346 /* Update to next stage of control transfer */
347 udc_ctrl_update_stage(dev, buf);
348
349 if (udc_ctrl_stage_is_status_out(dev)) {
350 /*
351 * IN transfer finished, release buffer,
352 * control OUT buffer should be already fed.
353 */
354 net_buf_unref(buf);
355 }
356
357 return;
358 }
359
360 udc_submit_ep_event(dev, buf, 0);
361
362 buf = udc_buf_peek(dev, ep);
363 if (buf) {
364 udc_stm32_tx(dev, ep, buf);
365 }
366 }
367
368 #if DT_INST_NODE_HAS_PROP(0, disconnect_gpios)
HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef * hpcd,uint8_t state)369 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
370 {
371 struct gpio_dt_spec usb_disconnect = GPIO_DT_SPEC_INST_GET(0, disconnect_gpios);
372
373 gpio_pin_configure_dt(&usb_disconnect,
374 state ? GPIO_OUTPUT_ACTIVE : GPIO_OUTPUT_INACTIVE);
375 }
376 #endif
377
udc_stm32_irq(const struct device * dev)378 static void udc_stm32_irq(const struct device *dev)
379 {
380 const struct udc_stm32_data *priv = udc_get_private(dev);
381
382 /* HAL irq handler will call the related above callback */
383 HAL_PCD_IRQHandler((PCD_HandleTypeDef *)&priv->pcd);
384 }
385
udc_stm32_init(const struct device * dev)386 int udc_stm32_init(const struct device *dev)
387 {
388 struct udc_stm32_data *priv = udc_get_private(dev);
389 HAL_StatusTypeDef status;
390
391 if (priv->clk_enable && priv->clk_enable()) {
392 LOG_ERR("Error enabling clock(s)");
393 return -EIO;
394 }
395
396 priv->pcd_prepare(dev);
397
398 status = HAL_PCD_Init(&priv->pcd);
399 if (status != HAL_OK) {
400 LOG_ERR("PCD_Init failed, %d", (int)status);
401 return -EIO;
402 }
403
404 HAL_PCD_Stop(&priv->pcd);
405
406 return 0;
407 }
408
409 #if defined(USB) || defined(USB_DRD_FS)
udc_stm32_mem_init(const struct device * dev)410 static inline void udc_stm32_mem_init(const struct device *dev)
411 {
412 struct udc_stm32_data *priv = udc_get_private(dev);
413 const struct udc_stm32_config *cfg = dev->config;
414
415 priv->occupied_mem = cfg->pma_offset;
416 }
417
udc_stm32_ep_mem_config(const struct device * dev,struct udc_ep_config * ep,bool enable)418 static int udc_stm32_ep_mem_config(const struct device *dev,
419 struct udc_ep_config *ep,
420 bool enable)
421 {
422 struct udc_stm32_data *priv = udc_get_private(dev);
423 const struct udc_stm32_config *cfg = dev->config;
424 uint32_t size;
425
426 size = MIN(ep->mps, cfg->ep_mps);
427
428 if (!enable) {
429 priv->occupied_mem -= size;
430 return 0;
431 }
432
433 if (priv->occupied_mem + size >= cfg->dram_size) {
434 LOG_ERR("Unable to allocate FIFO for 0x%02x", ep->addr);
435 return -ENOMEM;
436 }
437
438 /* Configure PMA offset for the endpoint */
439 HAL_PCDEx_PMAConfig(&priv->pcd, ep->addr, PCD_SNG_BUF,
440 priv->occupied_mem);
441
442 priv->occupied_mem += size;
443
444 return 0;
445 }
446 #else
udc_stm32_mem_init(const struct device * dev)447 static void udc_stm32_mem_init(const struct device *dev)
448 {
449 struct udc_stm32_data *priv = udc_get_private(dev);
450 const struct udc_stm32_config *cfg = dev->config;
451 int words;
452
453 LOG_DBG("DRAM size: %ub", cfg->dram_size);
454
455 if (cfg->ep_mps % 4 || cfg->ep0_mps % 4) {
456 LOG_ERR("Not a 32-bit word multiple: ep0(%u)|ep(%u)",
457 cfg->ep0_mps, cfg->ep_mps);
458 return;
459 }
460
461 /* The documentation is not clear at all about RX FiFo size requirement,
462 * Allocate a minimum of 0x40 words, which seems to work reliably.
463 */
464 words = MAX(0x40, cfg->ep_mps / 4);
465 HAL_PCDEx_SetRxFiFo(&priv->pcd, words);
466 priv->occupied_mem = words * 4;
467
468 /* For EP0 TX, reserve only one MPS */
469 HAL_PCDEx_SetTxFiFo(&priv->pcd, 0, cfg->ep0_mps / 4);
470 priv->occupied_mem += cfg->ep0_mps;
471
472 /* Reset TX allocs */
473 for (unsigned int i = 1U; i < cfg->num_endpoints; i++) {
474 HAL_PCDEx_SetTxFiFo(&priv->pcd, i, 0);
475 }
476 }
477
udc_stm32_ep_mem_config(const struct device * dev,struct udc_ep_config * ep,bool enable)478 static int udc_stm32_ep_mem_config(const struct device *dev,
479 struct udc_ep_config *ep,
480 bool enable)
481 {
482 struct udc_stm32_data *priv = udc_get_private(dev);
483 const struct udc_stm32_config *cfg = dev->config;
484 unsigned int words;
485
486 if (!(ep->addr & USB_EP_DIR_IN) || !USB_EP_GET_IDX(ep->addr)) {
487 return 0;
488 }
489
490 words = MIN(ep->mps, cfg->ep_mps) / 4;
491 words = (words <= 64) ? words * 2 : words;
492
493 if (!enable) {
494 if (priv->occupied_mem >= (words * 4)) {
495 priv->occupied_mem -= (words * 4);
496 }
497 HAL_PCDEx_SetTxFiFo(&priv->pcd, USB_EP_GET_IDX(ep->addr), 0);
498 return 0;
499 }
500
501 if (cfg->dram_size - priv->occupied_mem < words * 4) {
502 LOG_ERR("Unable to allocate FIFO for 0x%02x", ep->addr);
503 return -ENOMEM;
504 }
505
506 HAL_PCDEx_SetTxFiFo(&priv->pcd, USB_EP_GET_IDX(ep->addr), words);
507
508 priv->occupied_mem += words * 4;
509
510 return 0;
511 }
512 #endif
513
udc_stm32_enable(const struct device * dev)514 static int udc_stm32_enable(const struct device *dev)
515 {
516 struct udc_stm32_data *priv = udc_get_private(dev);
517 const struct udc_stm32_config *cfg = dev->config;
518 HAL_StatusTypeDef status;
519 int ret;
520
521 LOG_DBG("Enable UDC");
522
523 udc_stm32_mem_init(dev);
524
525 status = HAL_PCD_Start(&priv->pcd);
526 if (status != HAL_OK) {
527 LOG_ERR("PCD_Start failed, %d", (int)status);
528 return -EIO;
529 }
530
531 ret = udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT,
532 USB_EP_TYPE_CONTROL, cfg->ep0_mps, 0);
533 if (ret) {
534 LOG_ERR("Failed enabling ep 0x%02x", USB_CONTROL_EP_OUT);
535 return ret;
536 }
537
538 ret |= udc_ep_enable_internal(dev, USB_CONTROL_EP_IN,
539 USB_EP_TYPE_CONTROL, cfg->ep0_mps, 0);
540 if (ret) {
541 LOG_ERR("Failed enabling ep 0x%02x", USB_CONTROL_EP_IN);
542 return ret;
543 }
544
545 irq_enable(priv->irq);
546
547 return 0;
548 }
549
udc_stm32_disable(const struct device * dev)550 static int udc_stm32_disable(const struct device *dev)
551 {
552 struct udc_stm32_data *priv = udc_get_private(dev);
553 HAL_StatusTypeDef status;
554
555 irq_disable(UDC_STM32_IRQ);
556
557 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_OUT)) {
558 LOG_ERR("Failed to disable control endpoint");
559 return -EIO;
560 }
561
562 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_IN)) {
563 LOG_ERR("Failed to disable control endpoint");
564 return -EIO;
565 }
566
567 status = HAL_PCD_Stop(&priv->pcd);
568 if (status != HAL_OK) {
569 LOG_ERR("PCD_Stop failed, %d", (int)status);
570 return -EIO;
571 }
572
573 return 0;
574 }
575
udc_stm32_shutdown(const struct device * dev)576 static int udc_stm32_shutdown(const struct device *dev)
577 {
578 struct udc_stm32_data *priv = udc_get_private(dev);
579 HAL_StatusTypeDef status;
580
581 status = HAL_PCD_DeInit(&priv->pcd);
582 if (status != HAL_OK) {
583 LOG_ERR("PCD_DeInit failed, %d", (int)status);
584 /* continue anyway */
585 }
586
587 if (priv->clk_disable && priv->clk_disable()) {
588 LOG_ERR("Error disabling clock(s)");
589 /* continue anyway */
590 }
591
592 if (irq_is_enabled(priv->irq)) {
593 irq_disable(priv->irq);
594 }
595
596 return 0;
597 }
598
udc_stm32_set_address(const struct device * dev,const uint8_t addr)599 static int udc_stm32_set_address(const struct device *dev, const uint8_t addr)
600 {
601 struct udc_stm32_data *priv = udc_get_private(dev);
602 HAL_StatusTypeDef status;
603
604 LOG_DBG("Set Address %u", addr);
605
606 status = HAL_PCD_SetAddress(&priv->pcd, addr);
607 if (status != HAL_OK) {
608 LOG_ERR("HAL_PCD_SetAddress failed(0x%02x), %d",
609 addr, (int)status);
610 return -EIO;
611 }
612
613 return 0;
614 }
615
udc_stm32_host_wakeup(const struct device * dev)616 static int udc_stm32_host_wakeup(const struct device *dev)
617 {
618 struct udc_stm32_data *priv = udc_get_private(dev);
619 HAL_StatusTypeDef status;
620
621 status = HAL_PCD_ActivateRemoteWakeup(&priv->pcd);
622 if (status != HAL_OK) {
623 LOG_ERR("HAL_PCD_ActivateRemoteWakeup, %d", (int)status);
624 return -EIO;
625 }
626
627 /* Must be active from 1ms to 15ms as per reference manual. */
628 k_sleep(K_MSEC(2));
629
630 status = HAL_PCD_DeActivateRemoteWakeup(&priv->pcd);
631 if (status != HAL_OK) {
632 return -EIO;
633 }
634
635 return 0;
636 }
637
udc_stm32_ep_enable(const struct device * dev,struct udc_ep_config * ep_cfg)638 static int udc_stm32_ep_enable(const struct device *dev,
639 struct udc_ep_config *ep_cfg)
640 {
641 struct udc_stm32_data *priv = udc_get_private(dev);
642 HAL_StatusTypeDef status;
643 uint8_t ep_type;
644 int ret;
645
646 LOG_DBG("Enable ep 0x%02x", ep_cfg->addr);
647
648 switch (ep_cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) {
649 case USB_EP_TYPE_CONTROL:
650 ep_type = EP_TYPE_CTRL;
651 break;
652 case USB_EP_TYPE_BULK:
653 ep_type = EP_TYPE_BULK;
654 break;
655 case USB_EP_TYPE_INTERRUPT:
656 ep_type = EP_TYPE_INTR;
657 break;
658 case USB_EP_TYPE_ISO:
659 ep_type = EP_TYPE_ISOC;
660 break;
661 default:
662 return -EINVAL;
663 }
664
665 ret = udc_stm32_ep_mem_config(dev, ep_cfg, true);
666 if (ret) {
667 return ret;
668 }
669
670 status = HAL_PCD_EP_Open(&priv->pcd, ep_cfg->addr, ep_cfg->mps,
671 ep_type);
672 if (status != HAL_OK) {
673 LOG_ERR("HAL_PCD_EP_Open failed(0x%02x), %d",
674 ep_cfg->addr, (int)status);
675 return -EIO;
676 }
677
678 return 0;
679 }
680
udc_stm32_ep_disable(const struct device * dev,struct udc_ep_config * ep)681 static int udc_stm32_ep_disable(const struct device *dev,
682 struct udc_ep_config *ep)
683 {
684 struct udc_stm32_data *priv = udc_get_private(dev);
685 HAL_StatusTypeDef status;
686
687 LOG_DBG("Disable ep 0x%02x", ep->addr);
688
689 status = HAL_PCD_EP_Close(&priv->pcd, ep->addr);
690 if (status != HAL_OK) {
691 LOG_ERR("HAL_PCD_EP_Close failed(0x%02x), %d",
692 ep->addr, (int)status);
693 return -EIO;
694 }
695
696 return udc_stm32_ep_mem_config(dev, ep, false);
697 }
698
udc_stm32_ep_set_halt(const struct device * dev,struct udc_ep_config * cfg)699 static int udc_stm32_ep_set_halt(const struct device *dev,
700 struct udc_ep_config *cfg)
701 {
702 struct udc_stm32_data *priv = udc_get_private(dev);
703 HAL_StatusTypeDef status;
704
705 LOG_DBG("Halt ep 0x%02x", cfg->addr);
706
707 status = HAL_PCD_EP_SetStall(&priv->pcd, cfg->addr);
708 if (status != HAL_OK) {
709 LOG_ERR("HAL_PCD_EP_SetStall failed(0x%02x), %d",
710 cfg->addr, (int)status);
711 return -EIO;
712 }
713
714 return 0;
715 }
716
udc_stm32_ep_clear_halt(const struct device * dev,struct udc_ep_config * cfg)717 static int udc_stm32_ep_clear_halt(const struct device *dev,
718 struct udc_ep_config *cfg)
719 {
720 struct udc_stm32_data *priv = udc_get_private(dev);
721 HAL_StatusTypeDef status;
722
723 LOG_DBG("Clear halt for ep 0x%02x", cfg->addr);
724
725 status = HAL_PCD_EP_ClrStall(&priv->pcd, cfg->addr);
726 if (status != HAL_OK) {
727 LOG_ERR("HAL_PCD_EP_ClrStall failed(0x%02x), %d",
728 cfg->addr, (int)status);
729 return -EIO;
730 }
731
732 return 0;
733 }
734
udc_stm32_ep_flush(const struct device * dev,struct udc_ep_config * cfg)735 static int udc_stm32_ep_flush(const struct device *dev,
736 struct udc_ep_config *cfg)
737 {
738 struct udc_stm32_data *priv = udc_get_private(dev);
739 HAL_StatusTypeDef status;
740
741 LOG_DBG("Flush ep 0x%02x", cfg->addr);
742
743 status = HAL_PCD_EP_Flush(&priv->pcd, cfg->addr);
744 if (status != HAL_OK) {
745 LOG_ERR("HAL_PCD_EP_Flush failed(0x%02x), %d",
746 cfg->addr, (int)status);
747 return -EIO;
748 }
749
750 return 0;
751 }
752
udc_stm32_ep_enqueue(const struct device * dev,struct udc_ep_config * epcfg,struct net_buf * buf)753 static int udc_stm32_ep_enqueue(const struct device *dev,
754 struct udc_ep_config *epcfg,
755 struct net_buf *buf)
756 {
757 unsigned int lock_key;
758 int ret;
759
760 udc_buf_put(epcfg, buf);
761
762 lock_key = irq_lock();
763
764 if (USB_EP_DIR_IS_IN(epcfg->addr)) {
765 ret = udc_stm32_tx(dev, epcfg->addr, buf);
766 } else {
767 ret = udc_stm32_rx(dev, epcfg->addr, buf);
768 }
769
770 irq_unlock(lock_key);
771
772 return ret;
773 }
774
udc_stm32_ep_dequeue(const struct device * dev,struct udc_ep_config * epcfg)775 static int udc_stm32_ep_dequeue(const struct device *dev,
776 struct udc_ep_config *epcfg)
777 {
778 struct net_buf *buf;
779
780 udc_stm32_ep_flush(dev, epcfg);
781
782 buf = udc_buf_get_all(dev, epcfg->addr);
783 if (buf) {
784 udc_submit_ep_event(dev, buf, -ECONNABORTED);
785 }
786
787 udc_ep_set_busy(dev, epcfg->addr, false);
788
789 return 0;
790 }
791
udc_stm32_device_speed(const struct device * dev)792 static enum udc_bus_speed udc_stm32_device_speed(const struct device *dev)
793 {
794 struct udc_stm32_data *priv = udc_get_private(dev);
795
796 #ifdef USBD_HS_SPEED
797 if (priv->pcd.Init.speed == USBD_HS_SPEED) {
798 return UDC_BUS_SPEED_HS;
799 }
800 #endif
801
802 if (priv->pcd.Init.speed == USBD_FS_SPEED) {
803 return UDC_BUS_SPEED_FS;
804 }
805
806 return UDC_BUS_UNKNOWN;
807 }
808
809 static const struct udc_api udc_stm32_api = {
810 .lock = udc_stm32_lock,
811 .unlock = udc_stm32_unlock,
812 .init = udc_stm32_init,
813 .enable = udc_stm32_enable,
814 .disable = udc_stm32_disable,
815 .shutdown = udc_stm32_shutdown,
816 .set_address = udc_stm32_set_address,
817 .host_wakeup = udc_stm32_host_wakeup,
818 .ep_try_config = NULL,
819 .ep_enable = udc_stm32_ep_enable,
820 .ep_disable = udc_stm32_ep_disable,
821 .ep_set_halt = udc_stm32_ep_set_halt,
822 .ep_clear_halt = udc_stm32_ep_clear_halt,
823 .ep_enqueue = udc_stm32_ep_enqueue,
824 .ep_dequeue = udc_stm32_ep_dequeue,
825 .device_speed = udc_stm32_device_speed,
826 };
827
828 /* ----------------- Instance/Device specific data ----------------- */
829
830 /*
831 * USB, USB_OTG_FS and USB_DRD_FS are defined in STM32Cube HAL and allows to
832 * distinguish between two kind of USB DC. STM32 F0, F3, L0 and G4 series
833 * support USB device controller. STM32 F4 and F7 series support USB_OTG_FS
834 * device controller. STM32 F1 and L4 series support either USB or USB_OTG_FS
835 * device controller.STM32 G0 series supports USB_DRD_FS device controller.
836 *
837 * WARNING: Don't mix USB defined in STM32Cube HAL and CONFIG_USB_* from Zephyr
838 * Kconfig system.
839 */
840 #define USB_NUM_BIDIR_ENDPOINTS DT_INST_PROP(0, num_bidir_endpoints)
841
842 #if defined(USB) || defined(USB_DRD_FS)
843 #define EP0_MPS 64U
844 #define EP_MPS 64U
845 #define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
846 #define USB_RAM_SIZE DT_INST_PROP(0, ram_size)
847 #else /* USB_OTG_FS */
848 #define EP0_MPS USB_OTG_MAX_EP0_SIZE
849 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
850 #define EP_MPS USB_OTG_HS_MAX_PACKET_SIZE
851 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) || DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
852 #define EP_MPS USB_OTG_FS_MAX_PACKET_SIZE
853 #endif
854 #define USB_RAM_SIZE DT_INST_PROP(0, ram_size)
855 #define USB_BTABLE_SIZE 0
856 #endif /* USB */
857
858 #define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
859 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
860
861 #define USB_OTG_HS_ULPI_PHY (DT_HAS_COMPAT_STATUS_OKAY(usb_ulpi_phy) && \
862 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
863
864 static struct udc_stm32_data udc0_priv;
865
866 static struct udc_data udc0_data = {
867 .mutex = Z_MUTEX_INITIALIZER(udc0_data.mutex),
868 .priv = &udc0_priv,
869 };
870
871 static const struct udc_stm32_config udc0_cfg = {
872 .num_endpoints = USB_NUM_BIDIR_ENDPOINTS,
873 .dram_size = USB_RAM_SIZE,
874 .pma_offset = USB_BTABLE_SIZE,
875 .ep0_mps = EP0_MPS,
876 .ep_mps = EP_MPS,
877 };
878
879 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
usb_dc_stm32_get_maximum_speed(void)880 static uint32_t usb_dc_stm32_get_maximum_speed(void)
881 {
882 /*
883 * STM32L4 series USB LL API doesn't provide HIGH and HIGH_IN_FULL speed
884 * defines.
885 */
886 #if defined(CONFIG_SOC_SERIES_STM32L4X)
887 #define USB_OTG_SPEED_HIGH 0U
888 #define USB_OTG_SPEED_HIGH_IN_FULL 1U
889 #endif /* CONFIG_SOC_SERIES_STM32L4X */
890 /*
891 * If max-speed is not passed via DT, set it to USB controller's
892 * maximum hardware capability.
893 */
894 #if USB_OTG_HS_EMB_PHY || USB_OTG_HS_ULPI_PHY
895 uint32_t speed = USB_OTG_SPEED_HIGH;
896 #else
897 uint32_t speed = USB_OTG_SPEED_FULL;
898 #endif
899
900 #ifdef USB_MAXIMUM_SPEED
901
902 if (!strncmp(USB_MAXIMUM_SPEED, "high-speed", 10)) {
903 speed = USB_OTG_SPEED_HIGH;
904 } else if (!strncmp(USB_MAXIMUM_SPEED, "full-speed", 10)) {
905 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHY)
906 speed = USB_OTG_SPEED_HIGH_IN_FULL;
907 #else
908 speed = USB_OTG_SPEED_FULL;
909 #endif
910 } else {
911 LOG_DBG("Unsupported maximum speed defined in device tree. "
912 "USB controller will default to its maximum HW "
913 "capability");
914 }
915 #endif
916
917 return speed;
918 }
919 #endif /* USB_OTG_FS || USB_OTG_HS */
920
priv_pcd_prepare(const struct device * dev)921 static void priv_pcd_prepare(const struct device *dev)
922 {
923 struct udc_stm32_data *priv = udc_get_private(dev);
924 const struct udc_stm32_config *cfg = dev->config;
925
926 memset(&priv->pcd, 0, sizeof(priv->pcd));
927
928 /* Default values */
929 priv->pcd.Init.dev_endpoints = cfg->num_endpoints;
930 priv->pcd.Init.ep0_mps = cfg->ep0_mps;
931 priv->pcd.Init.speed = PCD_SPEED_FULL;
932
933 /* Per controller/Phy values */
934 #if defined(USB)
935 priv->pcd.Instance = USB;
936 #elif defined(USB_DRD_FS)
937 priv->pcd.Instance = USB_DRD_FS;
938 #elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
939 priv->pcd.Init.speed = usb_dc_stm32_get_maximum_speed();
940 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
941 priv->pcd.Instance = USB_OTG_HS;
942 #else
943 priv->pcd.Instance = USB_OTG_FS;
944 #endif
945 #endif /* USB */
946
947 #if USB_OTG_HS_EMB_PHY
948 priv->pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
949 #elif USB_OTG_HS_ULPI_PHY
950 priv->pcd.Init.phy_itface = USB_OTG_ULPI_PHY;
951 #else
952 priv->pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
953 #endif /* USB_OTG_HS_EMB_PHY */
954 }
955
956 static const struct stm32_pclken pclken[] = STM32_DT_INST_CLOCKS(0);
957
priv_clock_enable(void)958 static int priv_clock_enable(void)
959 {
960 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
961
962 if (!device_is_ready(clk)) {
963 LOG_ERR("clock control device not ready");
964 return -ENODEV;
965 }
966
967 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) && defined(CONFIG_SOC_SERIES_STM32U5X)
968 /* Sequence to enable the power of the OTG HS on a stm32U5 serie : Enable VDDUSB */
969 bool pwr_clk = LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PWR);
970
971 if (!pwr_clk) {
972 LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
973 }
974
975 /* Check that power range is 1 or 2 */
976 if (LL_PWR_GetRegulVoltageScaling() < LL_PWR_REGU_VOLTAGE_SCALE2) {
977 LOG_ERR("Wrong Power range to use USB OTG HS");
978 return -EIO;
979 }
980
981 LL_PWR_EnableVddUSB();
982 /* Configure VOSR register of USB HSTransceiverSupply(); */
983 LL_PWR_EnableUSBPowerSupply();
984 LL_PWR_EnableUSBEPODBooster();
985 while (LL_PWR_IsActiveFlag_USBBOOST() != 1) {
986 /* Wait for USB EPOD BOOST ready */
987 }
988
989 /* Leave the PWR clock in its initial position */
990 if (!pwr_clk) {
991 LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PWR);
992 }
993
994 /* Set the OTG PHY reference clock selection (through SYSCFG) block */
995 LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SYSCFG);
996 HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
997 /* Configuring the SYSCFG registers OTG_HS PHY : OTG_HS PHY enable*/
998 HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
999 #elif defined(PWR_USBSCR_USB33SV) || defined(PWR_SVMCR_USV)
1000 /*
1001 * VDDUSB independent USB supply (PWR clock is on)
1002 * with LL_PWR_EnableVDDUSB function (higher case)
1003 */
1004 LL_PWR_EnableVDDUSB();
1005 #endif
1006
1007 #if defined(CONFIG_SOC_SERIES_STM32H7X)
1008 LL_PWR_EnableUSBVoltageDetector();
1009
1010 /* Per AN2606: USBREGEN not supported when running in FS mode. */
1011 LL_PWR_DisableUSBReg();
1012 while (!LL_PWR_IsActiveFlag_USB()) {
1013 LOG_INF("PWR not active yet");
1014 k_sleep(K_MSEC(100));
1015 }
1016 #endif
1017
1018 if (DT_INST_NUM_CLOCKS(0) > 1) {
1019 if (clock_control_configure(clk, (clock_control_subsys_t *)&pclken[1],
1020 NULL) != 0) {
1021 LOG_ERR("Could not select USB domain clock");
1022 return -EIO;
1023 }
1024 }
1025
1026 if (clock_control_on(clk, (clock_control_subsys_t *)&pclken[0]) != 0) {
1027 LOG_ERR("Unable to enable USB clock");
1028 return -EIO;
1029 }
1030
1031 if (IS_ENABLED(CONFIG_USB_DC_STM32_CLOCK_CHECK)) {
1032 uint32_t usb_clock_rate;
1033
1034 if (clock_control_get_rate(clk,
1035 (clock_control_subsys_t *)&pclken[1],
1036 &usb_clock_rate) != 0) {
1037 LOG_ERR("Failed to get USB domain clock rate");
1038 return -EIO;
1039 }
1040
1041 if (usb_clock_rate != MHZ(48)) {
1042 LOG_ERR("USB Clock is not 48MHz (%d)", usb_clock_rate);
1043 return -ENOTSUP;
1044 }
1045 }
1046
1047 /* Previous check won't work in case of F1/F3. Add build time check */
1048 #if defined(RCC_CFGR_OTGFSPRE) || defined(RCC_CFGR_USBPRE)
1049
1050 #if (MHZ(48) == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) && !defined(STM32_PLL_USBPRE)
1051 /* PLL output clock is set to 48MHz, it should not be divided */
1052 #warning USBPRE/OTGFSPRE should be set in rcc node
1053 #endif
1054
1055 #endif /* RCC_CFGR_OTGFSPRE / RCC_CFGR_USBPRE */
1056
1057 #if USB_OTG_HS_ULPI_PHY
1058 #if defined(CONFIG_SOC_SERIES_STM32H7X)
1059 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
1060 #else
1061 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
1062 #endif
1063 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) /* USB_OTG_HS_ULPI_PHY */
1064 /* Disable ULPI interface (for external high-speed PHY) clock in sleep/low-power mode.
1065 * It is disabled by default in run power mode, no need to disable it.
1066 */
1067 #if defined(CONFIG_SOC_SERIES_STM32H7X)
1068 LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
1069 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
1070 LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_USBPHY);
1071 /* Both OTG HS and USBPHY sleep clock MUST be disabled here at the same time */
1072 LL_AHB2_GRP1_DisableClockStopSleep(LL_AHB2_GRP1_PERIPH_OTG_HS ||
1073 LL_AHB2_GRP1_PERIPH_USBPHY);
1074 #else
1075 LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
1076 #endif /* defined(CONFIG_SOC_SERIES_STM32H7X) */
1077
1078 #if USB_OTG_HS_EMB_PHY
1079 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
1080 #endif
1081 #elif defined(CONFIG_SOC_SERIES_STM32H7X) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
1082 /* The USB2 controller only works in FS mode, but the ULPI clock needs
1083 * to be disabled in sleep mode for it to work.
1084 */
1085 LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
1086 #endif /* USB_OTG_HS_ULPI_PHY */
1087
1088 return 0;
1089 }
1090
priv_clock_disable(void)1091 static int priv_clock_disable(void)
1092 {
1093 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
1094
1095 if (clock_control_off(clk, (clock_control_subsys_t *)&pclken[0]) != 0) {
1096 LOG_ERR("Unable to disable USB clock");
1097 return -EIO;
1098 }
1099 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs) && defined(CONFIG_SOC_SERIES_STM32U5X)
1100 LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_USBPHY);
1101 #endif
1102
1103 return 0;
1104 }
1105
1106 static struct udc_ep_config ep_cfg_in[DT_INST_PROP(0, num_bidir_endpoints)];
1107 static struct udc_ep_config ep_cfg_out[DT_INST_PROP(0, num_bidir_endpoints)];
1108
1109 PINCTRL_DT_INST_DEFINE(0);
1110 static const struct pinctrl_dev_config *usb_pcfg =
1111 PINCTRL_DT_INST_DEV_CONFIG_GET(0);
1112
1113 #if USB_OTG_HS_ULPI_PHY
1114 static const struct gpio_dt_spec ulpi_reset =
1115 GPIO_DT_SPEC_GET_OR(DT_PHANDLE(DT_INST(0, st_stm32_otghs), phys), reset_gpios, {0});
1116 #endif
1117
udc_stm32_driver_init0(const struct device * dev)1118 static int udc_stm32_driver_init0(const struct device *dev)
1119 {
1120 struct udc_stm32_data *priv = udc_get_private(dev);
1121 const struct udc_stm32_config *cfg = dev->config;
1122 struct udc_data *data = dev->data;
1123 int err;
1124
1125 for (unsigned int i = 0; i < ARRAY_SIZE(ep_cfg_out); i++) {
1126 ep_cfg_out[i].caps.out = 1;
1127 if (i == 0) {
1128 ep_cfg_out[i].caps.control = 1;
1129 ep_cfg_out[i].caps.mps = cfg->ep0_mps;
1130 } else {
1131 ep_cfg_out[i].caps.bulk = 1;
1132 ep_cfg_out[i].caps.interrupt = 1;
1133 ep_cfg_out[i].caps.iso = 1;
1134 ep_cfg_out[i].caps.mps = cfg->ep_mps;
1135 }
1136
1137 ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
1138 err = udc_register_ep(dev, &ep_cfg_out[i]);
1139 if (err != 0) {
1140 LOG_ERR("Failed to register endpoint");
1141 return err;
1142 }
1143 }
1144
1145 for (unsigned int i = 0; i < ARRAY_SIZE(ep_cfg_in); i++) {
1146 ep_cfg_in[i].caps.in = 1;
1147 if (i == 0) {
1148 ep_cfg_in[i].caps.control = 1;
1149 ep_cfg_in[i].caps.mps = cfg->ep0_mps;
1150 } else {
1151 ep_cfg_in[i].caps.bulk = 1;
1152 ep_cfg_in[i].caps.interrupt = 1;
1153 ep_cfg_in[i].caps.iso = 1;
1154 ep_cfg_in[i].caps.mps = 1023;
1155 }
1156
1157 ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
1158 err = udc_register_ep(dev, &ep_cfg_in[i]);
1159 if (err != 0) {
1160 LOG_ERR("Failed to register endpoint");
1161 return err;
1162 }
1163 }
1164
1165 data->caps.rwup = true;
1166 data->caps.out_ack = false;
1167 data->caps.mps0 = UDC_MPS0_64;
1168
1169 priv->dev = dev;
1170 priv->irq = UDC_STM32_IRQ;
1171 priv->clk_enable = priv_clock_enable;
1172 priv->clk_disable = priv_clock_disable;
1173 priv->pcd_prepare = priv_pcd_prepare;
1174
1175 IRQ_CONNECT(UDC_STM32_IRQ, UDC_STM32_IRQ_PRI, udc_stm32_irq,
1176 DEVICE_DT_INST_GET(0), 0);
1177
1178 err = pinctrl_apply_state(usb_pcfg, PINCTRL_STATE_DEFAULT);
1179 if (err < 0) {
1180 LOG_ERR("USB pinctrl setup failed (%d)", err);
1181 return err;
1182 }
1183
1184 #ifdef SYSCFG_CFGR1_USB_IT_RMP
1185 /*
1186 * STM32F302/F303: USB IRQ collides with CAN_1 IRQ (§14.1.3, RM0316)
1187 * Remap IRQ by default to enable use of both IPs simultaneoulsy
1188 * This should be done before calling any HAL function
1189 */
1190 if (LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SYSCFG)) {
1191 LL_SYSCFG_EnableRemapIT_USB();
1192 } else {
1193 LOG_ERR("System Configuration Controller clock is "
1194 "disabled. Unable to enable IRQ remapping.");
1195 }
1196 #endif
1197
1198 #if USB_OTG_HS_ULPI_PHY
1199 if (ulpi_reset.port != NULL) {
1200 if (!gpio_is_ready_dt(&ulpi_reset)) {
1201 LOG_ERR("Reset GPIO device not ready");
1202 return -EINVAL;
1203 }
1204 if (gpio_pin_configure_dt(&ulpi_reset, GPIO_OUTPUT_INACTIVE)) {
1205 LOG_ERR("Couldn't configure reset pin");
1206 return -EIO;
1207 }
1208 }
1209 #endif
1210
1211 /*cd
1212 * Required for at least STM32L4 devices as they electrically
1213 * isolate USB features from VDDUSB. It must be enabled before
1214 * USB can function. Refer to section 5.1.3 in DM00083560 or
1215 * DM00310109.
1216 */
1217 #ifdef PWR_CR2_USV
1218 #if defined(LL_APB1_GRP1_PERIPH_PWR)
1219 if (LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_PWR)) {
1220 LL_PWR_EnableVddUSB();
1221 } else {
1222 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
1223 LL_PWR_EnableVddUSB();
1224 LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
1225 }
1226 #else
1227 LL_PWR_EnableVddUSB();
1228 #endif /* defined(LL_APB1_GRP1_PERIPH_PWR) */
1229 #endif /* PWR_CR2_USV */
1230
1231 return 0;
1232 }
1233
1234 DEVICE_DT_INST_DEFINE(0, udc_stm32_driver_init0, NULL, &udc0_data, &udc0_cfg,
1235 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
1236 &udc_stm32_api);
1237
