1 /*
2 * SPDX-License-Identifier: Apache-2.0
3 * Copyright (c) 2024 sensry.io
4 */
5
6 #define DT_DRV_COMPAT sy1xx_sys_timer
7
8 #include <zephyr/init.h>
9 #include <zephyr/kernel.h>
10 #include <zephyr/sys/util.h>
11 #include <zephyr/drivers/timer/system_timer.h>
12 #include <soc.h>
13 #include <zephyr/irq.h>
14
15 #define SY1XX_SYS_TIMER_NODE DT_NODELABEL(systick)
16 #define SY1XX_SYS_TIMER_BASE_ADDR DT_REG_ADDR(SY1XX_SYS_TIMER_NODE)
17
18 #define SY1XX_MINIMUM_ALLOWED_TICK 1000
19
20 #define SY1XX_REG_TIMER_CMP_LO_OFFS 0x10
21
22 /* config bits */
23 #define SY1XX_TIMER_ENABLE_BIT 0
24 #define SY1XX_TIMER_RESET_BIT 1
25 #define SY1XX_TIMER_IRQ_ENABLE_BIT 2
26 #define SY1XX_TIMER_IEM_BIT 3
27 #define SY1XX_TIMER_CMP_CLR_BIT 4
28 #define SY1XX_TIMER_ONE_SHOT_BIT 5
29 #define SY1XX_TIMER_PRESCALER_ENABLE_BIT 6
30 #define SY1XX_TIMER_CLOCK_SOURCE_BIT 7
31 #define SY1XX_TIMER_PRESCALER_VALUE_BIT 8
32 #define SY1XX_TIMER_PRESCALER_VALUE_BITS 8
33 #define SY1XX_TIMER_64_BIT 31
34
35 /* config flags */
36 #define SY1XX_TIMER_ACTIVE 1
37 #define SY1XX_TIMER_IDLE 0
38
39 #define SY1XX_TIMER_RESET_ENABLED 1
40 #define SY1XX_TIMER_RESET_DISABLED 0
41
42 #define SY1XX_TIMER_IRQ_ENABLED 1
43 #define SY1XX_TIMER_IRQ_DISABLED 0
44
45 #define SY1XX_TIMER_IEM_ENABLED 1
46 #define SY1XX_TIMER_IEM_DISABLED 0
47
48 #define SY1XX_TIMER_CMPCLR_ENABLED 1
49 #define SY1XX_TIMER_CMPCLR_DISABLED 0
50
51 #define SY1XX_TIMER_ONE_SHOT_ENABLED 1
52 #define SY1XX_TIMER_ONE_SHOT_DISABLED 0
53
54 #define SY1XX_TIMER_REFCLK_ENABLED 1
55 #define SY1XX_TIMER_REFCLK_DISABLED 0
56
57 #define SY1XX_TIMER_PRESCALER_ENABLED 1
58 #define SY1XX_TIMER_PRESCALER_DISABLED 0
59
60 #define SY1XX_TIMER_MODE_64_ENABLED 1
61 #define SY1XX_TIMER_MODE_64_DISABLED 0
62
63 static volatile uint32_t current_sys_clock;
64
65 struct sy1xx_timer_cfg {
66 uint32_t tick_us;
67 };
68
sy1xx_timer_conf_prep(int enable,int reset,int irq_enable,int event_mask,int cmp_clr,int one_shot,int clk_source,int prescaler_enable,int prescaler,int mode_64)69 static inline unsigned int sy1xx_timer_conf_prep(int enable, int reset, int irq_enable,
70 int event_mask, int cmp_clr, int one_shot,
71 int clk_source, int prescaler_enable,
72 int prescaler, int mode_64)
73 {
74 return (enable << SY1XX_TIMER_ENABLE_BIT) | (reset << SY1XX_TIMER_RESET_BIT) |
75 (irq_enable << SY1XX_TIMER_IRQ_ENABLE_BIT) | (event_mask << SY1XX_TIMER_IEM_BIT) |
76 (cmp_clr << SY1XX_TIMER_CMP_CLR_BIT) | (one_shot << SY1XX_TIMER_ONE_SHOT_BIT) |
77 (clk_source << SY1XX_TIMER_CLOCK_SOURCE_BIT) |
78 (prescaler_enable << SY1XX_TIMER_PRESCALER_ENABLE_BIT) |
79 (prescaler << SY1XX_TIMER_PRESCALER_VALUE_BIT) | (mode_64 << SY1XX_TIMER_64_BIT);
80 }
81
sy1xx_sys_timer_reload(uint32_t base,uint32_t reload_timer_ticks)82 static void sy1xx_sys_timer_reload(uint32_t base, uint32_t reload_timer_ticks)
83 {
84 sys_write32(reload_timer_ticks, (base + SY1XX_REG_TIMER_CMP_LO_OFFS));
85 }
86
sy1xx_sys_timer_cfg_auto_reload(uint32_t base)87 static void sy1xx_sys_timer_cfg_auto_reload(uint32_t base)
88 {
89
90 uint32_t conf = sy1xx_timer_conf_prep(
91 SY1XX_TIMER_ACTIVE, SY1XX_TIMER_RESET_ENABLED, SY1XX_TIMER_IRQ_ENABLED,
92 SY1XX_TIMER_IEM_DISABLED, SY1XX_TIMER_CMPCLR_ENABLED, SY1XX_TIMER_ONE_SHOT_DISABLED,
93 SY1XX_TIMER_REFCLK_ENABLED, SY1XX_TIMER_PRESCALER_DISABLED, 0,
94 SY1XX_TIMER_MODE_64_DISABLED);
95
96 sys_write32(conf, base);
97 }
98
sy1xx_sys_timer_irq_enable(void)99 static void sy1xx_sys_timer_irq_enable(void)
100 {
101 soc_enable_irq(DT_IRQN(SY1XX_SYS_TIMER_NODE));
102 }
103
sy1xx_sys_timer_irq_disable(void)104 static void sy1xx_sys_timer_irq_disable(void)
105 {
106 soc_disable_irq(DT_IRQN(SY1XX_SYS_TIMER_NODE));
107 }
108
sy1xx_sys_timer_config(uint32_t base,struct sy1xx_timer_cfg * cfg)109 static int32_t sy1xx_sys_timer_config(uint32_t base, struct sy1xx_timer_cfg *cfg)
110 {
111
112 /* global irq disable */
113 uint32_t isr_state = arch_irq_lock();
114
115 if (cfg->tick_us < SY1XX_MINIMUM_ALLOWED_TICK) {
116 cfg->tick_us = SY1XX_MINIMUM_ALLOWED_TICK;
117 }
118
119 /* expect 1.0ms resolution => tick_us = 1000 */
120 uint32_t us = cfg->tick_us;
121 volatile double ticks_f =
122 (((double)us / (double)1000000) * (double)sy1xx_soc_get_rts_clock_frequency()) +
123 1.0;
124
125 volatile uint32_t timer_ticks = (uint32_t)ticks_f;
126
127 printk("timer [%d] expected %u (%d)\n", sy1xx_soc_get_rts_clock_frequency(), cfg->tick_us,
128 timer_ticks);
129
130 sy1xx_sys_timer_reload(base, timer_ticks);
131
132 sy1xx_sys_timer_cfg_auto_reload(base);
133
134 /* we always start timer irq disabled */
135 sy1xx_sys_timer_irq_disable();
136
137 /* restore global irq */
138 arch_irq_unlock(isr_state);
139
140 return 0;
141 }
142
sys_clock_elapsed(void)143 uint32_t sys_clock_elapsed(void)
144 {
145 return 0;
146 }
147
sys_clock_cycle_get_32(void)148 uint32_t sys_clock_cycle_get_32(void)
149 {
150 return current_sys_clock;
151 }
152
sy1xx_sys_timer_callback(const void * user_data)153 void sy1xx_sys_timer_callback(const void *user_data)
154 {
155 current_sys_clock += 1;
156
157 sys_clock_announce(1);
158 }
159
sy1xx_sys_timer_init(void)160 static int sy1xx_sys_timer_init(void)
161 {
162 printk("starting sys_timer\n");
163
164 struct sy1xx_timer_cfg timerCfg0 = {
165 .tick_us = DT_PROP(SY1XX_SYS_TIMER_NODE, ticks_us),
166 };
167
168 sy1xx_sys_timer_config(SY1XX_SYS_TIMER_BASE_ADDR, &timerCfg0);
169
170 uint32_t irq = arch_irq_lock();
171
172 /* register interrupt routine with zephyr */
173 irq_connect_dynamic(DT_IRQN(SY1XX_SYS_TIMER_NODE), 0, sy1xx_sys_timer_callback, NULL, 0);
174
175 sy1xx_sys_timer_irq_enable();
176
177 arch_irq_unlock(irq | 0x1);
178
179 return 0;
180 }
181
182 SYS_INIT(sy1xx_sys_timer_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
183
