1 /*
2 * Copyright (c) 2019 Intel Corporation
3 * Copyright (c) 2021 Microchip Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_xec_i2c_v2
9
10 #include <zephyr/kernel.h>
11 #include <soc.h>
12 #include <errno.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
15 #include <zephyr/drivers/gpio.h>
16 #include <zephyr/drivers/i2c.h>
17 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
18 #include <zephyr/drivers/pinctrl.h>
19 #include <zephyr/sys/printk.h>
20 #include <zephyr/sys/sys_io.h>
21 #include <zephyr/logging/log.h>
22 #include <zephyr/irq.h>
23 LOG_MODULE_REGISTER(i2c_mchp, CONFIG_I2C_LOG_LEVEL);
24
25 #include "i2c-priv.h"
26
27 #define SPEED_100KHZ_BUS 0
28 #define SPEED_400KHZ_BUS 1
29 #define SPEED_1MHZ_BUS 2
30
31 #define EC_OWN_I2C_ADDR 0x7F
32 #define RESET_WAIT_US 20
33
34 /* I2C timeout is 10 ms (WAIT_INTERVAL * WAIT_COUNT) */
35 #define WAIT_INTERVAL 50
36 #define WAIT_COUNT 200
37 #define STOP_WAIT_COUNT 500
38 #define PIN_CFG_WAIT 50
39
40 /* I2C Read/Write bit pos */
41 #define I2C_READ_WRITE_POS 0
42
43 /* I2C recover SCL low retries */
44 #define I2C_RECOVER_SCL_LOW_RETRIES 10
45 /* I2C recover SDA low retries */
46 #define I2C_RECOVER_SDA_LOW_RETRIES 3
47 /* I2C recovery bit bang delay */
48 #define I2C_RECOVER_BB_DELAY_US 5
49 /* I2C recovery SCL sample delay */
50 #define I2C_RECOVER_SCL_DELAY_US 50
51
52 /* I2C SCL and SDA lines(signals) */
53 #define I2C_LINES_SCL_HI BIT(SOC_I2C_SCL_POS)
54 #define I2C_LINES_SDA_HI BIT(SOC_I2C_SDA_POS)
55 #define I2C_LINES_BOTH_HI (I2C_LINES_SCL_HI | I2C_LINES_SDA_HI)
56
57 #define I2C_START 0U
58 #define I2C_RPT_START 1U
59
60 #define I2C_ENI_DIS 0U
61 #define I2C_ENI_EN 1U
62
63 #define I2C_WAIT_PIN_DEASSERT 0U
64 #define I2C_WAIT_PIN_ASSERT 1U
65
66 #define I2C_XEC_CTRL_WR_DLY 8
67
68 #define I2C_XEC_STATE_STOPPED 1U
69 #define I2C_XEC_STATE_OPEN 2U
70
71 #define I2C_XEC_OK 0
72 #define I2C_XEC_ERR_LAB 1
73 #define I2C_XEC_ERR_BUS 2
74 #define I2C_XEC_ERR_TMOUT 3
75
76 #define XEC_GPIO_CTRL_BASE DT_REG_ADDR(DT_NODELABEL(gpio_000_036))
77
78 struct xec_speed_cfg {
79 uint32_t bus_clk;
80 uint32_t data_timing;
81 uint32_t start_hold_time;
82 uint32_t idle_scale;
83 uint32_t timeout_scale;
84 };
85
86 struct i2c_xec_config {
87 uint32_t port_sel;
88 uint32_t base_addr;
89 uint32_t clock_freq;
90 uint8_t girq;
91 uint8_t girq_pos;
92 uint8_t pcr_idx;
93 uint8_t pcr_bitpos;
94 const struct pinctrl_dev_config *pcfg;
95 void (*irq_config_func)(void);
96 };
97
98 struct i2c_xec_data {
99 uint8_t state;
100 uint8_t read_discard;
101 uint8_t speed_id;
102 struct i2c_target_config *target_cfg;
103 bool target_attached;
104 bool target_read;
105 uint32_t i2c_compl;
106 uint8_t i2c_ctrl;
107 uint8_t i2c_addr;
108 uint8_t i2c_status;
109 };
110
111 /* Recommended programming values based on 16MHz
112 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
113 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
114 * (16MHz/400KHz -2) = 0x0F + 0x17
115 * (16MHz/1MHz -2) = 0x05 + 0x09
116 */
117 static const struct xec_speed_cfg xec_cfg_params[] = {
118 [SPEED_100KHZ_BUS] = {
119 .bus_clk = 0x00004F4F,
120 .data_timing = 0x0C4D5006,
121 .start_hold_time = 0x0000004D,
122 .idle_scale = 0x01FC01ED,
123 .timeout_scale = 0x4B9CC2C7,
124 },
125 [SPEED_400KHZ_BUS] = {
126 .bus_clk = 0x00000F17,
127 .data_timing = 0x040A0A06,
128 .start_hold_time = 0x0000000A,
129 .idle_scale = 0x01000050,
130 .timeout_scale = 0x159CC2C7,
131 },
132 [SPEED_1MHZ_BUS] = {
133 .bus_clk = 0x00000509,
134 .data_timing = 0x04060601,
135 .start_hold_time = 0x00000006,
136 .idle_scale = 0x10000050,
137 .timeout_scale = 0x089CC2C7,
138 },
139 };
140
i2c_ctl_wr(const struct device * dev,uint8_t ctrl)141 static void i2c_ctl_wr(const struct device *dev, uint8_t ctrl)
142 {
143 const struct i2c_xec_config *cfg =
144 (const struct i2c_xec_config *const) (dev->config);
145 struct i2c_xec_data *data =
146 (struct i2c_xec_data *const) (dev->data);
147 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
148
149 data->i2c_ctrl = ctrl;
150 regs->CTRLSTS = ctrl;
151 for (int i = 0; i < I2C_XEC_CTRL_WR_DLY; i++) {
152 regs->BLKID = ctrl;
153 }
154 }
155
156 static int i2c_xec_reset_config(const struct device *dev);
157
wait_bus_free(const struct device * dev,uint32_t nwait)158 static int wait_bus_free(const struct device *dev, uint32_t nwait)
159 {
160 const struct i2c_xec_config *cfg =
161 (const struct i2c_xec_config *const) (dev->config);
162 struct i2c_xec_data *data =
163 (struct i2c_xec_data *const) (dev->data);
164 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
165 uint32_t count = nwait;
166 uint8_t sts = 0;
167
168 while (count--) {
169 sts = regs->CTRLSTS;
170 data->i2c_status = sts;
171 if (sts & MCHP_I2C_SMB_STS_NBB) {
172 break; /* bus is free */
173 }
174 k_busy_wait(WAIT_INTERVAL);
175 }
176
177 /* NBB -> 1 not busy can occur for STOP, BER, or LAB */
178 if (sts == (MCHP_I2C_SMB_STS_PIN | MCHP_I2C_SMB_STS_NBB)) {
179 /* No service requested(PIN=1), NotBusy(NBB=1), and no errors */
180 return 0;
181 }
182
183 if (sts & MCHP_I2C_SMB_STS_BER) {
184 return I2C_XEC_ERR_BUS;
185 }
186
187 if (sts & MCHP_I2C_SMB_STS_LAB) {
188 return I2C_XEC_ERR_LAB;
189 }
190
191 return I2C_XEC_ERR_TMOUT;
192 }
193
194 /*
195 * returns state of I2C SCL and SDA lines.
196 * b[0] = SCL, b[1] = SDA
197 * Call soc specific routine to read GPIO pad input.
198 * Why? We can get the pins from our PINCTRL info but
199 * we do not know which pin is I2C clock and which pin
200 * is I2C data. There's no ordering in PINCTRL DT unless
201 * we impose an order.
202 */
get_lines(const struct device * dev)203 static uint32_t get_lines(const struct device *dev)
204 {
205 const struct i2c_xec_config *cfg =
206 (const struct i2c_xec_config *const) (dev->config);
207 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
208 uint8_t port = regs->CFG & MCHP_I2C_SMB_CFG_PORT_SEL_MASK;
209 uint32_t lines = 0u;
210
211 soc_i2c_port_lines_get(port, &lines);
212
213 return lines;
214 }
215
i2c_xec_reset_config(const struct device * dev)216 static int i2c_xec_reset_config(const struct device *dev)
217 {
218 const struct i2c_xec_config *cfg =
219 (const struct i2c_xec_config *const) (dev->config);
220 struct i2c_xec_data *data =
221 (struct i2c_xec_data *const) (dev->data);
222 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
223
224 data->state = I2C_XEC_STATE_STOPPED;
225 data->read_discard = 0;
226
227 /* Assert RESET */
228 z_mchp_xec_pcr_periph_reset(cfg->pcr_idx, cfg->pcr_bitpos);
229
230 regs->CFG = MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO |
231 MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO |
232 MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO |
233 MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
234
235 mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
236
237 /* PIN=1 to clear all status except NBB and synchronize */
238 i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN);
239
240 /*
241 * Controller implements two peripheral addresses for itself.
242 * It always monitors whether an external controller issues START
243 * plus target address. We should write valid peripheral addresses
244 * that do not match any peripheral on the bus.
245 * An alternative is to use the default 0 value which is the
246 * general call address and disable the general call match
247 * enable in the configuration register.
248 */
249 regs->OWN_ADDR = EC_OWN_I2C_ADDR | (EC_OWN_I2C_ADDR << 8);
250 #ifdef CONFIG_I2C_TARGET
251 if (data->target_cfg) {
252 regs->OWN_ADDR = data->target_cfg->address;
253 }
254 #endif
255 /* Port number and filter enable MUST be written before enabling */
256 regs->CFG |= BIT(14); /* disable general call */
257 regs->CFG |= MCHP_I2C_SMB_CFG_FEN;
258 regs->CFG |= (cfg->port_sel & MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
259
260 /*
261 * Before enabling the controller program the desired bus clock,
262 * repeated start hold time, data timing, and timeout scaling
263 * registers.
264 */
265 regs->BUSCLK = xec_cfg_params[data->speed_id].bus_clk;
266 regs->RSHTM = xec_cfg_params[data->speed_id].start_hold_time;
267 regs->DATATM = xec_cfg_params[data->speed_id].data_timing;
268 regs->TMOUTSC = xec_cfg_params[data->speed_id].timeout_scale;
269 regs->IDLSC = xec_cfg_params[data->speed_id].idle_scale;
270
271 /*
272 * PIN=1 clears all status except NBB
273 * ESO=1 enables output drivers
274 * ACK=1 enable ACK generation when data/address is clocked in.
275 */
276 i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN |
277 MCHP_I2C_SMB_CTRL_ESO |
278 MCHP_I2C_SMB_CTRL_ACK);
279
280 /* Enable controller */
281 regs->CFG |= MCHP_I2C_SMB_CFG_ENAB;
282 k_busy_wait(RESET_WAIT_US);
283
284 /* wait for NBB=1, BER, LAB, or timeout */
285 int rc = wait_bus_free(dev, WAIT_COUNT);
286
287 return rc;
288 }
289
290 /*
291 * If SCL is low sample I2C_RECOVER_SCL_LOW_RETRIES times with a 5 us delay
292 * between samples. If SCL remains low then return -EBUSY
293 * If SCL is High and SDA is low then loop up to I2C_RECOVER_SDA_LOW_RETRIES
294 * times driving the pins:
295 * Drive SCL high
296 * delay I2C_RECOVER_BB_DELAY_US
297 * Generate 9 clock pulses on SCL checking SDA before each falling edge of SCL
298 * If SDA goes high exit clock loop else to all 9 clocks
299 * Drive SDA low, delay 5 us, release SDA, delay 5 us
300 * Both lines are high then exit SDA recovery loop
301 * Both lines should not be driven
302 * Check both lines: if any bad return error else return success
303 * NOTE 1: Bit-bang mode uses a HW MUX to switch the lines away from the I2C
304 * controller logic to BB logic.
305 * NOTE 2: Bit-bang mode requires HW timeouts to be disabled.
306 * NOTE 3: Bit-bang mode requires the controller's configuration enable bit
307 * to be set.
308 * NOTE 4: The controller must be reset after using bit-bang mode.
309 */
i2c_xec_recover_bus(const struct device * dev)310 static int i2c_xec_recover_bus(const struct device *dev)
311 {
312 const struct i2c_xec_config *cfg =
313 (const struct i2c_xec_config *const) (dev->config);
314 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
315 int i, j, ret;
316
317 LOG_ERR("I2C attempt bus recovery\n");
318
319 /* reset controller to a known state */
320 z_mchp_xec_pcr_periph_reset(cfg->pcr_idx, cfg->pcr_bitpos);
321
322 regs->CFG = BIT(14) | MCHP_I2C_SMB_CFG_FEN |
323 (cfg->port_sel & MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
324 regs->CFG |= MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO |
325 MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO |
326 MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO |
327 MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
328 regs->CTRLSTS = MCHP_I2C_SMB_CTRL_PIN;
329 regs->BBCTRL = MCHP_I2C_SMB_BB_EN | MCHP_I2C_SMB_BB_CL |
330 MCHP_I2C_SMB_BB_DAT;
331 regs->CFG |= MCHP_I2C_SMB_CFG_ENAB;
332
333 if (!(regs->BBCTRL & MCHP_I2C_SMB_BB_CLKI_RO)) {
334 for (i = 0;; i++) {
335 if (i >= I2C_RECOVER_SCL_LOW_RETRIES) {
336 ret = -EBUSY;
337 goto recov_exit;
338 }
339 k_busy_wait(I2C_RECOVER_SCL_DELAY_US);
340 if (regs->BBCTRL & MCHP_I2C_SMB_BB_CLKI_RO) {
341 break; /* SCL went High */
342 }
343 }
344 }
345
346 if (regs->BBCTRL & MCHP_I2C_SMB_BB_DATI_RO) {
347 ret = 0;
348 goto recov_exit;
349 }
350
351 ret = -EBUSY;
352 /* SDA recovery */
353 for (i = 0; i < I2C_RECOVER_SDA_LOW_RETRIES; i++) {
354 /* SCL output mode and tri-stated */
355 regs->BBCTRL = MCHP_I2C_SMB_BB_EN |
356 MCHP_I2C_SMB_BB_SCL_DIR_OUT |
357 MCHP_I2C_SMB_BB_CL |
358 MCHP_I2C_SMB_BB_DAT;
359 k_busy_wait(I2C_RECOVER_BB_DELAY_US);
360
361 for (j = 0; j < 9; j++) {
362 if (regs->BBCTRL & MCHP_I2C_SMB_BB_DATI_RO) {
363 break;
364 }
365 /* drive SCL low */
366 regs->BBCTRL = MCHP_I2C_SMB_BB_EN |
367 MCHP_I2C_SMB_BB_SCL_DIR_OUT |
368 MCHP_I2C_SMB_BB_DAT;
369 k_busy_wait(I2C_RECOVER_BB_DELAY_US);
370 /* release SCL: pulled high by external pull-up */
371 regs->BBCTRL = MCHP_I2C_SMB_BB_EN |
372 MCHP_I2C_SMB_BB_SCL_DIR_OUT |
373 MCHP_I2C_SMB_BB_CL |
374 MCHP_I2C_SMB_BB_DAT;
375 k_busy_wait(I2C_RECOVER_BB_DELAY_US);
376 }
377
378 /* SCL is High. Produce rising edge on SCL for STOP */
379 regs->BBCTRL = MCHP_I2C_SMB_BB_EN | MCHP_I2C_SMB_BB_CL |
380 MCHP_I2C_SMB_BB_SDA_DIR_OUT; /* drive low */
381 k_busy_wait(I2C_RECOVER_BB_DELAY_US);
382 regs->BBCTRL = MCHP_I2C_SMB_BB_EN | MCHP_I2C_SMB_BB_CL |
383 MCHP_I2C_SMB_BB_DAT; /* release SCL */
384 k_busy_wait(I2C_RECOVER_BB_DELAY_US);
385
386 /* check if SCL and SDA are both high */
387 uint8_t bb = regs->BBCTRL &
388 (MCHP_I2C_SMB_BB_CLKI_RO | MCHP_I2C_SMB_BB_DATI_RO);
389
390 if (bb == (MCHP_I2C_SMB_BB_CLKI_RO | MCHP_I2C_SMB_BB_DATI_RO)) {
391 ret = 0; /* successful recovery */
392 goto recov_exit;
393 }
394 }
395
396 recov_exit:
397 /* BB mode disable reconnects SCL and SDA to I2C logic. */
398 regs->BBCTRL = 0;
399 regs->CTRLSTS = MCHP_I2C_SMB_CTRL_PIN; /* clear status */
400 i2c_xec_reset_config(dev); /* reset controller */
401
402 return ret;
403 }
404
405 #ifdef CONFIG_I2C_TARGET
406 /*
407 * Restart I2C controller as target for ACK of address match.
408 * Setting PIN clears all status in I2C.Status register except NBB.
409 */
restart_target(const struct device * dev)410 static void restart_target(const struct device *dev)
411 {
412 i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
413 MCHP_I2C_SMB_CTRL_ACK | MCHP_I2C_SMB_CTRL_ENI);
414 }
415
416 /*
417 * Configure I2C controller acting as target to NACK the next received byte.
418 * NOTE: Firmware must re-enable ACK generation before the start of the next
419 * transaction otherwise the controller will NACK its target addresses.
420 */
target_config_for_nack(const struct device * dev)421 static void target_config_for_nack(const struct device *dev)
422 {
423 i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
424 MCHP_I2C_SMB_CTRL_ENI);
425 }
426 #endif
427
wait_pin(const struct device * dev,bool pin_assert,uint32_t nwait)428 static int wait_pin(const struct device *dev, bool pin_assert, uint32_t nwait)
429 {
430 const struct i2c_xec_config *cfg =
431 (const struct i2c_xec_config *const) (dev->config);
432 struct i2c_xec_data *data =
433 (struct i2c_xec_data *const) (dev->data);
434 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
435
436 for (;;) {
437 k_busy_wait(WAIT_INTERVAL);
438
439 data->i2c_compl = regs->COMPL;
440 data->i2c_status = regs->CTRLSTS;
441
442 if (data->i2c_status & MCHP_I2C_SMB_STS_BER) {
443 return I2C_XEC_ERR_BUS;
444 }
445
446 if (data->i2c_status & MCHP_I2C_SMB_STS_LAB) {
447 return I2C_XEC_ERR_LAB;
448 }
449
450 if (!(data->i2c_status & MCHP_I2C_SMB_STS_PIN)) {
451 if (pin_assert) {
452 return 0;
453 }
454 } else if (!pin_assert) {
455 return 0;
456 }
457
458 if (nwait) {
459 --nwait;
460 } else {
461 break;
462 }
463 }
464
465 return I2C_XEC_ERR_TMOUT;
466 }
467
gen_start(const struct device * dev,uint8_t addr8,bool is_repeated)468 static int gen_start(const struct device *dev, uint8_t addr8,
469 bool is_repeated)
470 {
471 const struct i2c_xec_config *cfg =
472 (const struct i2c_xec_config *const) (dev->config);
473 struct i2c_xec_data *data =
474 (struct i2c_xec_data *const) (dev->data);
475 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
476 uint8_t ctrl = MCHP_I2C_SMB_CTRL_ESO | MCHP_I2C_SMB_CTRL_STA |
477 MCHP_I2C_SMB_CTRL_ACK;
478
479 data->i2c_addr = addr8;
480
481 if (is_repeated) {
482 i2c_ctl_wr(dev, ctrl);
483 regs->I2CDATA = addr8;
484 } else {
485 ctrl |= MCHP_I2C_SMB_CTRL_PIN;
486 regs->I2CDATA = addr8;
487 i2c_ctl_wr(dev, ctrl);
488 }
489
490 return 0;
491 }
492
gen_stop(const struct device * dev)493 static int gen_stop(const struct device *dev)
494 {
495 const struct i2c_xec_config *cfg =
496 (const struct i2c_xec_config *const) (dev->config);
497 struct i2c_xec_data *data =
498 (struct i2c_xec_data *const) (dev->data);
499 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
500 uint8_t ctrl = MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
501 MCHP_I2C_SMB_CTRL_STO | MCHP_I2C_SMB_CTRL_ACK;
502
503 data->i2c_ctrl = ctrl;
504 regs->CTRLSTS = ctrl;
505
506 return 0;
507 }
508
do_stop(const struct device * dev,uint32_t nwait)509 static int do_stop(const struct device *dev, uint32_t nwait)
510 {
511 const struct i2c_xec_config *cfg =
512 (const struct i2c_xec_config *const) (dev->config);
513 struct i2c_xec_data *data =
514 (struct i2c_xec_data *const) (dev->data);
515 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
516 int ret;
517
518 data->state = I2C_XEC_STATE_STOPPED;
519 data->read_discard = 0;
520
521 gen_stop(dev);
522 ret = wait_bus_free(dev, nwait);
523 if (ret) {
524 uint32_t lines = get_lines(dev);
525
526 if (lines != I2C_LINES_BOTH_HI) {
527 i2c_xec_recover_bus(dev);
528 } else {
529 ret = i2c_xec_reset_config(dev);
530 }
531 }
532
533 if (ret == 0) {
534 /* stop success: prepare for next transaction */
535 regs->CTRLSTS = MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
536 MCHP_I2C_SMB_CTRL_ACK;
537 }
538
539 return ret;
540 }
541
do_start(const struct device * dev,uint8_t addr8,bool is_repeated)542 static int do_start(const struct device *dev, uint8_t addr8, bool is_repeated)
543 {
544 struct i2c_xec_data *data =
545 (struct i2c_xec_data *const) (dev->data);
546 int ret;
547
548 gen_start(dev, addr8, is_repeated);
549 ret = wait_pin(dev, I2C_WAIT_PIN_ASSERT, WAIT_COUNT);
550 if (ret) {
551 i2c_xec_reset_config(dev);
552 return ret;
553 }
554
555 /* PIN 1->0: check for NACK */
556 if (data->i2c_status & MCHP_I2C_SMB_STS_LRB_AD0) {
557 gen_stop(dev);
558 ret = wait_bus_free(dev, WAIT_COUNT);
559 if (ret) {
560 i2c_xec_reset_config(dev);
561 }
562 return -EIO;
563 }
564
565 return 0;
566 }
567
i2c_xec_configure(const struct device * dev,uint32_t dev_config_raw)568 static int i2c_xec_configure(const struct device *dev,
569 uint32_t dev_config_raw)
570 {
571 struct i2c_xec_data *data =
572 (struct i2c_xec_data *const) (dev->data);
573
574 if (!(dev_config_raw & I2C_MODE_CONTROLLER)) {
575 return -ENOTSUP;
576 }
577
578 if (dev_config_raw & I2C_ADDR_10_BITS) {
579 return -ENOTSUP;
580 }
581
582 switch (I2C_SPEED_GET(dev_config_raw)) {
583 case I2C_SPEED_STANDARD:
584 data->speed_id = SPEED_100KHZ_BUS;
585 break;
586 case I2C_SPEED_FAST:
587 data->speed_id = SPEED_400KHZ_BUS;
588 break;
589 case I2C_SPEED_FAST_PLUS:
590 data->speed_id = SPEED_1MHZ_BUS;
591 break;
592 default:
593 return -EINVAL;
594 }
595
596 int ret = i2c_xec_reset_config(dev);
597
598 return ret;
599 }
600
601 /* I2C Controller transmit: polling implementation */
ctrl_tx(const struct device * dev,struct i2c_msg * msg,uint16_t addr)602 static int ctrl_tx(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
603 {
604 const struct i2c_xec_config *cfg =
605 (const struct i2c_xec_config *const) (dev->config);
606 struct i2c_xec_data *data =
607 (struct i2c_xec_data *const) (dev->data);
608 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
609 int ret = 0;
610 uint8_t mflags = msg->flags;
611 uint8_t addr8 = (uint8_t)((addr & 0x7FU) << 1);
612
613 if (data->state == I2C_XEC_STATE_STOPPED) {
614 data->i2c_addr = addr8;
615 /* Is bus free and controller ready? */
616 ret = wait_bus_free(dev, WAIT_COUNT);
617 if (ret) {
618 ret = i2c_xec_recover_bus(dev);
619 if (ret) {
620 return ret;
621 }
622 }
623
624 ret = do_start(dev, addr8, I2C_START);
625 if (ret) {
626 return ret;
627 }
628
629 data->state = I2C_XEC_STATE_OPEN;
630
631 } else if (mflags & I2C_MSG_RESTART) {
632 data->i2c_addr = addr8;
633 ret = do_start(dev, addr8, I2C_RPT_START);
634 if (ret) {
635 return ret;
636 }
637 }
638
639 for (size_t n = 0; n < msg->len; n++) {
640 regs->I2CDATA = msg->buf[n];
641 ret = wait_pin(dev, I2C_WAIT_PIN_ASSERT, WAIT_COUNT);
642 if (ret) {
643 i2c_xec_reset_config(dev);
644 return ret;
645 }
646 if (data->i2c_status & MCHP_I2C_SMB_STS_LRB_AD0) { /* NACK? */
647 do_stop(dev, STOP_WAIT_COUNT);
648 return -EIO;
649 }
650 }
651
652 if (mflags & I2C_MSG_STOP) {
653 ret = do_stop(dev, STOP_WAIT_COUNT);
654 }
655
656 return ret;
657 }
658
659 /*
660 * I2C Controller receive: polling implementation
661 * Transmitting a target address with BIT[0] == 1 causes the controller
662 * to enter controller-read mode where every read of I2CDATA generates
663 * clocks for the next byte. When we generate START or Repeated-START
664 * and transmit an address the address is also clocked in during
665 * address transmission. The address must read and discarded.
666 * Read of I2CDATA returns data currently in I2C read buffer, sets
667 * I2CSTATUS.PIN = 1, and !!generates clocks for the next
668 * byte!!
669 * For this controller to NACK the last byte we must clear the
670 * I2C CTRL register ACK bit BEFORE reading the next to last
671 * byte. Before reading the last byte we configure I2C CTRL to generate a STOP
672 * and then read the last byte from I2 DATA.
673 * When controller is in STOP mode it will not generate clocks when I2CDATA is
674 * read. UGLY HW DESIGN.
675 * We will NOT attempt to follow this HW design for Controller read except
676 * when all information is available: STOP message flag set AND number of
677 * bytes to read including dummy is >= 2. General usage can result in the
678 * controller not NACK'ing the last byte.
679 */
ctrl_rx(const struct device * dev,struct i2c_msg * msg,uint16_t addr)680 static int ctrl_rx(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
681 {
682 const struct i2c_xec_config *cfg =
683 (const struct i2c_xec_config *const) (dev->config);
684 struct i2c_xec_data *data =
685 (struct i2c_xec_data *const) (dev->data);
686 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
687 int ret = 0;
688 size_t data_len = msg->len;
689 uint8_t mflags = msg->flags;
690 uint8_t addr8 = (uint8_t)(((addr & 0x7FU) << 1) | BIT(0));
691 uint8_t temp = 0;
692
693 if (data->state == I2C_XEC_STATE_STOPPED) {
694 data->i2c_addr = addr8;
695 /* Is bus free and controller ready? */
696 ret = wait_bus_free(dev, WAIT_COUNT);
697 if (ret) {
698 i2c_xec_reset_config(dev);
699 return ret;
700 }
701
702 ret = do_start(dev, addr8, I2C_START);
703 if (ret) {
704 return ret;
705 }
706
707 data->state = I2C_XEC_STATE_OPEN;
708
709 /* controller clocked address into I2CDATA */
710 data->read_discard = 1U;
711
712 } else if (mflags & I2C_MSG_RESTART) {
713 data->i2c_addr = addr8;
714 ret = do_start(dev, addr8, I2C_RPT_START);
715 if (ret) {
716 return ret;
717 }
718
719 /* controller clocked address into I2CDATA */
720 data->read_discard = 1U;
721 }
722
723 if (!data_len) { /* requested message length is 0 */
724 ret = 0;
725 if (mflags & I2C_MSG_STOP) {
726 data->state = I2C_XEC_STATE_STOPPED;
727 data->read_discard = 0;
728 ret = do_stop(dev, STOP_WAIT_COUNT);
729 }
730 return ret;
731 }
732
733 if (data->read_discard) {
734 data_len++;
735 }
736
737 uint8_t *p8 = &msg->buf[0];
738
739 while (data_len) {
740 if (mflags & I2C_MSG_STOP) {
741 if (data_len == 2) {
742 i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_ESO);
743 } else if (data_len == 1) {
744 break;
745 }
746 }
747 temp = regs->I2CDATA; /* generates clocks */
748 if (data->read_discard) {
749 data->read_discard = 0;
750 } else {
751 *p8++ = temp;
752 }
753 ret = wait_pin(dev, I2C_WAIT_PIN_ASSERT, WAIT_COUNT);
754 if (ret) {
755 i2c_xec_reset_config(dev);
756 return ret;
757 }
758 data_len--;
759 }
760
761 if (mflags & I2C_MSG_STOP) {
762 data->state = I2C_XEC_STATE_STOPPED;
763 data->read_discard = 0;
764 ret = do_stop(dev, STOP_WAIT_COUNT);
765 if (ret == 0) {
766 *p8 = regs->I2CDATA;
767 }
768 }
769
770 return ret;
771 }
772
i2c_xec_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)773 static int i2c_xec_transfer(const struct device *dev, struct i2c_msg *msgs,
774 uint8_t num_msgs, uint16_t addr)
775 {
776 struct i2c_xec_data *data = dev->data;
777 int ret = 0;
778
779 #ifdef CONFIG_I2C_TARGET
780 if (data->target_attached) {
781 LOG_ERR("Device is registered as target");
782 return -EBUSY;
783 }
784 #endif
785
786 for (uint8_t i = 0; i < num_msgs; i++) {
787 struct i2c_msg *m = &msgs[i];
788
789 if ((m->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
790 ret = ctrl_tx(dev, m, addr);
791 } else {
792 ret = ctrl_rx(dev, m, addr);
793 }
794 if (ret) {
795 data->state = I2C_XEC_STATE_STOPPED;
796 data->read_discard = 0;
797 LOG_ERR("i2x_xfr: flags: %x error: %d", m->flags, ret);
798 break;
799 }
800 }
801
802 return ret;
803 }
804
i2c_xec_bus_isr(const struct device * dev)805 static void i2c_xec_bus_isr(const struct device *dev)
806 {
807 #ifdef CONFIG_I2C_TARGET
808 const struct i2c_xec_config *cfg =
809 (const struct i2c_xec_config *const) (dev->config);
810 struct i2c_xec_data *data = dev->data;
811 const struct i2c_target_callbacks *target_cb =
812 data->target_cfg->callbacks;
813 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
814 int ret;
815 uint32_t status;
816 uint32_t compl_status;
817 uint8_t val;
818 uint8_t dummy = 0U;
819
820 /* Get current status */
821 status = regs->CTRLSTS;
822 compl_status = regs->COMPL & MCHP_I2C_SMB_CMPL_RW1C_MASK;
823
824 /* Idle interrupt enabled and active? */
825 if ((regs->CFG & MCHP_I2C_SMB_CFG_ENIDI) &&
826 (compl_status & MCHP_I2C_SMB_CMPL_IDLE_RWC)) {
827 regs->CFG &= ~MCHP_I2C_SMB_CFG_ENIDI;
828 if (status & MCHP_I2C_SMB_STS_NBB) {
829 restart_target(dev);
830 goto clear_iag;
831 }
832 }
833
834 if (!data->target_attached) {
835 goto clear_iag;
836 }
837
838 /* Bus Error */
839 if (status & MCHP_I2C_SMB_STS_BER) {
840 if (target_cb->stop) {
841 target_cb->stop(data->target_cfg);
842 }
843 restart_target(dev);
844 goto clear_iag;
845 }
846
847 /* External stop */
848 if (status & MCHP_I2C_SMB_STS_EXT_STOP) {
849 if (target_cb->stop) {
850 target_cb->stop(data->target_cfg);
851 }
852 restart_target(dev);
853 goto clear_iag;
854 }
855
856 /* Address byte handling */
857 if (status & MCHP_I2C_SMB_STS_AAS) {
858 if (status & MCHP_I2C_SMB_STS_PIN) {
859 goto clear_iag;
860 }
861
862 uint8_t rx_data = regs->I2CDATA;
863
864 if (rx_data & BIT(I2C_READ_WRITE_POS)) {
865 /* target transmitter mode */
866 data->target_read = true;
867 val = dummy;
868 if (target_cb->read_requested) {
869 target_cb->read_requested(
870 data->target_cfg, &val);
871
872 /* Application target transmit handler
873 * does not have data to send. In
874 * target transmit mode the external
875 * Controller is ACK's data we send.
876 * All we can do is keep sending dummy
877 * data. We assume read_requested does
878 * not modify the value pointed to by val
879 * if it has not data(returns error).
880 */
881 }
882 /*
883 * Writing I2CData causes this HW to release SCL
884 * ending clock stretching. The external Controller
885 * senses SCL released and begins generating clocks
886 * and capturing data driven by this controller
887 * on SDA. External Controller ACK's data until it
888 * wants no more then it will NACK.
889 */
890 regs->I2CDATA = val;
891 goto clear_iag; /* Exit ISR */
892 } else {
893 /* target receiver mode */
894 data->target_read = false;
895 if (target_cb->write_requested) {
896 ret = target_cb->write_requested(
897 data->target_cfg);
898 if (ret) {
899 /*
900 * Application handler can't accept
901 * data. Configure HW to NACK next
902 * data transmitted by external
903 * Controller.
904 * !!! TODO We must re-program our HW
905 * for address ACK before next
906 * transaction is begun !!!
907 */
908 target_config_for_nack(dev);
909 }
910 }
911 goto clear_iag; /* Exit ISR */
912 }
913 }
914
915 if (data->target_read) { /* Target transmitter mode */
916
917 /* Master has Nacked, then just write a dummy byte */
918 status = regs->CTRLSTS;
919 if (status & MCHP_I2C_SMB_STS_LRB_AD0) {
920
921 /*
922 * ISSUE: HW will not detect external STOP in
923 * target transmit mode. Enable IDLE interrupt
924 * to catch PIN 0 -> 1 and NBB 0 -> 1.
925 */
926 regs->CFG |= MCHP_I2C_SMB_CFG_ENIDI;
927
928 /*
929 * dummy write causes this controller's PIN status
930 * to de-assert 0 -> 1. Data is not transmitted.
931 * SCL is not driven low by this controller.
932 */
933 regs->I2CDATA = dummy;
934
935 status = regs->CTRLSTS;
936
937 } else {
938 val = dummy;
939 if (target_cb->read_processed) {
940 target_cb->read_processed(
941 data->target_cfg, &val);
942 }
943 regs->I2CDATA = val;
944 }
945 } else { /* target receiver mode */
946 /*
947 * Reading the I2CData register causes this target to release
948 * SCL. The external Controller senses SCL released generates
949 * clocks for transmitting the next data byte.
950 * Reading I2C Data register causes PIN status 0 -> 1.
951 */
952 val = regs->I2CDATA;
953 if (target_cb->write_received) {
954 /*
955 * Call back returns error if we should NACK
956 * next byte.
957 */
958 ret = target_cb->write_received(data->target_cfg, val);
959 if (ret) {
960 /*
961 * Configure HW to NACK next byte. It will not
962 * generate clocks for another byte of data
963 */
964 target_config_for_nack(dev);
965 }
966 }
967 }
968
969 clear_iag:
970 regs->COMPL = compl_status;
971 mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
972 #endif
973 }
974
975 #ifdef CONFIG_I2C_TARGET
i2c_xec_target_register(const struct device * dev,struct i2c_target_config * config)976 static int i2c_xec_target_register(const struct device *dev,
977 struct i2c_target_config *config)
978 {
979 const struct i2c_xec_config *cfg = dev->config;
980 struct i2c_xec_data *data = dev->data;
981 int ret;
982
983 if (!config) {
984 return -EINVAL;
985 }
986
987 if (data->target_attached) {
988 return -EBUSY;
989 }
990
991 /* Wait for any outstanding transactions to complete so that
992 * the bus is free
993 */
994 ret = wait_bus_free(dev, WAIT_COUNT);
995 if (ret) {
996 return ret;
997 }
998
999 data->target_cfg = config;
1000
1001 ret = i2c_xec_reset_config(dev);
1002 if (ret) {
1003 return ret;
1004 }
1005
1006 restart_target(dev);
1007
1008 data->target_attached = true;
1009
1010 /* Clear before enabling girq bit */
1011 mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
1012 mchp_xec_ecia_girq_src_en(cfg->girq, cfg->girq_pos);
1013
1014 return 0;
1015 }
1016
i2c_xec_target_unregister(const struct device * dev,struct i2c_target_config * config)1017 static int i2c_xec_target_unregister(const struct device *dev,
1018 struct i2c_target_config *config)
1019 {
1020 const struct i2c_xec_config *cfg = dev->config;
1021 struct i2c_xec_data *data = dev->data;
1022
1023 if (!data->target_attached) {
1024 return -EINVAL;
1025 }
1026
1027 data->target_cfg = NULL;
1028 data->target_attached = false;
1029
1030 mchp_xec_ecia_girq_src_dis(cfg->girq, cfg->girq_pos);
1031
1032 return 0;
1033 }
1034 #endif
1035
1036 static DEVICE_API(i2c, i2c_xec_driver_api) = {
1037 .configure = i2c_xec_configure,
1038 .transfer = i2c_xec_transfer,
1039 #ifdef CONFIG_I2C_TARGET
1040 .target_register = i2c_xec_target_register,
1041 .target_unregister = i2c_xec_target_unregister,
1042 #endif
1043 #ifdef CONFIG_I2C_RTIO
1044 .iodev_submit = i2c_iodev_submit_fallback,
1045 #endif
1046 };
1047
i2c_xec_init(const struct device * dev)1048 static int i2c_xec_init(const struct device *dev)
1049 {
1050 const struct i2c_xec_config *cfg = dev->config;
1051 struct i2c_xec_data *data =
1052 (struct i2c_xec_data *const) (dev->data);
1053 int ret;
1054 uint32_t bitrate_cfg;
1055
1056 data->state = I2C_XEC_STATE_STOPPED;
1057 data->target_cfg = NULL;
1058 data->target_attached = false;
1059
1060 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
1061 if (ret != 0) {
1062 LOG_ERR("XEC I2C pinctrl setup failed (%d)", ret);
1063 return ret;
1064 }
1065
1066 bitrate_cfg = i2c_map_dt_bitrate(cfg->clock_freq);
1067 if (!bitrate_cfg) {
1068 return -EINVAL;
1069 }
1070
1071 /* Default configuration */
1072 ret = i2c_xec_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
1073 if (ret) {
1074 return ret;
1075 }
1076
1077 #ifdef CONFIG_I2C_TARGET
1078 const struct i2c_xec_config *config =
1079 (const struct i2c_xec_config *const) (dev->config);
1080
1081 config->irq_config_func();
1082 #endif
1083 return 0;
1084 }
1085
1086 #define I2C_XEC_DEVICE(n) \
1087 \
1088 PINCTRL_DT_INST_DEFINE(n); \
1089 \
1090 static void i2c_xec_irq_config_func_##n(void); \
1091 \
1092 static struct i2c_xec_data i2c_xec_data_##n; \
1093 static const struct i2c_xec_config i2c_xec_config_##n = { \
1094 .base_addr = \
1095 DT_INST_REG_ADDR(n), \
1096 .port_sel = DT_INST_PROP(n, port_sel), \
1097 .clock_freq = DT_INST_PROP(n, clock_frequency), \
1098 .girq = DT_INST_PROP_BY_IDX(n, girqs, 0), \
1099 .girq_pos = DT_INST_PROP_BY_IDX(n, girqs, 1), \
1100 .pcr_idx = DT_INST_PROP_BY_IDX(n, pcrs, 0), \
1101 .pcr_bitpos = DT_INST_PROP_BY_IDX(n, pcrs, 1), \
1102 .irq_config_func = i2c_xec_irq_config_func_##n, \
1103 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
1104 }; \
1105 I2C_DEVICE_DT_INST_DEFINE(n, i2c_xec_init, NULL, \
1106 &i2c_xec_data_##n, &i2c_xec_config_##n, \
1107 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
1108 &i2c_xec_driver_api); \
1109 \
1110 static void i2c_xec_irq_config_func_##n(void) \
1111 { \
1112 IRQ_CONNECT(DT_INST_IRQN(n), \
1113 DT_INST_IRQ(n, priority), \
1114 i2c_xec_bus_isr, \
1115 DEVICE_DT_INST_GET(n), 0); \
1116 irq_enable(DT_INST_IRQN(n)); \
1117 }
1118
1119 DT_INST_FOREACH_STATUS_OKAY(I2C_XEC_DEVICE)
1120
