1 /*
2  * Copyright (c) 2022 Andes Technology Corporation
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file I2C driver for AndesTech atciic100 IP
9  */
10 #include <errno.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/device.h>
13 #include <zephyr/drivers/i2c.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/sys/sys_io.h>
16 
17 #define I2C_MAX_COUNT		256
18 #define BURST_CMD_COUNT		1
19 
20 #define RED_IDR			0x00
21 #define REG_CFG			0x10
22 #define REG_INTE		0x14
23 #define REG_STAT		0x18
24 #define REG_ADDR		0x1C
25 #define REG_DATA		0x20
26 #define REG_CTRL		0x24
27 #define REG_CMD			0x28
28 #define REG_SET			0x2C
29 
30 #define I2C_BASE(dev) \
31 	((const struct i2c_atciic100_config * const)(dev)->config)->base
32 
33 #define I2C_CFG(dev)	(I2C_BASE(dev) + REG_CFG)
34 #define I2C_INTE(dev)	(I2C_BASE(dev) + REG_INTE)
35 #define I2C_STAT(dev)	(I2C_BASE(dev) + REG_STAT)
36 #define I2C_ADDR(dev)	(I2C_BASE(dev) + REG_ADDR)
37 #define I2C_CMD(dev)	(I2C_BASE(dev) + REG_CMD)
38 #define I2C_SET(dev)	(I2C_BASE(dev) + REG_SET)
39 #define I2C_DATA(dev)	(I2C_BASE(dev) + REG_DATA)
40 #define I2C_CTRL(dev)	(I2C_BASE(dev) + REG_CTRL)
41 
42 #define TARGET_ADDR_MSK			BIT_MASK(10)
43 #define DATA_MSK			BIT_MASK(8)
44 
45 /* Interrupt Enable Register(RW) */
46 #define IEN_ALL				BIT_MASK(10)
47 #define IEN_CMPL			BIT(9)
48 #define IEN_BYTE_RECV			BIT(8)
49 #define IEN_BYTE_TRANS			BIT(7)
50 #define IEN_START			BIT(6)
51 #define IEN_STOP			BIT(5)
52 #define IEN_ARB_LOSE			BIT(4)
53 #define IEN_ADDR_HIT			BIT(3)
54 #define IEN_FIFO_HALF			BIT(2)
55 #define IEN_FIFO_FULL			BIT(1)
56 #define IEN_FIFO_EMPTY			BIT(0)
57 
58 /* Status Register(RW) */
59 #define STATUS_W1C_ALL			(BIT_MASK(7) << 3)
60 #define STATUS_LINE_SDA			BIT(14)
61 #define STATUS_LINE_SCL			BIT(13)
62 #define STATUS_GEN_CALL			BIT(12)
63 #define STATUS_BUS_BUSY			BIT(11)
64 #define STATUS_ACK			BIT(10)
65 #define STATUS_CMPL			BIT(9)
66 #define STATUS_BYTE_RECV		BIT(8)
67 #define STATUS_BYTE_TRANS		BIT(7)
68 #define STATUS_START			BIT(6)
69 #define STATUS_STOP			BIT(5)
70 #define STATUS_ARB_LOSE			BIT(4)
71 #define STATUS_ADDR_HIT			BIT(3)
72 #define STATUS_FIFO_HALF		BIT(2)
73 #define STATUS_FIFO_FULL		BIT(1)
74 #define STATUS_FIFO_EMPTY		BIT(0)
75 
76 /* Control Register(RW) */
77 #define CTRL_PHASE_START		BIT(12)
78 #define CTRL_PHASE_ADDR			BIT(11)
79 #define CTRL_PHASE_DATA			BIT(10)
80 #define CTRL_PHASE_STOP			BIT(9)
81 #define CTRL_DIR			BIT(8)
82 #define CTRL_DATA_COUNT			BIT_MASK(8)
83 
84 /* Command Register(RW) */
85 #define CMD_MSK				BIT_MASK(3)
86 #define CMD_NO_ACT			(0x0)
87 #define CMD_ISSUE_TRANSACTION		(0x1)
88 #define CMD_ACK				(0x2)
89 #define CMD_NACK			(0x3)
90 #define CMD_CLEAR_FIFO			(0x4)
91 #define CMD_RESET_I2C			(0x5)
92 
93 /* Setup Register(RW) */
94 #define SETUP_T_SUDAT			(BIT_MASK(5) << 24)
95 #define SETUP_T_SP			(BIT_MASK(3) << 21)
96 #define SETUP_T_HDDAT			(BIT_MASK(5) << 16)
97 #define SETUP_T_SCL_RATIO		BIT(13)
98 #define SETUP_T_SCLHI			(BIT_MASK(9) << 4)
99 #define SETUP_DMA_EN			BIT(3)
100 #define SETUP_CONTROLLER		BIT(2)
101 #define SETUP_ADDRESSING		BIT(1)
102 #define SETUP_I2C_EN			BIT(0)
103 
104 #if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 30000000
105 
106 #define SETUP_T_SUDAT_STD		(0x3)
107 #define SETUP_T_SP_STD			(0x1)
108 #define SETUP_T_HDDAT_STD		(5)
109 #define SETUP_T_SCL_RATIO_STD		(0x0)
110 #define SETUP_T_SCLHI_STD		(138)
111 
112 #define SETUP_T_SUDAT_FAST		(0x0)
113 #define SETUP_T_SP_FAST			(0x1)
114 #define SETUP_T_HDDAT_FAST		(5)
115 #define SETUP_T_SCL_RATIO_FAST		(0x1)
116 #define SETUP_T_SCLHI_FAST		(18)
117 
118 #define SETUP_T_SUDAT_FAST_P		(0x0)
119 #define SETUP_T_SP_FAST_P		(0x1)
120 #define SETUP_T_HDDAT_FAST_P		(0x0)
121 #define SETUP_T_SCL_RATIO_FAST_P	(0x1)
122 #define SETUP_T_SCLHI_FAST_P		(6)
123 
124 #elif CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 40000000
125 
126 #define SETUP_T_SUDAT_STD		(0x4)
127 #define SETUP_T_SP_STD			(0x2)
128 #define SETUP_T_HDDAT_STD		(0x6)
129 #define SETUP_T_SCL_RATIO_STD		(0x0)
130 #define SETUP_T_SCLHI_STD		(182)
131 
132 #define SETUP_T_SUDAT_FAST		(0x0)
133 #define SETUP_T_SP_FAST			(0x2)
134 #define SETUP_T_HDDAT_FAST		(0x6)
135 #define SETUP_T_SCL_RATIO_FAST		(0x1)
136 #define SETUP_T_SCLHI_FAST		(23)
137 
138 #define SETUP_T_SUDAT_FAST_P		(0x0)
139 #define SETUP_T_SP_FAST_P		(0x2)
140 #define SETUP_T_HDDAT_FAST_P		(0x0)
141 #define SETUP_T_SCL_RATIO_FAST_P	(0x1)
142 #define SETUP_T_SCLHI_FAST_P		(7)
143 
144 #else
145 
146 #define SETUP_T_SUDAT_STD		(0x9)
147 #define SETUP_T_SP_STD			(0x3)
148 #define SETUP_T_HDDAT_STD		(12)
149 #define SETUP_T_SCL_RATIO_STD		(0x0)
150 #define SETUP_T_SCLHI_STD		(287)
151 
152 #define SETUP_T_SUDAT_FAST		(0x0)
153 #define SETUP_T_SP_FAST			(0x3)
154 #define SETUP_T_HDDAT_FAST		(12)
155 #define SETUP_T_SCL_RATIO_FAST		(0x1)
156 #define SETUP_T_SCLHI_FAST		(38)
157 
158 #define SETUP_T_SUDAT_FAST_P		(0x0)
159 #define SETUP_T_SP_FAST_P		(0x3)
160 #define SETUP_T_HDDAT_FAST_P		(0x0)
161 #define SETUP_T_SCL_RATIO_FAST_P	(0x1)
162 #define SETUP_T_SCLHI_FAST_P		(13)
163 
164 #endif
165 
166 #define SETUP_SPEED_MSK			(SETUP_T_SUDAT		| \
167 					SETUP_T_SP		| \
168 					SETUP_T_HDDAT		| \
169 					SETUP_T_SCL_RATIO	| \
170 					SETUP_T_SCLHI)
171 
172 #define SETUP_SPEED_STD			((SETUP_T_SUDAT_STD << 24)	| \
173 					(SETUP_T_SP_STD  << 21)		| \
174 					(SETUP_T_HDDAT_STD << 16)	| \
175 					(SETUP_T_SCL_RATIO_STD << 13)	| \
176 					(SETUP_T_SCLHI_STD << 4))
177 
178 #define SETUP_SPEED_FAST		((SETUP_T_SUDAT_FAST << 24)	| \
179 					(SETUP_T_SP_FAST  << 21)	| \
180 					(SETUP_T_HDDAT_FAST << 16)	| \
181 					(SETUP_T_SCL_RATIO_FAST << 13)	| \
182 					(SETUP_T_SCLHI_FAST << 4))
183 
184 #define SETUP_SPEED_FAST_PLUS		((SETUP_T_SUDAT_FAST_P << 24)	| \
185 					(SETUP_T_SP_FAST_P  << 21)	| \
186 					(SETUP_T_HDDAT_FAST_P << 16)	| \
187 					(SETUP_T_SCL_RATIO_FAST_P << 13)| \
188 					(SETUP_T_SCLHI_FAST_P << 4))
189 
190 #define MAX_XFER_SZ			(256)
191 
192 enum _i2c_ctrl_reg_item_dir {
193 	I2C_CONTROLLER_TX = 0x0,
194 	I2C_CONTROLLER_RX = 0x1,
195 	I2C_TARGET_TX = 0x1,
196 	I2C_TARGET_RX = 0x0,
197 };
198 
199 /* I2C driver running state */
200 enum _i2c_driver_state {
201 	I2C_DRV_NONE = 0x0,
202 	I2C_DRV_INIT = BIT(0),
203 	I2C_DRV_POWER = BIT(1),
204 	I2C_DRV_CFG_PARAM = BIT(2),
205 	I2C_DRV_CONTROLLER_TX = BIT(3),
206 	I2C_DRV_CONTROLLER_RX = BIT(4),
207 	I2C_DRV_TARGET_TX = BIT(5),
208 	I2C_DRV_TARGET_RX = BIT(6),
209 	I2C_DRV_CONTROLLER_TX_CMPL = BIT(7),
210 	I2C_DRV_CONTROLLER_RX_CMPL = BIT(8),
211 	I2C_DRV_TARGET_TX_CMPL = BIT(9),
212 	I2C_DRV_TARGET_RX_CMPL = BIT(10),
213 };
214 
215 /* brief I2C Status */
216 struct _i2c_status {
217 /* /< Mode: 0=Slave, 1=Master */
218 	uint32_t mode:1;
219 	uint32_t general_call: 1;
220 	uint32_t arbitration_lost : 1;
221 	uint32_t target_ack       : 1;
222 };
223 
224 struct i2c_atciic100_dev_data_t {
225 	struct k_sem			bus_lock;
226 	struct k_sem			device_sync_sem;
227 	volatile uint32_t		driver_state;
228 	uint8_t				*middleware_rx_buf;
229 	uint8_t				*middleware_tx_buf;
230 	uint32_t			fifo_depth;
231 	uint32_t			target_addr;
232 	uint32_t			xfer_wt_num;
233 	uint32_t			xfer_rd_num;
234 	uint32_t			xfered_data_wt_ptr; /* write pointer  */
235 	uint32_t			xfered_data_rd_ptr; /* read pointer  */
236 	volatile struct _i2c_status	status;
237 	const struct i2c_target_callbacks	*target_callbacks;
238 	struct i2c_target_config	*target_config;
239 };
240