1 /*
2 * Copyright (c) 2023 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_espi_taf
8
9 #include <soc.h>
10 #include <zephyr/drivers/espi.h>
11 #include <zephyr/drivers/espi_saf.h>
12 #include <zephyr/drivers/flash.h>
13 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
14 #include <zephyr/drivers/flash/npcx_flash_api_ex.h>
15 #endif
16 #include <zephyr/kernel.h>
17 #include <zephyr/logging/log.h>
18
19 LOG_MODULE_REGISTER(espi_taf, CONFIG_ESPI_LOG_LEVEL);
20
21 #define NPCX_TAF_PRIME_FLASH_NODE DT_ALIAS(taf_flash)
22 #define NPCX_TAF_SEC_FLASH_NODE DT_ALIAS(taf_flash1)
23
24 #define NPCX_TAF_ALLOC_SIZE(node) (MB(1) << DT_ENUM_IDX(node, spi_dev_size))
25
26 static const struct device *const spi_dev = DEVICE_DT_GET(NPCX_TAF_PRIME_FLASH_NODE);
27 #if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
28 static const struct device *const spi_dev1 = DEVICE_DT_GET(NPCX_TAF_SEC_FLASH_NODE);
29 #endif
30
31 enum ESPI_TAF_ERASE_LEN {
32 NPCX_ESPI_TAF_ERASE_LEN_4KB,
33 NPCX_ESPI_TAF_ERASE_LEN_32KB,
34 NPCX_ESPI_TAF_ERASE_LEN_64KB,
35 NPCX_ESPI_TAF_ERASE_LEN_128KB,
36 NPCX_ESPI_TAF_ERASE_LEN_MAX,
37 };
38
39 struct espi_taf_npcx_config {
40 uintptr_t base;
41 uintptr_t mapped_addr;
42 uintptr_t rx_plsz;
43 enum NPCX_ESPI_TAF_ERASE_BLOCK_SIZE erase_sz;
44 enum NPCX_ESPI_TAF_MAX_READ_REQ max_rd_sz;
45 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
46 uint8_t rpmc_cnt_num;
47 uint8_t rpmc_op1_code;
48 #endif
49 };
50
51 #define MAX_TX_PAYLOAD_SIZE DT_PROP(DT_INST_PARENT(0), tx_plsize)
52
53 struct espi_taf_npcx_data {
54 sys_slist_t *callbacks;
55 const struct device *host_dev;
56 uint8_t taf_type;
57 uint8_t taf_tag;
58 uint32_t address;
59 uint16_t length;
60 uint32_t src[16];
61 uint8_t read_buf[MAX_TX_PAYLOAD_SIZE];
62 struct k_work work;
63 #if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
64 const struct device *low_dev_ptr;
65 const struct device *high_dev_ptr;
66 uint32_t low_dev_size;
67 #endif
68 };
69
70 static struct espi_taf_npcx_data npcx_espi_taf_data;
71 static struct espi_callback espi_taf_cb;
72
73 #define HAL_INSTANCE(dev) \
74 ((struct espi_reg *)((const struct espi_taf_npcx_config *) \
75 (dev)->config)->base)
76
77 #define FLBASE_ADDR ( \
78 GET_FIELD(inst->FLASHBASE, NPCX_FLASHBASE_FLBASE_ADDR) \
79 << GET_FIELD_POS(NPCX_FLASHBASE_FLBASE_ADDR))
80
81 #define PRTR_BADDR(i) ( \
82 GET_FIELD(inst->FLASH_PRTR_BADDR[i], NPCX_FLASH_PRTR_BADDR) \
83 << GET_FIELD_POS(NPCX_FLASH_PRTR_BADDR))
84
85 #define PRTR_HADDR(i) ( \
86 GET_FIELD(inst->FLASH_PRTR_HADDR[i], NPCX_FLASH_PRTR_HADDR) \
87 << GET_FIELD_POS(NPCX_FLASH_PRTR_HADDR)) | 0xFFF;
88
espi_taf_get_pckt(const struct device * dev,struct espi_taf_npcx_data * pckt,struct espi_event event)89 static void espi_taf_get_pckt(const struct device *dev, struct espi_taf_npcx_data *pckt,
90 struct espi_event event)
91 {
92 struct espi_taf_pckt *data_ptr;
93
94 data_ptr = (struct espi_taf_pckt *)event.evt_data;
95
96 pckt->taf_type = data_ptr->type;
97 pckt->length = data_ptr->len;
98 pckt->taf_tag = data_ptr->tag;
99 pckt->address = data_ptr->addr;
100 if ((data_ptr->type == NPCX_ESPI_TAF_REQ_WRITE) ||
101 (IS_ENABLED(CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT) &&
102 (data_ptr->type == NPCX_ESPI_TAF_REQ_RPMC_OP1))) {
103 memcpy(pckt->src, data_ptr->src, sizeof(pckt->src));
104 }
105 }
106
107 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
108 /* Check access region of read request is protected or not */
espi_taf_check_read_protect(const struct device * dev,uint32_t addr,uint32_t len,uint8_t tag)109 static bool espi_taf_check_read_protect(const struct device *dev, uint32_t addr, uint32_t len,
110 uint8_t tag)
111 {
112 struct espi_reg *const inst = HAL_INSTANCE(dev);
113 uint32_t flash_addr = addr;
114 uint8_t i;
115 uint16_t override_rd;
116 uint32_t base, high;
117 bool rdpr;
118
119 flash_addr += FLBASE_ADDR;
120
121 for (i = 0; i < CONFIG_ESPI_TAF_PR_NUM; i++) {
122 base = PRTR_BADDR(i);
123 high = PRTR_HADDR(i);
124
125 rdpr = IS_BIT_SET(inst->FLASH_PRTR_BADDR[i], NPCX_FRGN_RPR);
126 override_rd = GET_FIELD(inst->FLASH_RGN_TAG_OVR[i], NPCX_FLASH_TAG_OVR_RPR);
127
128 if (rdpr && !IS_BIT_SET(override_rd, tag) &&
129 (base <= flash_addr + len - 1 && flash_addr <= high)) {
130 return true;
131 }
132 }
133
134 return false;
135 }
136 #endif
137
138 /* Check access region of write request is protected or not */
espi_taf_check_write_protect(const struct device * dev,uint32_t addr,uint32_t len,uint8_t tag)139 static bool espi_taf_check_write_protect(const struct device *dev, uint32_t addr,
140 uint32_t len, uint8_t tag)
141 {
142 struct espi_reg *const inst = HAL_INSTANCE(dev);
143 uint32_t flash_addr = addr;
144 uint8_t i;
145 uint16_t override_wr;
146 uint32_t base, high;
147 bool wrpr;
148
149 flash_addr += FLBASE_ADDR;
150
151 for (i = 0; i < CONFIG_ESPI_TAF_PR_NUM; i++) {
152 base = PRTR_BADDR(i);
153 high = PRTR_HADDR(i);
154
155 wrpr = IS_BIT_SET(inst->FLASH_PRTR_BADDR[i], NPCX_FRGN_WPR);
156 override_wr = GET_FIELD(inst->FLASH_RGN_TAG_OVR[i], NPCX_FLASH_TAG_OVR_WPR);
157
158 if (wrpr && !IS_BIT_SET(override_wr, tag) &&
159 (base <= flash_addr + len - 1 && flash_addr <= high)) {
160 return true;
161 }
162 }
163
164 return false;
165 }
166
espi_taf_npcx_configure(const struct device * dev,const struct espi_saf_cfg * cfg)167 static int espi_taf_npcx_configure(const struct device *dev, const struct espi_saf_cfg *cfg)
168 {
169 struct espi_reg *const inst = HAL_INSTANCE(dev);
170
171 if (cfg->nflash_devices == 0U) {
172 return -EINVAL;
173 }
174
175 #if defined(CONFIG_ESPI_TAF_AUTO_MODE)
176 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
177 #else
178 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
179 #endif
180
181 return 0;
182 }
183
espi_taf_npcx_set_pr(const struct device * dev,const struct espi_saf_protection * pr)184 static int espi_taf_npcx_set_pr(const struct device *dev, const struct espi_saf_protection *pr)
185 {
186 struct espi_reg *const inst = HAL_INSTANCE(dev);
187 const struct espi_saf_pr *preg = pr->pregions;
188 size_t n = pr->nregions;
189 uint8_t regnum;
190 uint16_t bitmask, offset;
191 uint32_t rw_pr, override_rw;
192
193 if ((dev == NULL) || (pr == NULL)) {
194 return -EINVAL;
195 }
196
197 if (pr->nregions >= CONFIG_ESPI_TAF_PR_NUM) {
198 return -EINVAL;
199 }
200
201 while (n--) {
202 regnum = preg->pr_num;
203
204 if (regnum >= CONFIG_ESPI_TAF_PR_NUM) {
205 return -EINVAL;
206 }
207
208 rw_pr = preg->master_bm_we << NPCX_FRGN_WPR;
209 rw_pr = rw_pr | (preg->master_bm_rd << NPCX_FRGN_RPR);
210
211 if (preg->flags) {
212 bitmask = BIT_MASK(GET_FIELD_SZ(NPCX_FLASH_PRTR_BADDR));
213 offset = GET_FIELD_POS(NPCX_FLASH_PRTR_BADDR);
214 inst->FLASH_PRTR_BADDR[regnum] = ((preg->start & bitmask) << offset)
215 | rw_pr;
216 bitmask = BIT_MASK(GET_FIELD_SZ(NPCX_FLASH_PRTR_HADDR));
217 offset = GET_FIELD_POS(NPCX_FLASH_PRTR_HADDR);
218 inst->FLASH_PRTR_HADDR[regnum] = (preg->end & bitmask) << offset;
219 }
220
221 override_rw = (preg->override_r << 16) | preg->override_w;
222 inst->FLASH_RGN_TAG_OVR[regnum] = override_rw;
223 preg++;
224 }
225
226 return 0;
227 }
228
espi_taf_npcx_activate(const struct device * dev)229 static int espi_taf_npcx_activate(const struct device *dev)
230 {
231 struct espi_reg *const inst = HAL_INSTANCE(dev);
232
233 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
234 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_BLK_FLASH_NP_FREE);
235
236 return 0;
237 }
238
espi_taf_npcx_channel_ready(const struct device * dev)239 static bool espi_taf_npcx_channel_ready(const struct device *dev)
240 {
241 struct espi_reg *const inst = HAL_INSTANCE(dev);
242 uint8_t ret =
243 GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLCAPA) & NPCX_FLASH_SHARING_CAP_SUPP_TAF;
244
245 if (ret != NPCX_FLASH_SHARING_CAP_SUPP_TAF) {
246 return false;
247 }
248
249 if (!device_is_ready(spi_dev)) {
250 return false;
251 }
252 #if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
253 if (!device_is_ready(spi_dev1)) {
254 return false;
255 }
256 #endif
257
258 return true;
259 }
260
261 /* This routine set FLASH_C_AVAIL for standard request */
taf_set_flash_c_avail(const struct device * dev)262 static void taf_set_flash_c_avail(const struct device *dev)
263 {
264 struct espi_reg *const inst = HAL_INSTANCE(dev);
265 uint32_t tmp = inst->FLASHCTL;
266
267 /*
268 * Clear FLASHCTL_FLASH_NP_FREE to avoid host puts a flash
269 * standard request command at here.
270 */
271 tmp &= NPCX_FLASHCTL_ACCESS_MASK;
272
273 /* Set FLASHCTL_FLASH_TX_AVAIL */
274 tmp |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
275 inst->FLASHCTL = tmp;
276 }
277
278 /* This routine release FLASH_NP_FREE for standard request */
taf_release_flash_np_free(const struct device * dev)279 static void taf_release_flash_np_free(const struct device *dev)
280 {
281 struct espi_reg *const inst = HAL_INSTANCE(dev);
282 uint32_t tmp = inst->FLASHCTL;
283
284 /*
285 * Clear FLASHCTL_FLASH_TX_AVAIL to avoid host puts a
286 * GET_FLASH_C command at here.
287 */
288 tmp &= NPCX_FLASHCTL_ACCESS_MASK;
289
290 /* Release FLASH_NP_FREE */
291 tmp |= BIT(NPCX_FLASHCTL_FLASH_NP_FREE);
292 inst->FLASHCTL = tmp;
293 }
294
taf_npcx_completion_handler(const struct device * dev,uint8_t type,uint8_t tag,uint16_t len,uint32_t * buffer)295 static int taf_npcx_completion_handler(const struct device *dev, uint8_t type, uint8_t tag,
296 uint16_t len, uint32_t *buffer)
297 {
298 struct espi_reg *const inst = HAL_INSTANCE(dev);
299 struct npcx_taf_head taf_head;
300 uint16_t i, size;
301 uint32_t tx_buf[16];
302
303 taf_head.pkt_len = NPCX_TAF_CMP_HEADER_LEN + len;
304 taf_head.type = type;
305 taf_head.tag_hlen = (tag << 4) | ((len & 0xF00) >> 8);
306 taf_head.llen = len & 0xFF;
307
308 memcpy(&tx_buf[0], &taf_head, sizeof(struct npcx_taf_head));
309
310 if (type == CYC_SCS_CMP_WITH_DATA_ONLY || type == CYC_SCS_CMP_WITH_DATA_FIRST ||
311 type == CYC_SCS_CMP_WITH_DATA_MIDDLE || type == CYC_SCS_CMP_WITH_DATA_LAST) {
312 memcpy(&tx_buf[1], buffer, (uint8_t)(len));
313 }
314
315 /* Check the Flash Access TX Queue is empty by polling
316 * FLASH_TX_AVAIL.
317 */
318 if (WAIT_FOR(!IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL),
319 NPCX_FLASH_CHK_TIMEOUT, NULL) == false) {
320 LOG_ERR("Check TX Queue Is Empty Timeout");
321 return -EBUSY;
322 }
323
324 /* Write packet to FLASHTXBUF */
325 size = DIV_ROUND_UP((uint8_t)(tx_buf[0]) + 1, sizeof(uint32_t));
326 for (i = 0; i < size; i++) {
327 inst->FLASHTXBUF[i] = tx_buf[i];
328 }
329
330 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
331 taf_set_flash_c_avail(dev);
332
333 /* Release FLASH_NP_FREE here to ready get next TAF request */
334 if ((type != CYC_SCS_CMP_WITH_DATA_FIRST) && (type != CYC_SCS_CMP_WITH_DATA_MIDDLE)) {
335 taf_release_flash_np_free(dev);
336 }
337
338 return 0;
339 }
340
341 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
espi_taf_npcx_flash_read(const struct device * dev,struct espi_saf_packet * pckt)342 static int espi_taf_npcx_flash_read(const struct device *dev, struct espi_saf_packet *pckt)
343 {
344 struct espi_reg *const inst = HAL_INSTANCE(dev);
345 struct espi_taf_npcx_config *config = ((struct espi_taf_npcx_config *)(dev)->config);
346 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
347 uint8_t cycle_type = CYC_SCS_CMP_WITH_DATA_ONLY;
348 uint32_t total_len = pckt->len;
349 uint32_t len = total_len;
350 uint32_t addr = pckt->flash_addr;
351 uint8_t flash_req_size = GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLASHREQSIZE);
352 uint8_t target_max_size = GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLREQSUP);
353 uint16_t max_read_req = 32 << flash_req_size;
354 int rc;
355
356 if (flash_req_size > target_max_size) {
357 LOG_DBG("Exceeded the maximum supported length");
358 if (target_max_size == 0) {
359 target_max_size = 1;
360 }
361 max_read_req = 32 << target_max_size;
362 }
363
364 if (total_len > max_read_req) {
365 LOG_ERR("Exceeded the limitation of read length");
366 return -EINVAL;
367 }
368
369 if (espi_taf_check_read_protect(dev, addr, len, taf_data_ptr->tag)) {
370 LOG_ERR("Access protect region");
371 return -EINVAL;
372 }
373
374 if (total_len <= config->rx_plsz) {
375 cycle_type = CYC_SCS_CMP_WITH_DATA_ONLY;
376 len = total_len;
377 } else {
378 cycle_type = CYC_SCS_CMP_WITH_DATA_FIRST;
379 len = config->rx_plsz;
380 }
381
382 do {
383 #if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
384 if ((addr + len) <= npcx_espi_taf_data.low_dev_size) {
385 rc = flash_read(npcx_espi_taf_data.low_dev_ptr, addr,
386 npcx_espi_taf_data.read_buf, len);
387 } else if (addr >= npcx_espi_taf_data.low_dev_size) {
388 rc = flash_read(npcx_espi_taf_data.high_dev_ptr,
389 (addr - npcx_espi_taf_data.low_dev_size),
390 npcx_espi_taf_data.read_buf, len);
391 } else {
392 rc = flash_read(npcx_espi_taf_data.low_dev_ptr, addr,
393 npcx_espi_taf_data.read_buf,
394 (npcx_espi_taf_data.low_dev_size.low_dev_size - addr));
395
396 if (rc) {
397 LOG_ERR("flash read fail 0x%x", rc);
398 return -EIO;
399 }
400
401 uint32_t index = low_dev_size - addr;
402
403 rc = flash_read(
404 npcx_espi_taf_data.high_dev_ptr, 0x0,
405 &npcx_espi_taf_data.read_buf[index],
406 (addr + len - npcx_espi_taf_data.low_dev_size.low_dev_size));
407 }
408 #else
409 rc = flash_read(spi_dev, addr, npcx_espi_taf_data.read_buf, len);
410 #endif
411 if (rc) {
412 LOG_ERR("flash read fail 0x%x", rc);
413 return -EIO;
414 }
415
416 rc = taf_npcx_completion_handler(dev, cycle_type, taf_data_ptr->tag, len,
417 (uint32_t *)npcx_espi_taf_data.read_buf);
418 if (rc) {
419 LOG_ERR("espi taf completion handler fail");
420 return rc;
421 }
422
423 total_len -= len;
424 addr += len;
425
426 if (total_len <= config->rx_plsz) {
427 cycle_type = CYC_SCS_CMP_WITH_DATA_LAST;
428 len = total_len;
429 } else {
430 cycle_type = CYC_SCS_CMP_WITH_DATA_MIDDLE;
431 }
432 } while (total_len);
433
434 return 0;
435 }
436 #endif
437
espi_taf_npcx_flash_write(const struct device * dev,struct espi_saf_packet * pckt)438 static int espi_taf_npcx_flash_write(const struct device *dev, struct espi_saf_packet *pckt)
439 {
440 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
441 uint8_t *data_ptr = (uint8_t *)(taf_data_ptr->data);
442 uint32_t addr = pckt->flash_addr;
443 uint32_t len = pckt->len;
444 int rc;
445
446 if (espi_taf_check_write_protect(dev, pckt->flash_addr,
447 pckt->len, taf_data_ptr->tag)) {
448 LOG_ERR("Access protection region");
449 return -EINVAL;
450 }
451
452 #if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
453 if ((addr + len) <= npcx_espi_taf_data.low_dev_size) {
454 rc = flash_write(npcx_espi_taf_data.low_dev_ptr, addr, data_ptr, len);
455 } else if (addr >= npcx_espi_taf_data.low_dev_size) {
456 rc = flash_write(npcx_espi_taf_data.high_dev_ptr,
457 (addr - npcx_espi_taf_data.low_dev_size), data_ptr, len);
458 } else {
459 LOG_ERR("Write across two flashes");
460 return -EINVAL;
461 }
462 #else
463 rc = flash_write(spi_dev, addr, data_ptr, len);
464 #endif
465 if (rc) {
466 LOG_ERR("flash write fail 0x%x", rc);
467 return -EIO;
468 }
469
470 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
471 NULL);
472 if (rc) {
473 LOG_ERR("espi taf completion handler fail");
474 return rc;
475 }
476
477 return 0;
478 }
479
espi_taf_npcx_flash_erase(const struct device * dev,struct espi_saf_packet * pckt)480 static int espi_taf_npcx_flash_erase(const struct device *dev, struct espi_saf_packet *pckt)
481 {
482 int erase_blk[] = {KB(4), KB(32), KB(64), KB(128)};
483 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
484 uint32_t addr = pckt->flash_addr;
485 uint32_t len;
486 int rc;
487
488 if ((pckt->len < 0) || (pckt->len >= NPCX_ESPI_TAF_ERASE_LEN_MAX)) {
489 LOG_ERR("Invalid erase block size");
490 return -EINVAL;
491 }
492
493 len = erase_blk[pckt->len];
494
495 if (espi_taf_check_write_protect(dev, addr, len, taf_data_ptr->tag)) {
496 LOG_ERR("Access protection region");
497 return -EINVAL;
498 }
499
500 #if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
501 if ((addr + len) <= npcx_espi_taf_data.low_dev_size) {
502 rc = flash_erase(npcx_espi_taf_data.low_dev_ptr, addr, len);
503 } else if (addr >= npcx_espi_taf_data.low_dev_size) {
504 rc = flash_erase(npcx_espi_taf_data.high_dev_ptr,
505 (addr - npcx_espi_taf_data.low_dev_size), len);
506 } else {
507 LOG_ERR("Erase across two flashes");
508 return -EINVAL;
509 }
510 #else
511 rc = flash_erase(spi_dev, addr, len);
512 #endif
513 if (rc) {
514 LOG_ERR("flash erase fail");
515 return -EIO;
516 }
517
518 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
519 NULL);
520 if (rc) {
521 LOG_ERR("espi taf completion handler fail");
522 return rc;
523 }
524
525 return 0;
526 }
527
528 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
espi_taf_npcx_rpmc_op1(const struct device * dev,struct espi_saf_packet * pckt)529 static int espi_taf_npcx_rpmc_op1(const struct device *dev, struct espi_saf_packet *pckt)
530 {
531 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
532 uint8_t *data_ptr = taf_data_ptr->data;
533 struct npcx_ex_ops_uma_in op_in = {
534 .opcode = ESPI_TAF_RPMC_OP1_CMD,
535 .tx_buf = data_ptr + 1,
536 .tx_count = (pckt->len) - 1,
537 .rx_count = 0,
538 };
539 int rc;
540
541 rc = flash_ex_op(spi_dev, FLASH_NPCX_EX_OP_EXEC_UMA, (uintptr_t)&op_in, NULL);
542 if (rc) {
543 LOG_ERR("flash RPMC OP1 fail");
544 return -EIO;
545 }
546
547 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
548 NULL);
549 if (rc) {
550 LOG_ERR("espi taf completion handler fail");
551 return rc;
552 }
553
554 return 0;
555 }
556
espi_taf_npcx_rpmc_op2(const struct device * dev,struct espi_saf_packet * pckt)557 static int espi_taf_npcx_rpmc_op2(const struct device *dev, struct espi_saf_packet *pckt)
558 {
559 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
560 uint8_t dummy_byte = 0;
561 struct npcx_ex_ops_uma_in op_in = {
562 .opcode = ESPI_TAF_RPMC_OP2_CMD,
563 .tx_buf = &dummy_byte,
564 .tx_count = 1,
565 .rx_count = pckt->len,
566 };
567 struct npcx_ex_ops_uma_out op_out = {
568 .rx_buf = npcx_espi_taf_data.read_buf,
569 };
570
571 int rc;
572
573 if (pckt->len > MAX_TX_PAYLOAD_SIZE) {
574 LOG_ERR("Invalid size");
575 return -EINVAL;
576 }
577
578 rc = flash_ex_op(spi_dev, FLASH_NPCX_EX_OP_EXEC_UMA, (uintptr_t)&op_in, &op_out);
579 if (rc) {
580 LOG_ERR("flash RPMC OP2 fail");
581 return -EIO;
582 }
583
584 rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITH_DATA_ONLY, taf_data_ptr->tag,
585 pckt->len, (uint32_t *)npcx_espi_taf_data.read_buf);
586 if (rc) {
587 LOG_ERR("espi taf completion handler fail");
588 return rc;
589 }
590
591 return 0;
592 }
593 #endif
594
espi_taf_npcx_flash_unsuccess(const struct device * dev,struct espi_saf_packet * pckt)595 static int espi_taf_npcx_flash_unsuccess(const struct device *dev, struct espi_saf_packet *pckt)
596 {
597 struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
598 int rc;
599
600 rc = taf_npcx_completion_handler(dev, CYC_UNSCS_CMP_WITHOUT_DATA_ONLY, taf_data_ptr->tag,
601 0x0, NULL);
602 if (rc) {
603 LOG_ERR("espi taf completion handler fail");
604 return rc;
605 }
606
607 return 0;
608 }
609
espi_taf_work(struct k_work * item)610 static void espi_taf_work(struct k_work *item)
611 {
612 struct espi_taf_npcx_data *info = CONTAINER_OF(item, struct espi_taf_npcx_data, work);
613 int ret = 0;
614
615 struct espi_taf_npcx_pckt taf_data;
616 struct espi_saf_packet pckt_taf;
617
618 pckt_taf.flash_addr = info->address;
619 pckt_taf.len = info->length;
620 taf_data.tag = info->taf_tag;
621 if ((info->taf_type == NPCX_ESPI_TAF_REQ_WRITE) ||
622 (IS_ENABLED(CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT) &&
623 (info->taf_type == NPCX_ESPI_TAF_REQ_RPMC_OP1))) {
624 taf_data.data = (uint8_t *)info->src;
625 } else {
626 taf_data.data = NULL;
627 }
628 pckt_taf.buf = (uint8_t *)&taf_data;
629
630 switch (info->taf_type) {
631 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
632 case NPCX_ESPI_TAF_REQ_READ:
633 ret = espi_taf_npcx_flash_read(info->host_dev, &pckt_taf);
634 break;
635 #endif
636 case NPCX_ESPI_TAF_REQ_ERASE:
637 ret = espi_taf_npcx_flash_erase(info->host_dev, &pckt_taf);
638 break;
639 case NPCX_ESPI_TAF_REQ_WRITE:
640 ret = espi_taf_npcx_flash_write(info->host_dev, &pckt_taf);
641 break;
642 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
643 case NPCX_ESPI_TAF_REQ_RPMC_OP1:
644 ret = espi_taf_npcx_rpmc_op1(info->host_dev, &pckt_taf);
645 break;
646 case NPCX_ESPI_TAF_REQ_RPMC_OP2:
647 ret = espi_taf_npcx_rpmc_op2(info->host_dev, &pckt_taf);
648 break;
649 #endif
650 }
651
652 if (ret != 0) {
653 ret = espi_taf_npcx_flash_unsuccess(info->host_dev, &pckt_taf);
654 }
655 }
656
espi_taf_event_handler(const struct device * dev,struct espi_callback * cb,struct espi_event event)657 static void espi_taf_event_handler(const struct device *dev, struct espi_callback *cb,
658 struct espi_event event)
659 {
660 if ((event.evt_type != ESPI_BUS_TAF_NOTIFICATION) ||
661 (event.evt_details != ESPI_CHANNEL_FLASH)) {
662 return;
663 }
664
665 espi_taf_get_pckt(dev, &npcx_espi_taf_data, event);
666 k_work_submit(&npcx_espi_taf_data.work);
667 }
668
espi_taf_npcx_block(const struct device * dev,bool en_block)669 int espi_taf_npcx_block(const struct device *dev, bool en_block)
670 {
671 struct espi_reg *const inst = HAL_INSTANCE(dev);
672
673 if (!IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_SAF_AUTO_READ)) {
674 return 0;
675 }
676
677 if (en_block) {
678 if (WAIT_FOR(!IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_FLAUTORDREQ),
679 CONFIG_ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT, NULL) == false) {
680 LOG_ERR("Check Automatic Read Queue Empty Timeout");
681 return -ETIMEDOUT;
682 }
683
684 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
685
686 if (WAIT_FOR(IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_AUTO_RD_DIS_STS),
687 CONFIG_ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT, NULL) == false) {
688 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
689 inst->ESPISTS |= BIT(NPCX_ESPISTS_AUTO_RD_DIS_STS);
690 LOG_ERR("Check Automatic Read Disable Timeout");
691 return -ETIMEDOUT;
692 }
693 } else {
694 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
695 inst->ESPISTS |= BIT(NPCX_ESPISTS_AUTO_RD_DIS_STS);
696 }
697
698 return 0;
699 }
700
npcx_init_taf(const struct device * dev,sys_slist_t * callbacks)701 int npcx_init_taf(const struct device *dev, sys_slist_t *callbacks)
702 {
703 espi_init_callback(&espi_taf_cb, espi_taf_event_handler, ESPI_BUS_TAF_NOTIFICATION);
704 espi_add_callback(dev, &espi_taf_cb);
705
706 npcx_espi_taf_data.host_dev = dev;
707 npcx_espi_taf_data.callbacks = callbacks;
708 k_work_init(&npcx_espi_taf_data.work, espi_taf_work);
709
710 return 0;
711 }
712
espi_taf_npcx_init(const struct device * dev)713 static int espi_taf_npcx_init(const struct device *dev)
714 {
715 struct espi_reg *const inst = HAL_INSTANCE(dev);
716 struct espi_taf_npcx_config *config = ((struct espi_taf_npcx_config *)(dev)->config);
717
718 SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLCAPA,
719 NPCX_FLASH_SHARING_CAP_SUPP_TAF_AND_CAF);
720 SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_TRGFLEBLKSIZE,
721 BIT(config->erase_sz));
722 SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLREQSUP,
723 config->max_rd_sz);
724 inst->FLASHBASE = config->mapped_addr;
725
726 #if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
727 if (IS_ENABLED(CONFIG_FLASH_NPCX_FIU_SUPP_LOW_DEV_SWAP)) {
728 npcx_espi_taf_data.low_dev_ptr = spi_dev1;
729 npcx_espi_taf_data.high_dev_ptr = spi_dev;
730 npcx_espi_taf_data.low_dev_size = NPCX_TAF_ALLOC_SIZE(NPCX_TAF_SEC_FLASH_NODE);
731 } else {
732 npcx_espi_taf_data.low_dev_ptr = spi_dev;
733 npcx_espi_taf_data.high_dev_ptr = spi_dev1;
734 npcx_espi_taf_data.low_dev_size = NPCX_TAF_ALLOC_SIZE(NPCX_TAF_PRIME_FLASH_NODE);
735 }
736 #endif
737
738 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
739 uint8_t count_num = 0;
740
741 /* RPMC_CFG1_CNTR is 0-based number, e.g. 0 indicates that 1 counter is supported, 1
742 * indicates 2 counters, etc.
743 */
744 if (config->rpmc_cnt_num > 0) {
745 count_num = config->rpmc_cnt_num - 1;
746 }
747
748 SET_FIELD(inst->FLASH_RPMC_CFG_1, NPCX_FLASH_RPMC_CFG1_CNTR, count_num);
749 SET_FIELD(inst->FLASH_RPMC_CFG_1, NPCX_FLASH_RPMC_CFG1_OP1, config->rpmc_op1_code);
750 SET_FIELD(inst->FLASH_RPMC_CFG_1, NPCX_FLASH_RPMC_CFG1_TRGRPMCSUP, config->rpmc_cnt_num);
751 #endif
752
753 return 0;
754 }
755
756 static DEVICE_API(espi_saf, espi_taf_npcx_driver_api) = {
757 .config = espi_taf_npcx_configure,
758 .set_protection_regions = espi_taf_npcx_set_pr,
759 .activate = espi_taf_npcx_activate,
760 .get_channel_status = espi_taf_npcx_channel_ready,
761 };
762
763 static const struct espi_taf_npcx_config espi_taf_npcx_config = {
764 .base = DT_INST_REG_ADDR(0),
765 .mapped_addr = DT_INST_PROP(0, mapped_addr),
766 .rx_plsz = DT_PROP(DT_INST_PARENT(0), rx_plsize),
767 .erase_sz = DT_INST_STRING_TOKEN(0, erase_sz),
768 .max_rd_sz = DT_INST_STRING_TOKEN(0, max_read_sz),
769 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
770 .rpmc_cnt_num = DT_INST_PROP(0, rpmc_cntr),
771 .rpmc_op1_code = DT_INST_PROP(0, rpmc_op1_code),
772 #endif
773 };
774
775 DEVICE_DT_INST_DEFINE(0, &espi_taf_npcx_init, NULL,
776 &npcx_espi_taf_data, &espi_taf_npcx_config,
777 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
778 &espi_taf_npcx_driver_api);
779
