1/*
2 * Copyright (c) 2023 Andes Technology Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <mem.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18		cpu0: cpu@0 {
19			compatible = "andestech,andescore-v5", "riscv";
20			device_type = "cpu";
21			reg = <0>;
22			status = "okay";
23			riscv,isa = "rv32gc_xandes";
24			mmu-type = "riscv,sv32";
25			clock-frequency = <60000000>;
26			i-cache-line-size = <32>;
27			d-cache-line-size = <32>;
28			cpu0_intc: interrupt-controller {
29				compatible = "riscv,cpu-intc";
30				#address-cells = <0>;
31				#interrupt-cells = <1>;
32				interrupt-controller;
33			};
34		};
35		cpu1: cpu@1 {
36			compatible = "andestech,andescore-v5", "riscv";
37			device_type = "cpu";
38			reg = <1>;
39			status = "okay";
40			riscv,isa = "rv32gc_xandes";
41			mmu-type = "riscv,sv32";
42			clock-frequency = <60000000>;
43			i-cache-line-size = <32>;
44			d-cache-line-size = <32>;
45			cpu1_intc: interrupt-controller {
46				compatible = "riscv,cpu-intc";
47				#address-cells = <0>;
48				#interrupt-cells = <1>;
49				interrupt-controller;
50			};
51		};
52		cpu2: cpu@2 {
53			compatible = "andestech,andescore-v5", "riscv";
54			device_type = "cpu";
55			reg = <2>;
56			status = "okay";
57			riscv,isa = "rv32gc_xandes";
58			mmu-type = "riscv,sv32";
59			clock-frequency = <60000000>;
60			i-cache-line-size = <32>;
61			d-cache-line-size = <32>;
62			cpu2_intc: interrupt-controller {
63				compatible = "riscv,cpu-intc";
64				#address-cells = <0>;
65				#interrupt-cells = <1>;
66				interrupt-controller;
67			};
68		};
69		cpu3: cpu@3 {
70			compatible = "andestech,andescore-v5", "riscv";
71			device_type = "cpu";
72			reg = <3>;
73			status = "okay";
74			riscv,isa = "rv32gc_xandes";
75			mmu-type = "riscv,sv32";
76			clock-frequency = <60000000>;
77			i-cache-line-size = <32>;
78			d-cache-line-size = <32>;
79			cpu3_intc: interrupt-controller {
80				compatible = "riscv,cpu-intc";
81				#address-cells = <0>;
82				#interrupt-cells = <1>;
83				interrupt-controller;
84			};
85		};
86		cpu4: cpu@4 {
87			compatible = "andestech,andescore-v5", "riscv";
88			device_type = "cpu";
89			reg = <4>;
90			status = "okay";
91			riscv,isa = "rv32gc_xandes";
92			mmu-type = "riscv,sv32";
93			clock-frequency = <60000000>;
94			i-cache-line-size = <32>;
95			d-cache-line-size = <32>;
96			cpu4_intc: interrupt-controller {
97				compatible = "riscv,cpu-intc";
98				#address-cells = <0>;
99				#interrupt-cells = <1>;
100				interrupt-controller;
101			};
102		};
103		cpu5: cpu@5 {
104			compatible = "andestech,andescore-v5", "riscv";
105			device_type = "cpu";
106			reg = <5>;
107			status = "okay";
108			riscv,isa = "rv32gc_xandes";
109			mmu-type = "riscv,sv32";
110			clock-frequency = <60000000>;
111			i-cache-line-size = <32>;
112			d-cache-line-size = <32>;
113			cpu5_intc: interrupt-controller {
114				compatible = "riscv,cpu-intc";
115				#address-cells = <0>;
116				#interrupt-cells = <1>;
117				interrupt-controller;
118			};
119		};
120		cpu6: cpu@6 {
121			compatible = "andestech,andescore-v5", "riscv";
122			device_type = "cpu";
123			reg = <6>;
124			status = "okay";
125			riscv,isa = "rv32gc_xandes";
126			mmu-type = "riscv,sv32";
127			clock-frequency = <60000000>;
128			i-cache-line-size = <32>;
129			d-cache-line-size = <32>;
130			cpu6_intc: interrupt-controller {
131				compatible = "riscv,cpu-intc";
132				#address-cells = <0>;
133				#interrupt-cells = <1>;
134				interrupt-controller;
135			};
136		};
137		cpu7: cpu@7 {
138			compatible = "andestech,andescore-v5", "riscv";
139			device_type = "cpu";
140			reg = <7>;
141			status = "okay";
142			riscv,isa = "rv32gc_xandes";
143			mmu-type = "riscv,sv32";
144			clock-frequency = <60000000>;
145			i-cache-line-size = <32>;
146			d-cache-line-size = <32>;
147			cpu7_intc: interrupt-controller {
148				compatible = "riscv,cpu-intc";
149				#address-cells = <0>;
150				#interrupt-cells = <1>;
151				interrupt-controller;
152			};
153		};
154	};
155
156	dram: memory@0 {
157		device_type = "memory";
158		compatible = "mmio-sram";
159		reg = <0x00000000 0x40000000>;
160	};
161
162	soc {
163		#address-cells = <1>;
164		#size-cells = <1>;
165		compatible = "andestech,ae350";
166		ranges;
167
168		plic0: interrupt-controller@e4000000 {
169			compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
170			#address-cells = <1>;
171			#interrupt-cells = <2>;
172			interrupt-controller;
173			reg = <0xe4000000 0x04000000>;
174			riscv,max-priority = <255>;
175			riscv,ndev = <1023>;
176			interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11
177					       &cpu2_intc 11 &cpu3_intc 11
178					       &cpu4_intc 11 &cpu5_intc 11
179					       &cpu6_intc 11 &cpu7_intc 11>;
180		};
181
182		mbox: mbox-controller@e6400000 {
183			compatible = "andestech,plic-sw";
184			reg = <0xe6400000 0x00400000>;
185			#mbox-cells = <1>;
186			channel-max = <30>;
187			status = "okay";
188		};
189
190		mtimer: timer@e6000000 {
191			compatible = "andestech,machine-timer";
192			reg = <0xe6000000 0x10>;
193			interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
194					       &cpu2_intc 7 &cpu3_intc 7
195					       &cpu4_intc 7 &cpu5_intc 7
196					       &cpu6_intc 7 &cpu7_intc 7>;
197		};
198
199		syscon: syscon@f0100000 {
200			compatible = "syscon", "andestech,atcsmu100";
201			reg = <0xf0100000 0x1000>;
202			status = "disabled";
203		};
204
205		l2_cache: cache-controller@e0500000 {
206			compatible = "andestech,l2c";
207			reg = <0xe0500000 0x1000>;
208			status = "disabled";
209		};
210
211		uart0: serial@f0200020 {
212			compatible = "ns16550";
213			reg = <0xf0200020 0x1000>;
214			reg-shift = <2>;
215			interrupts = <8 1>;
216			interrupt-parent = <&plic0>;
217			status = "disabled";
218		};
219
220		uart1: serial@f0300020 {
221			compatible = "ns16550";
222			reg = <0xf0300020 0x1000>;
223			reg-shift = <2>;
224			interrupts = <9 1>;
225			interrupt-parent = <&plic0>;
226			status = "disabled";
227		};
228
229		pit0: pit@f0400000 {
230			compatible = "andestech,atcpit100";
231			reg = <0xf0400000 0x1000>;
232			interrupts = <3 1>;
233			interrupt-parent = <&plic0>;
234			clock-frequency = <60000000>;
235			prescaler = <600>;
236			status = "disabled";
237		};
238
239		rtc0: rtc@f0600000 {
240			compatible = "andestech,atcrtc100";
241			reg = <0xf0600000 0x1000>;
242			interrupts = <1 1>, <2 1>;
243			interrupt-parent = <&plic0>;
244			wakeup-source;
245			status = "disabled";
246		};
247
248		gpio0: gpio@f0700000 {
249			compatible = "andestech,atcgpio100";
250			reg = <0xf0700000 0x1000>;
251			interrupts = <7 1>;
252			interrupt-parent = <&plic0>;
253			gpio-controller;
254			ngpios = <32>;
255			#gpio-cells = <2>;
256			status = "disabled";
257		};
258
259		i2c0: i2c@f0a00000 {
260			compatible = "andestech,atciic100";
261			reg = <0xf0a00000 0x1000>;
262			interrupts = <6 1>;
263			interrupt-parent = <&plic0>;
264			#address-cells = <1>;
265			#size-cells = <0>;
266			status = "disabled";
267		};
268
269		spi0: spi@f0b00000 {
270			compatible = "andestech,atcspi200";
271			reg = <0xf0b00000 0x1000
272			       0x80000000 DT_SIZE_K(1024)>;
273			reg-names = "control", "mem";
274			interrupts = <4 1>;
275			interrupt-parent = <&plic0>;
276			dmas = <&dma0 0 0 0x009>,
277			       <&dma0 1 1 0x00A>;
278			dma-names = "tx", "rx";
279			#address-cells = <1>;
280			#size-cells = <0>;
281			clock-frequency = <66000000>;
282			status = "disabled";
283		};
284
285		spi1: spi@f0f00000 {
286			compatible = "andestech,atcspi200";
287			reg = <0xf0f00000 0x1000>;
288			reg-names = "control";
289			interrupts = <5 1>;
290			interrupt-parent = <&plic0>;
291			dmas = <&dma0 2 2 0x009>,
292			       <&dma0 3 3 0x00A>;
293			dma-names = "tx", "rx";
294			#address-cells = <1>;
295			#size-cells = <0>;
296			clock-frequency = <66000000>;
297			status = "disabled";
298		};
299
300		dma0: dma@f0c00000 {
301			compatible = "andestech,atcdmac300";
302			reg = <0xf0c00000 0x1000>;
303			interrupts = <10 1>;
304			interrupt-parent = <&plic0>;
305			dma-channels = <8>;
306			dma-requests = <16>;
307			chain-transfer = <1>;
308			#dma-cells = <3>;
309			status = "disabled";
310		};
311
312		eth0: eth@e0100000 {
313			compatible = "andestech,atfmac100";
314			reg = <0xe0100000 0x1000>;
315			interrupts = <19 2>;
316			interrupt-parent = <&plic0>;
317			local-mac-address = [FC 8C EB 9B A6 51];
318			status = "disabled";
319		};
320
321		lcd0: lcd@e0200000 {
322			compatible = "andestech,atflcdc100";
323			reg = <0xe0200000 0x1000>;
324			interrupts = <20 1>;
325			interrupt-parent = <&plic0>;
326			clock-frequency = <30000000>;
327			status = "disabled";
328		};
329
330		wdt: wdt@f0500000 {
331			compatible = "andestech,atcwdt200";
332			reg = <0xf0500000 0x1000>;
333			interrupts = <20 1>;
334			interrupt-parent = <&plic0>;
335			status = "disabled";
336		};
337
338		smc0: smc@e0400000 {
339			compatible = "andestech,atfsmc020";
340			reg = <0xe0400000 0x1000>;
341			status = "disabled";
342		};
343
344		snd0: snd@f0d00000 {
345			compatible = "andestech,atfac97";
346			reg = <0xf0d00000 0x1000>;
347			interrupts = <17 1>;
348			interrupt-parent = <&plic0>;
349			status = "disabled";
350		};
351
352		mmc0: mmc@f0e00000 {
353			compatible = "andestech,atfsdc010";
354			reg = <0xf0e00000 0x1000>;
355			interrupts = <18 1>;
356			interrupt-parent = <&plic0>;
357			cap-sd-highspeed;
358			max-frequency = <100000000>;
359			clock-freq-min-max = <400000 100000000>;
360			fifo-depth = <0x10>;
361			status = "disabled";
362		};
363	};
364};
365