1 /*
2 * Copyright 2022,2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT zephyr_sdhc_spi_slot
8
9
10
11 #include <zephyr/drivers/sdhc.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/sys/byteorder.h>
15 #include <zephyr/drivers/spi.h>
16 #include <zephyr/sys/crc.h>
17 #include <zephyr/pm/device_runtime.h>
18
19 LOG_MODULE_REGISTER(sdhc_spi, CONFIG_SDHC_LOG_LEVEL);
20
21 #define MAX_CMD_READ 21
22 #define SPI_R1B_TIMEOUT_MS 3000
23 #define SD_SPI_SKIP_RETRIES 1000000
24
25 #define _INST_REQUIRES_EXPLICIT_FF(inst) (SPI_MOSI_OVERRUN_DT(DT_INST_BUS(inst)) != 0xFF) ||
26
27 /* The SD protocol requires sending ones while reading but the Zephyr
28 * SPI API defers the choice of default values to the drivers.
29 *
30 * For drivers that we know will send ones we can avoid allocating a
31 * 512 byte array of ones and remove the limit on the number of bytes
32 * that can be read in a single transaction.
33 */
34 #define ANY_INST_REQUIRES_EXPLICIT_FF DT_INST_FOREACH_STATUS_OKAY(_INST_REQUIRES_EXPLICIT_FF) 0
35
36 #if ANY_INST_REQUIRES_EXPLICIT_FF
37
38 static const uint8_t sdhc_ones[] = {
39 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
40 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
41 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
42 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
43 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
44 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
45 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
46 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
47 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
48 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
49 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
50 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
51 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
52 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
53 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
54 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
55 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
56 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
57 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
58 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
59 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
60 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
61 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
62 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
63 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
64 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
65 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
66 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
67 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
68 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
69 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
70 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
71 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
72 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
73 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
74 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
75 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
76 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
77 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
78 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
79 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
80 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
81 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
82 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
83 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
84 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
85 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
86 };
87
88 BUILD_ASSERT(sizeof(sdhc_ones) == 512, "0xFF array for SDHC must be 512 bytes");
89
90 #endif /* ANY_INST_REQUIRES_EXPLICIT_FF */
91
92 struct sdhc_spi_config {
93 const struct device *spi_dev;
94 const struct gpio_dt_spec pwr_gpio;
95 const uint32_t spi_max_freq;
96 uint32_t power_delay_ms;
97 };
98
99 struct sdhc_spi_data {
100 enum sdhc_power power_mode;
101 struct spi_config *spi_cfg;
102 struct spi_config cfg_a;
103 struct spi_config cfg_b;
104 uint8_t scratch[MAX_CMD_READ];
105 };
106
107 /* Receives a block of bytes */
sdhc_spi_rx(const struct device * spi_dev,struct spi_config * spi_cfg,uint8_t * buf,int len)108 static int sdhc_spi_rx(const struct device *spi_dev, struct spi_config *spi_cfg,
109 uint8_t *buf, int len)
110 {
111 #if ANY_INST_REQUIRES_EXPLICIT_FF
112 struct spi_buf tx_bufs[] = {
113 {
114 .buf = (uint8_t *)sdhc_ones,
115 .len = len
116 }
117 };
118
119 const struct spi_buf_set tx = {
120 .buffers = tx_bufs,
121 .count = 1,
122 };
123 const struct spi_buf_set *tx_ptr = &tx;
124 #else
125 const struct spi_buf_set *tx_ptr = NULL;
126 #endif /* ANY_INST_REQUIRES_EXPLICIT_FF */
127
128 struct spi_buf rx_bufs[] = {
129 {
130 .buf = buf,
131 .len = len
132 }
133 };
134
135 const struct spi_buf_set rx = {
136 .buffers = rx_bufs,
137 .count = 1,
138 };
139
140 return spi_transceive(spi_dev, spi_cfg, tx_ptr, &rx);
141 }
142
sdhc_spi_init_card(const struct device * dev)143 static int sdhc_spi_init_card(const struct device *dev)
144 {
145 /* SD spec requires at least 74 clocks be send to SD to start it.
146 * for SPI protocol, this will be performed by sending 10 0xff values
147 * to the card (this should result in 80 SCK cycles)
148 */
149 const struct sdhc_spi_config *config = dev->config;
150 struct sdhc_spi_data *data = dev->data;
151 struct spi_config *spi_cfg = data->spi_cfg;
152 int ret, ret2;
153
154 if (spi_cfg->frequency == 0) {
155 /* Use default 400KHZ frequency */
156 spi_cfg->frequency = SDMMC_CLOCK_400KHZ;
157 }
158
159 /* Request SPI bus to be active */
160 if (pm_device_runtime_get(config->spi_dev) < 0) {
161 return -EIO;
162 }
163
164 /* the initial 74 clocks must be sent while CS is high */
165 spi_cfg->operation |= SPI_CS_ACTIVE_HIGH;
166 ret = sdhc_spi_rx(config->spi_dev, spi_cfg, data->scratch, 10);
167
168 /* Release lock on SPI bus */
169 ret2 = spi_release(config->spi_dev, spi_cfg);
170 spi_cfg->operation &= ~SPI_CS_ACTIVE_HIGH;
171
172 /* Release request for SPI bus to be active */
173 (void)pm_device_runtime_put(config->spi_dev);
174
175 return ret ? ret : ret2;
176 }
177
178 /* Checks if SPI SD card is sending busy signal */
sdhc_spi_card_busy(const struct device * dev)179 static int sdhc_spi_card_busy(const struct device *dev)
180 {
181 const struct sdhc_spi_config *config = dev->config;
182 struct sdhc_spi_data *data = dev->data;
183 int ret;
184 uint8_t response;
185
186 /* Request SPI bus to be active */
187 if (pm_device_runtime_get(config->spi_dev) < 0) {
188 return -EIO;
189 }
190
191 ret = sdhc_spi_rx(config->spi_dev, data->spi_cfg, &response, 1);
192 (void)pm_device_runtime_put(config->spi_dev);
193 if (ret) {
194 return -EIO;
195 }
196
197 if (response == 0xFF) {
198 return 0;
199 } else {
200 return 1;
201 }
202 }
203
204 /* Waits for SPI SD card to stop sending busy signal */
sdhc_spi_wait_unbusy(const struct device * dev,int timeout_ms,int interval_ticks)205 static int sdhc_spi_wait_unbusy(const struct device *dev,
206 int timeout_ms,
207 int interval_ticks)
208 {
209 const struct sdhc_spi_config *config = dev->config;
210 struct sdhc_spi_data *data = dev->data;
211 int ret;
212 uint8_t response;
213
214 while (timeout_ms > 0) {
215 ret = sdhc_spi_rx(config->spi_dev, data->spi_cfg, &response, 1);
216 if (ret) {
217 return ret;
218 }
219 if (response == 0xFF) {
220 return 0;
221 }
222 k_msleep(k_ticks_to_ms_floor32(interval_ticks));
223 timeout_ms -= k_ticks_to_ms_floor32(interval_ticks);
224 }
225 return -ETIMEDOUT;
226 }
227
228
229 /* Read SD command from SPI response */
sdhc_spi_response_get(const struct device * dev,struct sdhc_command * cmd,int rx_len)230 static int sdhc_spi_response_get(const struct device *dev, struct sdhc_command *cmd,
231 int rx_len)
232 {
233 const struct sdhc_spi_config *config = dev->config;
234 struct sdhc_spi_data *dev_data = dev->data;
235 uint8_t *response = dev_data->scratch;
236 uint8_t *end = response + rx_len;
237 int ret, timeout = cmd->timeout_ms;
238 uint8_t value, i;
239
240 /* First step is finding the first valid byte of the response.
241 * All SPI responses start with R1, which will have MSB of zero.
242 * we know we can ignore the first 7 bytes, which hold the command and
243 * initial "card ready" byte.
244 */
245 response += 8;
246 while (response < end && ((*response & SD_SPI_START) == SD_SPI_START)) {
247 response++;
248 }
249 if (response == end) {
250 /* Some cards are slow, and need more time to respond. Continue
251 * with single byte reads until the card responds.
252 */
253 response = dev_data->scratch;
254 end = response + 1;
255 while (timeout > 0) {
256 ret = sdhc_spi_rx(config->spi_dev, dev_data->spi_cfg,
257 response, 1);
258 if (ret < 0) {
259 return ret;
260 }
261 if (*response != 0xff) {
262 break;
263 }
264 /* Delay for a bit, and poll the card again */
265 k_msleep(10);
266 timeout -= 10;
267 }
268 if (*response == 0xff) {
269 return -ETIMEDOUT;
270 }
271 }
272 /* Record R1 response */
273 cmd->response[0] = *response++;
274 /* Check response for error */
275 if (cmd->response[0] != 0) {
276 if (cmd->response[0] & (SD_SPI_R1PARAMETER_ERR | SD_SPI_R1ADDRESS_ERR)) {
277 return -EFAULT; /* Bad address */
278 } else if (cmd->response[0] & (SD_SPI_R1ILLEGAL_CMD_ERR)) {
279 return -EINVAL; /* Invalid command */
280 } else if (cmd->response[0] & (SD_SPI_R1CMD_CRC_ERR)) {
281 return -EILSEQ; /* Illegal byte sequence */
282 } else if (cmd->response[0] & (SD_SPI_R1ERASE_SEQ_ERR | SD_SPI_R1ERASE_RESET)) {
283 return -EIO;
284 }
285 /* else IDLE_STATE bit is set, which is not an error, card is just resetting */
286 }
287 switch ((cmd->response_type & SDHC_SPI_RESPONSE_TYPE_MASK)) {
288 case SD_SPI_RSP_TYPE_R1:
289 /* R1 response - one byte*/
290 break;
291 case SD_SPI_RSP_TYPE_R1b:
292 /* R1b response - one byte plus busy signal */
293 /* Read remaining bytes to see if card is still busy.
294 * card will be ready when it stops driving data out
295 * low.
296 */
297 while (response < end && (*response == 0x0)) {
298 response++;
299 }
300 if (response == end) {
301 value = cmd->timeout_ms;
302 response--;
303 /* Periodically check busy line */
304 ret = sdhc_spi_wait_unbusy(dev,
305 SPI_R1B_TIMEOUT_MS, 1000);
306 }
307 break;
308 case SD_SPI_RSP_TYPE_R2:
309 case SD_SPI_RSP_TYPE_R5:
310 /* R2/R5 response - R1 response + 1 byte*/
311 if (response == end) {
312 response = dev_data->scratch;
313 end = response + 1;
314 /* Read the next byte */
315 ret = sdhc_spi_rx(config->spi_dev,
316 dev_data->spi_cfg,
317 response, 1);
318 if (ret) {
319 return ret;
320 }
321 }
322 cmd->response[0] = (*response) << 8;
323 break;
324 case SD_SPI_RSP_TYPE_R3:
325 case SD_SPI_RSP_TYPE_R4:
326 case SD_SPI_RSP_TYPE_R7:
327 /* R3/R4/R7 response - R1 response + 4 bytes */
328 cmd->response[1] = 0;
329 for (i = 0; i < 4; i++) {
330 cmd->response[1] <<= 8;
331 /* Read bytes of response */
332 if (response == end) {
333 response = dev_data->scratch;
334 end = response + 1;
335 /* Read the next byte */
336 ret = sdhc_spi_rx(config->spi_dev,
337 dev_data->spi_cfg,
338 response, 1);
339 if (ret) {
340 return ret;
341 }
342 }
343 cmd->response[1] |= *response++;
344 }
345 break;
346 default:
347 /* Other RSP types not supported */
348 return -ENOTSUP;
349 }
350 return 0;
351 }
352
353 /* Send SD command using SPI */
sdhc_spi_send_cmd(const struct device * dev,struct sdhc_command * cmd,bool data_present)354 static int sdhc_spi_send_cmd(const struct device *dev, struct sdhc_command *cmd,
355 bool data_present)
356 {
357 const struct sdhc_spi_config *config = dev->config;
358 struct sdhc_spi_data *dev_data = dev->data;
359 int err;
360 uint8_t *cmd_buf;
361 /* To reduce overhead, we will send entire command in one SPI
362 * transaction. The packet takes the following format:
363 * - all ones byte to ensure card is ready
364 * - opcode byte (which includes start and transmission bits)
365 * - 4 bytes for argument
366 * - crc7 byte (with end bit)
367 * The SD card can take up to 8 bytes worth of SCLK cycles to respond.
368 * therefore, we provide 8 bytes of all ones, to read data from the card.
369 * the maximum spi response length is 5 bytes, so we provide an
370 * additional 5 bytes of data, leaving us with 13 bytes of 0xff.
371 * Finally, we send a padding byte of all 0xff, to ensure that
372 * the card recives at least one 0xff byte before next command.
373 */
374
375 /* Note: we can discard CMD data as we send it,
376 * so resuse the TX buf as RX
377 */
378 struct spi_buf bufs[] = {
379 {
380 .buf = dev_data->scratch,
381 .len = sizeof(dev_data->scratch),
382 },
383 };
384
385 const struct spi_buf_set buf_set = {
386 .buffers = bufs,
387 .count = 1,
388 };
389
390
391 if (data_present) {
392 /* We cannot send extra SCLK cycles with our command,
393 * since we'll miss the data the card responds with. We
394 * send one 0xff byte, six command bytes, two additional 0xff
395 * bytes, since the min value of NCR (see SD SPI timing
396 * diagrams) is one, and we know there will be an R1 response.
397 */
398 bufs[0].len = SD_SPI_CMD_SIZE + 3;
399 }
400 memset(dev_data->scratch, 0xFF, sizeof(dev_data->scratch));
401 cmd_buf = dev_data->scratch + 1;
402
403 /* Command packet holds the following bits:
404 * [47]: start bit, 0b0
405 * [46]: transmission bit, 0b1
406 * [45-40]: command index
407 * [39-8]: argument
408 * [7-1]: CRC
409 * [0]: end bit, 0b1
410 * Note that packets are sent MSB first.
411 */
412 /* Add start bit, tx bit, and cmd opcode */
413 cmd_buf[0] = (cmd->opcode & SD_SPI_CMD);
414 cmd_buf[0] = ((cmd_buf[0] | SD_SPI_TX) & ~SD_SPI_START);
415 /* Add argument */
416 sys_put_be32(cmd->arg, &cmd_buf[1]);
417 /* Add CRC, and set LSB as the end bit */
418 cmd_buf[SD_SPI_CMD_BODY_SIZE] = crc7_be(0, cmd_buf, SD_SPI_CMD_BODY_SIZE) | 0x1;
419 LOG_DBG("cmd%d arg 0x%x", cmd->opcode, cmd->arg);
420 /* Set data, will lock SPI bus */
421 err = spi_transceive(config->spi_dev, dev_data->spi_cfg, &buf_set, &buf_set);
422 if (err != 0) {
423 return err;
424 }
425 /* Read command response */
426 return sdhc_spi_response_get(dev, cmd, bufs[0].len);
427 }
428
429 /* Skips bytes in SDHC data stream. */
sdhc_skip(const struct device * dev,uint8_t skip_val)430 static int sdhc_skip(const struct device *dev, uint8_t skip_val)
431 {
432 const struct sdhc_spi_config *config = dev->config;
433 struct sdhc_spi_data *data = dev->data;
434 uint8_t buf;
435 int ret;
436 uint32_t retries = SD_SPI_SKIP_RETRIES;
437
438 do {
439 ret = sdhc_spi_rx(config->spi_dev, data->spi_cfg,
440 &buf, sizeof(buf));
441 if (ret) {
442 return ret;
443 }
444 } while (buf == skip_val && retries--);
445 if (retries == 0) {
446 return -ETIMEDOUT;
447 }
448 /* Return first non-skipped value */
449 return buf;
450 }
451
452 /* Handles reading data from SD SPI device */
sdhc_spi_read_data(const struct device * dev,struct sdhc_data * data)453 static int sdhc_spi_read_data(const struct device *dev, struct sdhc_data *data)
454 {
455 const struct sdhc_spi_config *config = dev->config;
456 struct sdhc_spi_data *dev_data = dev->data;
457 uint8_t *read_location = data->data;
458 uint32_t remaining = data->blocks;
459 int ret;
460 uint8_t crc[SD_SPI_CRC16_SIZE + 1];
461
462 #if ANY_INST_REQUIRES_EXPLICIT_FF
463 /* If the driver requires explicit 0xFF bytes on receive, we
464 * are limited to receiving the size of the sdhc_ones buffer
465 */
466 if (data->block_size > sizeof(sdhc_ones)) {
467 return -ENOTSUP;
468 }
469
470 const struct spi_buf tx_bufs[] = {
471 {
472 .buf = (uint8_t *)sdhc_ones,
473 .len = data->block_size,
474 },
475 };
476
477 const struct spi_buf_set tx = {
478 .buffers = tx_bufs,
479 .count = 1,
480 };
481 const struct spi_buf_set *tx_ptr = &tx;
482 #else
483 const struct spi_buf_set *tx_ptr = NULL;
484 #endif /* ANY_INST_REQUIRES_EXPLICIT_FF */
485
486 struct spi_buf rx_bufs[] = {
487 {
488 .buf = read_location,
489 .len = data->block_size,
490 }
491 };
492
493 const struct spi_buf_set rx = {
494 .buffers = rx_bufs,
495 .count = 1,
496 };
497
498
499 /* Read bytes until data stream starts. SD will send 0xff until
500 * data is available
501 */
502 ret = sdhc_skip(dev, 0xff);
503 if (ret < 0) {
504 return ret;
505 }
506 /* Check token */
507 if (ret != SD_SPI_TOKEN_SINGLE) {
508 return -EIO;
509 }
510
511 /* Read blocks until we are out of data */
512 while (remaining--) {
513 ret = spi_transceive(config->spi_dev,
514 dev_data->spi_cfg, tx_ptr, &rx);
515 if (ret) {
516 LOG_ERR("Data write failed");
517 return ret;
518 }
519 /* Read CRC16 plus one end byte */
520 ret = sdhc_spi_rx(config->spi_dev, dev_data->spi_cfg,
521 crc, sizeof(crc));
522 if (crc16_itu_t(0, read_location, data->block_size) !=
523 sys_get_be16(crc)) {
524 /* Bad CRC */
525 LOG_ERR("Bad data CRC");
526 return -EILSEQ;
527 }
528 /* Advance read location */
529 read_location += data->block_size;
530 rx_bufs[0].buf = read_location;
531 if (remaining) {
532 /* Check next data token */
533 ret = sdhc_skip(dev, 0xff);
534 if (ret != SD_SPI_TOKEN_SINGLE) {
535 LOG_ERR("Bad token");
536 return -EIO;
537 }
538 }
539 }
540 return ret;
541 }
542
543 /* Handles writing data to SD SPI device */
sdhc_spi_write_data(const struct device * dev,struct sdhc_data * data)544 static int sdhc_spi_write_data(const struct device *dev, struct sdhc_data *data)
545 {
546 const struct sdhc_spi_config *config = dev->config;
547 struct sdhc_spi_data *dev_data = dev->data;
548 int ret;
549 uint8_t token, resp;
550 uint8_t *write_location = data->data, crc[SD_SPI_CRC16_SIZE];
551 uint32_t remaining = data->blocks;
552
553 struct spi_buf tx_bufs[] = {
554 {
555 .buf = &token,
556 .len = sizeof(uint8_t),
557 },
558 {
559 .buf = write_location,
560 .len = data->block_size,
561 },
562 {
563 .buf = crc,
564 .len = sizeof(crc),
565 },
566 };
567
568 struct spi_buf_set tx = {
569 .buffers = tx_bufs,
570 .count = 3,
571 };
572
573 /* Set the token- single block reads use different token
574 * than multibock
575 */
576 if (remaining > 1) {
577 token = SD_SPI_TOKEN_MULTI_WRITE;
578 } else {
579 token = SD_SPI_TOKEN_SINGLE;
580 }
581
582 while (remaining--) {
583 /* Build the CRC for this data block */
584 sys_put_be16(crc16_itu_t(0, write_location, data->block_size),
585 crc);
586 ret = spi_write(config->spi_dev, dev_data->spi_cfg, &tx);
587 if (ret) {
588 return ret;
589 }
590 /* Read back the data response token from the card */
591 ret = sdhc_spi_rx(config->spi_dev, dev_data->spi_cfg,
592 &resp, sizeof(resp));
593 if (ret) {
594 return ret;
595 }
596 /* Check response token */
597 if ((resp & 0xF) != SD_SPI_RESPONSE_ACCEPTED) {
598 if ((resp & 0xF) == SD_SPI_RESPONSE_CRC_ERR) {
599 return -EILSEQ;
600 } else if ((resp & 0xF) == SD_SPI_RESPONSE_WRITE_ERR) {
601 return -EIO;
602 }
603 LOG_DBG("Unknown write response token 0x%x", resp);
604 return -EIO;
605 }
606 /* Advance write location */
607 write_location += data->block_size;
608 tx_bufs[1].buf = write_location;
609 /* Wait for card to stop being busy */
610 ret = sdhc_spi_wait_unbusy(dev, data->timeout_ms, 0);
611 if (ret) {
612 return ret;
613 }
614 }
615 if (data->blocks > 1) {
616 /* Write stop transfer token to card */
617 token = SD_SPI_TOKEN_STOP_TRAN;
618 tx.count = 1;
619 ret = spi_write(config->spi_dev, dev_data->spi_cfg, &tx);
620 if (ret) {
621 return ret;
622 }
623 /* Wait for card to stop being busy */
624 ret = sdhc_spi_wait_unbusy(dev, data->timeout_ms, 0);
625 if (ret) {
626 return ret;
627 }
628 }
629 return 0;
630 }
631
sdhc_spi_request(const struct device * dev,struct sdhc_command * cmd,struct sdhc_data * data)632 static int sdhc_spi_request(const struct device *dev,
633 struct sdhc_command *cmd,
634 struct sdhc_data *data)
635 {
636 const struct sdhc_spi_config *config = dev->config;
637 struct sdhc_spi_data *dev_data = dev->data;
638 int ret, ret2, stop_ret, retries = cmd->retries;
639 const struct sdhc_command stop_cmd = {
640 .opcode = SD_STOP_TRANSMISSION,
641 .arg = 0,
642 .response_type = SD_SPI_RSP_TYPE_R1b,
643 .timeout_ms = 1000,
644 .retries = 1,
645 };
646
647 /* Request SPI bus to be active */
648 if (pm_device_runtime_get(config->spi_dev) < 0) {
649 return -EIO;
650 }
651
652 if (data == NULL) {
653 do {
654 ret = sdhc_spi_send_cmd(dev, cmd, false);
655 } while ((ret != 0) && (retries-- > 0));
656 } else {
657 do {
658 retries--;
659 ret = sdhc_spi_send_cmd(dev, cmd, true);
660 if (ret) {
661 continue;
662 }
663 if ((cmd->opcode == SD_WRITE_SINGLE_BLOCK) ||
664 (cmd->opcode == SD_WRITE_MULTIPLE_BLOCK)) {
665 ret = sdhc_spi_write_data(dev, data);
666 } else {
667 ret = sdhc_spi_read_data(dev, data);
668 }
669 if (ret || (cmd->opcode == SD_READ_MULTIPLE_BLOCK)) {
670 int stop_retries = cmd->retries;
671
672 /* CMD12 is required after multiple read, or
673 * to retry failed transfer
674 */
675 stop_ret = sdhc_spi_send_cmd(dev,
676 (struct sdhc_command *)&stop_cmd,
677 false);
678 while ((stop_ret != 0) && (stop_retries > 0)) {
679 /* Retry stop command */
680 ret = stop_ret = sdhc_spi_send_cmd(dev,
681 (struct sdhc_command *)&stop_cmd,
682 false);
683 stop_retries--;
684 }
685 }
686 } while ((ret != 0) && (retries > 0));
687 }
688
689 /* Release SPI bus */
690 ret2 = spi_release(config->spi_dev, dev_data->spi_cfg);
691
692 /* Release request for SPI bus to be active */
693 (void)pm_device_runtime_put(config->spi_dev);
694
695 return ret ? ret : ret2;
696 }
697
sdhc_spi_set_io(const struct device * dev,struct sdhc_io * ios)698 static int sdhc_spi_set_io(const struct device *dev, struct sdhc_io *ios)
699 {
700 const struct sdhc_spi_config *cfg = dev->config;
701 struct sdhc_spi_data *data = dev->data;
702
703 if (ios->clock != data->spi_cfg->frequency) {
704 if (ios->clock > cfg->spi_max_freq) {
705 return -ENOTSUP;
706 }
707 /* Because pointer comparision is used, we have to
708 * swap to a new configuration structure to reconfigure SPI.
709 */
710 if (ios->clock != 0) {
711 if (data->spi_cfg == &data->cfg_a) {
712 data->cfg_a.frequency = ios->clock;
713 memcpy(&data->cfg_b, &data->cfg_a,
714 sizeof(struct spi_config));
715 data->spi_cfg = &data->cfg_b;
716 } else {
717 data->cfg_b.frequency = ios->clock;
718 memcpy(&data->cfg_a, &data->cfg_b,
719 sizeof(struct spi_config));
720 data->spi_cfg = &data->cfg_a;
721 }
722 }
723 }
724 if (ios->bus_mode != SDHC_BUSMODE_PUSHPULL) {
725 /* SPI mode supports push pull */
726 return -ENOTSUP;
727 }
728 if (data->power_mode != ios->power_mode) {
729 if (ios->power_mode == SDHC_POWER_ON) {
730 if (cfg->pwr_gpio.port) {
731 if (gpio_pin_set_dt(&cfg->pwr_gpio, 1)) {
732 return -EIO;
733 }
734
735 /* Wait until VDD is stable. Per the spec:
736 * Maximum VDD rise time of 35ms.
737 * Minimum 1ms VDD stable time.
738 */
739 k_sleep(K_MSEC(36));
740
741 LOG_INF("Powered up");
742 }
743
744 /* Send 74 clock cycles to start card */
745 if (sdhc_spi_init_card(dev) != 0) {
746 LOG_ERR("Card SCLK init sequence failed");
747 return -EIO;
748 }
749 } else {
750 if (cfg->pwr_gpio.port) {
751 if (gpio_pin_set_dt(&cfg->pwr_gpio, 0)) {
752 return -EIO;
753 }
754 LOG_INF("Powered down");
755 }
756 }
757 data->power_mode = ios->power_mode;
758 }
759 if (ios->bus_width != SDHC_BUS_WIDTH1BIT) {
760 /* SPI mode supports 1 bit bus */
761 return -ENOTSUP;
762 }
763 if (ios->signal_voltage != SD_VOL_3_3_V) {
764 /* SPI mode does not support UHS voltages */
765 return -ENOTSUP;
766 }
767 return 0;
768 }
769
sdhc_spi_get_card_present(const struct device * dev)770 static int sdhc_spi_get_card_present(const struct device *dev)
771 {
772 /* SPI has no card presence method, assume card is in slot */
773 return 1;
774 }
775
sdhc_spi_get_host_props(const struct device * dev,struct sdhc_host_props * props)776 static int sdhc_spi_get_host_props(const struct device *dev,
777 struct sdhc_host_props *props)
778 {
779 const struct sdhc_spi_config *cfg = dev->config;
780
781 memset(props, 0, sizeof(struct sdhc_host_props));
782
783 props->f_min = SDMMC_CLOCK_400KHZ;
784 props->f_max = cfg->spi_max_freq;
785 props->power_delay = cfg->power_delay_ms;
786 props->host_caps.vol_330_support = true;
787 props->is_spi = true;
788 return 0;
789 }
790
sdhc_spi_reset(const struct device * dev)791 static int sdhc_spi_reset(const struct device *dev)
792 {
793 struct sdhc_spi_data *data = dev->data;
794
795 /* Reset host I/O */
796 data->spi_cfg->frequency = SDMMC_CLOCK_400KHZ;
797 return 0;
798 }
799
sdhc_spi_init(const struct device * dev)800 static int sdhc_spi_init(const struct device *dev)
801 {
802 const struct sdhc_spi_config *cfg = dev->config;
803 struct sdhc_spi_data *data = dev->data;
804 int ret = 0;
805
806 if (!device_is_ready(cfg->spi_dev)) {
807 return -ENODEV;
808 }
809 if (cfg->pwr_gpio.port) {
810 if (!gpio_is_ready_dt(&cfg->pwr_gpio)) {
811 return -ENODEV;
812 }
813 ret = gpio_pin_configure_dt(&cfg->pwr_gpio, GPIO_OUTPUT_INACTIVE);
814 if (ret != 0) {
815 LOG_ERR("Could not configure power gpio (%d)", ret);
816 return ret;
817 }
818 }
819 data->power_mode = SDHC_POWER_OFF;
820 data->spi_cfg = &data->cfg_a;
821 data->spi_cfg->frequency = 0;
822 return ret;
823 }
824
825 static DEVICE_API(sdhc, sdhc_spi_api) = {
826 .request = sdhc_spi_request,
827 .set_io = sdhc_spi_set_io,
828 .get_host_props = sdhc_spi_get_host_props,
829 .get_card_present = sdhc_spi_get_card_present,
830 .reset = sdhc_spi_reset,
831 .card_busy = sdhc_spi_card_busy,
832 };
833
834
835 #define SDHC_SPI_INIT(n) \
836 const struct sdhc_spi_config sdhc_spi_config_##n = { \
837 .spi_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), \
838 .pwr_gpio = GPIO_DT_SPEC_INST_GET_OR(n, pwr_gpios, {0}), \
839 .spi_max_freq = DT_INST_PROP(n, spi_max_frequency), \
840 .power_delay_ms = DT_INST_PROP(n, power_delay_ms), \
841 }; \
842 \
843 struct sdhc_spi_data sdhc_spi_data_##n = { \
844 .cfg_a = SPI_CONFIG_DT_INST(n, \
845 (SPI_LOCK_ON | SPI_HOLD_ON_CS | SPI_WORD_SET(8) \
846 | (DT_INST_PROP(n, spi_clock_mode_cpol) ? SPI_MODE_CPOL : 0) \
847 | (DT_INST_PROP(n, spi_clock_mode_cpha) ? SPI_MODE_CPHA : 0) \
848 ),\
849 0), \
850 }; \
851 \
852 DEVICE_DT_INST_DEFINE(n, \
853 &sdhc_spi_init, \
854 NULL, \
855 &sdhc_spi_data_##n, \
856 &sdhc_spi_config_##n, \
857 POST_KERNEL, \
858 CONFIG_SDHC_INIT_PRIORITY, \
859 &sdhc_spi_api);
860
861 DT_INST_FOREACH_STATUS_OKAY(SDHC_SPI_INIT)
862
