1/* 2 * Copyright 2022-2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-r.dtsi> 9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10#include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "arm,cortex-r52"; 20 reg = <0>; 21 }; 22 23 cpu@1 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-r52"; 26 reg = <1>; 27 }; 28 29 cpu@2 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-r52"; 32 reg = <2>; 33 }; 34 35 cpu@3 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-r52"; 38 reg = <3>; 39 }; 40 41 cpu@4 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-r52"; 44 reg = <4>; 45 }; 46 47 cpu@5 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-r52"; 50 reg = <5>; 51 }; 52 53 cpu@6 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-r52"; 56 reg = <6>; 57 }; 58 59 cpu@7 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-r52"; 62 reg = <7>; 63 }; 64 }; 65 66 arch_timer: timer { 67 compatible = "arm,armv8_timer"; 68 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 69 <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 70 <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 71 <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 72 interrupt-parent = <&gic>; 73 }; 74 75 /* Dummy pinctrl node, filled with pin mux options at board level */ 76 pinctrl: pinctrl { 77 compatible = "nxp,s32ze-pinctrl"; 78 status = "okay"; 79 }; 80 81 soc { 82 interrupt-parent = <&gic>; 83 84 clock: clock-controller@40030000 { 85 compatible = "nxp,s32-clock"; 86 reg = <0x40030000 0x10000>, 87 <0x40200000 0x10000>, 88 <0x40210000 0x10000>, 89 <0x40220000 0x10000>, 90 <0x40260000 0x10000>, 91 <0x40270000 0x10000>, 92 <0x40830000 0x10000>, 93 <0x41030000 0x10000>, 94 <0x41830000 0x10000>, 95 <0x42030000 0x10000>, 96 <0x42830000 0x10000>, 97 <0x44030000 0x10000>, 98 <0x440a0000 0x10000>; 99 #clock-cells = <1>; 100 status = "okay"; 101 }; 102 103 gic: interrupt-controller@47800000 { 104 compatible = "arm,gic-v3", "arm,gic"; 105 reg = <0x47800000 0x10000>, 106 <0x47900000 0x80000>; 107 interrupt-controller; 108 #interrupt-cells = <4>; 109 status = "okay"; 110 }; 111 112 sram0: memory@31780000 { 113 compatible = "mmio-sram"; 114 reg = <0x31780000 DT_SIZE_M(1)>; 115 }; 116 117 sram1: memory@35780000 { 118 compatible = "mmio-sram"; 119 reg = <0x35780000 DT_SIZE_M(1)>; 120 }; 121 122 uart0: uart@40170000 { 123 compatible = "nxp,s32-linflexd"; 124 reg = <0x40170000 0x1000>; 125 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 126 status = "disabled"; 127 }; 128 129 uart1: uart@40180000 { 130 compatible = "nxp,s32-linflexd"; 131 reg = <0x40180000 0x1000>; 132 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 133 status = "disabled"; 134 }; 135 136 uart2: uart@40190000 { 137 compatible = "nxp,s32-linflexd"; 138 reg = <0x40190000 0x1000>; 139 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 140 status = "disabled"; 141 }; 142 143 uart3: uart@40970000 { 144 compatible = "nxp,s32-linflexd"; 145 reg = <0x40970000 0x1000>; 146 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 147 status = "disabled"; 148 }; 149 150 uart4: uart@40980000 { 151 compatible = "nxp,s32-linflexd"; 152 reg = <0x40980000 0x1000>; 153 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 154 status = "disabled"; 155 }; 156 157 uart5: uart@40990000 { 158 compatible = "nxp,s32-linflexd"; 159 reg = <0x40990000 0x1000>; 160 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 161 status = "disabled"; 162 }; 163 164 uart6: uart@42170000 { 165 compatible = "nxp,s32-linflexd"; 166 reg = <0x42170000 0x1000>; 167 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 168 status = "disabled"; 169 }; 170 171 uart7: uart@42180000 { 172 compatible = "nxp,s32-linflexd"; 173 reg = <0x42180000 0x1000>; 174 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 175 status = "disabled"; 176 }; 177 178 uart8: uart@42190000 { 179 compatible = "nxp,s32-linflexd"; 180 reg = <0x42190000 0x1000>; 181 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 182 status = "disabled"; 183 }; 184 185 uart9: uart@42980000 { 186 compatible = "nxp,s32-linflexd"; 187 reg = <0x42980000 0x1000>; 188 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 189 status = "disabled"; 190 }; 191 192 uart10: uart@42990000 { 193 compatible = "nxp,s32-linflexd"; 194 reg = <0x42990000 0x1000>; 195 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 196 status = "disabled"; 197 }; 198 199 uart11: uart@429a0000 { 200 compatible = "nxp,s32-linflexd"; 201 reg = <0x429a0000 0x1000>; 202 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 203 status = "disabled"; 204 }; 205 206 uart12: uart@40330000 { 207 compatible = "nxp,s32-linflexd"; 208 reg = <0x40330000 0x1000>; 209 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 210 status = "disabled"; 211 }; 212 213 siul2_0: siul2@40520000 { 214 reg = <0x40520000 0x10000>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 218 eirq0: eirq0@40520010 { 219 compatible = "nxp,s32-siul2-eirq"; 220 reg = <0x40520010 0xb4>; 221 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 status = "disabled"; 225 }; 226 227 gpioa: gpio@40521702 { 228 compatible = "nxp,s32-gpio"; 229 reg = <0x40521702 0x02>, <0x40520240 0x40>; 230 reg-names = "pgpdo", "mscr"; 231 interrupt-parent = <&eirq0>; 232 interrupts = <1 1>, <3 0>, <5 2>, <12 3>, 233 <13 4>, <14 5>, <15 6>; 234 gpio-controller; 235 #gpio-cells = <2>; 236 ngpios = <16>; 237 status = "disabled"; 238 }; 239 240 gpiob: gpio@40521700 { 241 compatible = "nxp,s32-gpio"; 242 reg = <0x40521700 0x02>, <0x40520280 0x40>; 243 reg-names = "pgpdo", "mscr"; 244 interrupt-parent = <&eirq0>; 245 interrupts = <0 7>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 ngpios = <15>; 249 status = "disabled"; 250 }; 251 252 gpioo: gpio@40521716 { 253 compatible = "nxp,s32-gpio"; 254 reg = <0x40521716 0x02>, <0x405204c0 0x40>; 255 reg-names = "pgpdo", "mscr"; 256 gpio-controller; 257 #gpio-cells = <2>; 258 ngpios = <14>; 259 gpio-reserved-ranges = <0 10>; 260 status = "disabled"; 261 }; 262 }; 263 264 siul2_1: siul2@40d20000 { 265 reg = <0x40d20000 0x10000>; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 269 eirq1: eirq1@40d20010 { 270 compatible = "nxp,s32-siul2-eirq"; 271 reg = <0x40d20010 0xb4>; 272 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 status = "disabled"; 276 }; 277 278 gpioc: gpio@40d21700 { 279 compatible = "nxp,s32-gpio"; 280 reg = <0x40d21700 0x02>, <0x40d20280 0x40>; 281 reg-names = "pgpdo", "mscr"; 282 interrupt-parent = <&eirq1>; 283 interrupts = <3 0>, <5 1>; 284 gpio-controller; 285 #gpio-cells = <2>; 286 ngpios = <16>; 287 gpio-reserved-ranges = <0 15>; 288 status = "disabled"; 289 }; 290 291 gpiod: gpio@40d21706 { 292 compatible = "nxp,s32-gpio"; 293 reg = <0x40d21706 0x02>, <0x40d202c0 0x40>; 294 reg-names = "pgpdo", "mscr"; 295 gpio-controller; 296 #gpio-cells = <2>; 297 ngpios = <16>; 298 status = "disabled"; 299 }; 300 301 gpioe: gpio@40d21704 { 302 compatible = "nxp,s32-gpio"; 303 reg = <0x40d21704 0x02>, <0x40d20300 0x40>; 304 reg-names = "pgpdo", "mscr"; 305 gpio-controller; 306 #gpio-cells = <2>; 307 ngpios = <16>; 308 status = "disabled"; 309 }; 310 311 gpiof: gpio@40d2170a { 312 compatible = "nxp,s32-gpio"; 313 reg = <0x40d2170a 0x02>, <0x40d20340 0x40>; 314 reg-names = "pgpdo", "mscr"; 315 gpio-controller; 316 #gpio-cells = <2>; 317 ngpios = <16>; 318 status = "disabled"; 319 }; 320 321 gpiog: gpio@40d21708 { 322 compatible = "nxp,s32-gpio"; 323 reg = <0x40d21708 0x02>, <0x40d20380 0x40>; 324 reg-names = "pgpdo", "mscr"; 325 interrupt-parent = <&eirq1>; 326 interrupts = <0 2>, <1 3>, <4 4>, 327 <5 5>, <10 6>, <11 7>; 328 gpio-controller; 329 #gpio-cells = <2>; 330 ngpios = <12>; 331 status = "disabled"; 332 }; 333 }; 334 335 siul2_3: siul2@41d20000 { 336 reg = <0x41d20000 0x10000>; 337 }; 338 339 siul2_4: siul2@42520000 { 340 reg = <0x42520000 0x10000>; 341 #address-cells = <1>; 342 #size-cells = <1>; 343 344 eirq4: eirq4@42520010 { 345 compatible = "nxp,s32-siul2-eirq"; 346 reg = <0x42520010 0xb4>; 347 interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 status = "disabled"; 351 }; 352 353 gpioh: gpio@42521708 { 354 compatible = "nxp,s32-gpio"; 355 reg = <0x42521708 0x02>, <0x42520380 0x40>; 356 reg-names = "pgpdo", "mscr"; 357 gpio-controller; 358 #gpio-cells = <2>; 359 ngpios = <16>; 360 gpio-reserved-ranges = <0 12>; 361 status = "disabled"; 362 }; 363 364 gpioi: gpio@4252170e { 365 compatible = "nxp,s32-gpio"; 366 reg = <0x4252170e 0x02>, <0x425203c0 0x40>; 367 reg-names = "pgpdo", "mscr"; 368 interrupt-parent = <&eirq4>; 369 interrupts = <11 0>, <13 1>; 370 gpio-controller; 371 #gpio-cells = <2>; 372 ngpios = <16>; 373 status = "disabled"; 374 }; 375 376 gpioj: gpio@4252170c { 377 compatible = "nxp,s32-gpio"; 378 reg = <0x4252170c 0x02>, <0x42520400 0x40>; 379 reg-names = "pgpdo", "mscr"; 380 interrupt-parent = <&eirq4>; 381 interrupts = <12 2>; 382 gpio-controller; 383 #gpio-cells = <2>; 384 ngpios = <16>; 385 status = "disabled"; 386 }; 387 388 gpiok: gpio@42521712 { 389 compatible = "nxp,s32-gpio"; 390 reg = <0x42521712 0x02>, <0x42520440 0x40>; 391 reg-names = "pgpdo", "mscr"; 392 interrupt-parent = <&eirq4>; 393 interrupts = <4 3>, <6 4>, <9 5>, 394 <11 6>, <13 7>; 395 gpio-controller; 396 #gpio-cells = <2>; 397 ngpios = <16>; 398 status = "disabled"; 399 }; 400 401 gpiol: gpio@42521710 { 402 compatible = "nxp,s32-gpio"; 403 reg = <0x42521710 0x02>, <0x42520480 0x40>; 404 reg-names = "pgpdo", "mscr"; 405 gpio-controller; 406 #gpio-cells = <2>; 407 ngpios = <2>; 408 status = "disabled"; 409 }; 410 }; 411 412 siul2_5: siul2@42d20000 { 413 reg = <0x42d20000 0x10000>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 417 eirq5: eirq5@42d20010 { 418 compatible = "nxp,s32-siul2-eirq"; 419 reg = <0x42d20010 0xb4>; 420 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 status = "disabled"; 424 }; 425 426 gpiom: gpio@42d21710 { 427 compatible = "nxp,s32-gpio"; 428 reg = <0x42d21710 0x02>, <0x42d20480 0x40>; 429 reg-names = "pgpdo", "mscr"; 430 interrupt-parent = <&eirq5>; 431 interrupts = <1 0>, <3 1>, <5 2>, <7 3>; 432 gpio-controller; 433 #gpio-cells = <2>; 434 ngpios = <16>; 435 gpio-reserved-ranges = <0 2>; 436 status = "disabled"; 437 }; 438 439 gpion: gpio@42d21716 { 440 compatible = "nxp,s32-gpio"; 441 reg = <0x42d21716 0x02>, <0x42d204c0 0x40>; 442 reg-names = "pgpdo", "mscr"; 443 interrupt-parent = <&eirq5>; 444 interrupts = <0 4>, <2 5>, <5 6>, <6 7>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 ngpios = <10>; 448 status = "disabled"; 449 }; 450 }; 451 452 spi0: spi@40130000 { 453 compatible = "nxp,s32-spi"; 454 reg = <0x40130000 0x10000>; 455 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 456 clocks = <&clock NXP_S32_SPI0_CLK>; 457 num-cs = <5>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 463 spi1: spi@40140000 { 464 compatible = "nxp,s32-spi"; 465 reg = <0x40140000 0x10000>; 466 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 467 clocks = <&clock NXP_S32_SPI1_CLK>; 468 num-cs = <5>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 status = "disabled"; 472 }; 473 474 spi2: spi@40930000 { 475 compatible = "nxp,s32-spi"; 476 reg = <0x40930000 0x10000>; 477 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 478 clocks = <&clock NXP_S32_SPI2_CLK>; 479 num-cs = <5>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 spi3: spi@40940000 { 486 compatible = "nxp,s32-spi"; 487 reg = <0x40940000 0x10000>; 488 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 489 clocks = <&clock NXP_S32_SPI3_CLK>; 490 num-cs = <5>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 496 spi4: spi@40950000 { 497 compatible = "nxp,s32-spi"; 498 reg = <0x40950000 0x10000>; 499 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 500 clocks = <&clock NXP_S32_SPI4_CLK>; 501 num-cs = <5>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 507 spi5: spi@42130000 { 508 compatible = "nxp,s32-spi"; 509 reg = <0x42130000 0x10000>; 510 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 511 clocks = <&clock NXP_S32_SPI5_CLK>; 512 num-cs = <5>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 status = "disabled"; 516 }; 517 518 spi6: spi@42140000 { 519 compatible = "nxp,s32-spi"; 520 reg = <0x42140000 0x10000>; 521 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 522 clocks = <&clock NXP_S32_SPI6_CLK>; 523 num-cs = <5>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 status = "disabled"; 527 }; 528 529 spi7: spi@42150000 { 530 compatible = "nxp,s32-spi"; 531 reg = <0x42150000 0x10000>; 532 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 533 clocks = <&clock NXP_S32_SPI7_CLK>; 534 num-cs = <5>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 spi8: spi@42930000 { 541 compatible = "nxp,s32-spi"; 542 reg = <0x42930000 0x10000>; 543 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 544 clocks = <&clock NXP_S32_SPI8_CLK>; 545 num-cs = <5>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 spi9: spi@42940000 { 552 compatible = "nxp,s32-spi"; 553 reg = <0x42940000 0x10000>; 554 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 555 clocks = <&clock NXP_S32_SPI9_CLK>; 556 num-cs = <5>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 status = "disabled"; 560 }; 561 562 mru0: mbox@76070000 { 563 compatible = "nxp,s32-mru"; 564 reg = <0x76070000 0x10000>; 565 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 566 #mbox-cells = <1>; 567 status = "disabled"; 568 }; 569 570 mru1: mbox@76090000 { 571 compatible = "nxp,s32-mru"; 572 reg = <0x76090000 0x10000>; 573 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 574 #mbox-cells = <1>; 575 status = "disabled"; 576 }; 577 578 mru2: mbox@76270000 { 579 compatible = "nxp,s32-mru"; 580 reg = <0x76270000 0x10000>; 581 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 582 #mbox-cells = <1>; 583 status = "disabled"; 584 }; 585 586 mru3: mbox@76290000 { 587 compatible = "nxp,s32-mru"; 588 reg = <0x76290000 0x10000>; 589 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 590 #mbox-cells = <1>; 591 status = "disabled"; 592 }; 593 594 mru4: mbox@76870000 { 595 compatible = "nxp,s32-mru"; 596 reg = <0x76870000 0x10000>; 597 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 598 #mbox-cells = <1>; 599 status = "disabled"; 600 }; 601 602 mru5: mbox@76890000 { 603 compatible = "nxp,s32-mru"; 604 reg = <0x76890000 0x10000>; 605 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 606 #mbox-cells = <1>; 607 status = "disabled"; 608 }; 609 610 mru6: mbox@76a70000 { 611 compatible = "nxp,s32-mru"; 612 reg = <0x76a70000 0x10000>; 613 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 614 #mbox-cells = <1>; 615 status = "disabled"; 616 }; 617 618 mru7: mbox@76a90000 { 619 compatible = "nxp,s32-mru"; 620 reg = <0x76a90000 0x10000>; 621 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 622 #mbox-cells = <1>; 623 status = "disabled"; 624 }; 625 626 netc: ethernet@74000000 { 627 reg = <0x74000000 0x1000000>; 628 #address-cells = <1>; 629 #size-cells = <1>; 630 ranges; 631 632 emdio: mdio@74b60000 { 633 compatible = "nxp,s32-netc-emdio"; 634 reg = <0x74b60000 0x1c44>; 635 status = "disabled"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 }; 639 640 enetc_psi0: ethernet@74b00000 { 641 compatible = "nxp,s32-netc-psi"; 642 reg = <0x74b00000 0x10000>; 643 status = "disabled"; 644 }; 645 646 enetc_vsi1: ethernet@74bc0000 { 647 compatible = "nxp,s32-netc-vsi"; 648 reg = <0x74bc0000 0x10000>; 649 status = "disabled"; 650 }; 651 652 enetc_vsi2: ethernet@74bd0000 { 653 compatible = "nxp,s32-netc-vsi"; 654 reg = <0x74bd0000 0x10000>; 655 status = "disabled"; 656 }; 657 658 enetc_vsi3: ethernet@74be0000 { 659 compatible = "nxp,s32-netc-vsi"; 660 reg = <0x74be0000 0x10000>; 661 status = "disabled"; 662 }; 663 664 enetc_vsi4: ethernet@74bf0000 { 665 compatible = "nxp,s32-netc-vsi"; 666 reg = <0x74bf0000 0x10000>; 667 status = "disabled"; 668 }; 669 670 enetc_vsi5: ethernet@74c00000 { 671 compatible = "nxp,s32-netc-vsi"; 672 reg = <0x74c00000 0x10000>; 673 status = "disabled"; 674 }; 675 676 enetc_vsi6: ethernet@74c10000 { 677 compatible = "nxp,s32-netc-vsi"; 678 reg = <0x74c10000 0x10000>; 679 status = "disabled"; 680 }; 681 682 enetc_vsi7: ethernet@74c20000 { 683 compatible = "nxp,s32-netc-vsi"; 684 reg = <0x74c20000 0x10000>; 685 status = "disabled"; 686 }; 687 }; 688 689 can0: can@4741b000 { 690 compatible = "nxp,s32-canxl"; 691 reg = <0x4741b000 0x1000>, 692 <0x47423000 0x1000>, 693 <0x47425000 0x1000>, 694 <0x47427000 0x1000>; 695 reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; 696 status = "disabled"; 697 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 698 <GIC_SPI 225 IRQ_TYPE_LEVEL 0xb0>; 699 interrupt-names = "rx_tx_mru", "error"; 700 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 701 }; 702 703 can1: can@4751b000 { 704 compatible = "nxp,s32-canxl"; 705 reg = <0x4751b000 0x1000>, 706 <0x47523000 0x1000>, 707 <0x47525000 0x1000>, 708 <0x47527000 0x1000>; 709 reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; 710 status = "disabled"; 711 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 712 <GIC_SPI 227 IRQ_TYPE_LEVEL 0xb0>; 713 interrupt-names = "rx_tx_mru", "error"; 714 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 715 }; 716 }; 717}; 718
