1/*
2 * Copyright (c) 2024 Analog Devices Inc.
3 * Copyright (c) 2024 Baylibre, SAS
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <dt-bindings/gpio/adi-sdp-120.h>
9
10/ {
11	sdp_k1_120_hdr: connector {
12		compatible = "adi,sdp-120";
13		#gpio-cells = <2>;
14		gpio-map-mask = <0xffffffff 0xffffffc0>;
15		gpio-map-pass-thru = <0 0x3f>;
16		gpio-map =
17			/* pin map */			/* sdp-120 */
18			<32 0 &gpiof 7 0>,		/* SPI_D2 */
19			<33 0 &gpiod 13 0>,		/* SPI_D3 */
20			<34 0 &gpioc 11 0>,		/* SERIAL_INT */
21			<36 0 &gpioc 6 0>,		/* SPI_SEL_B_N */
22			<37 0 &gpioc 7 0>,		/* SPI_SEL_C_N */
23			<38 0 &gpiof 6 0>,		/* SPI_SEL1/SPI_SS_N */
24
25			<42 0 &gpioj 0 0>,		/* GPIO0 */
26			<43 0 &gpioj 3 0>,		/* GPIO2 */
27			<44 0 &gpioj 5 0>,		/* GPIO4 */
28			<46 0 &gpioj 13 0>,		/* GPIO6 */
29
30			/* TIMER A */
31			<47 0 &gpiob 14 0>,		/* TMR_A */
32
33			<58 0 &gpiod 6 0>,		/* UART2_RX */
34			<61 0 &gpiod 5 0>,		/* UART2_TX */
35
36			/* TIMER D */
37			<71 0 &gpioc 8 0>,		/* TMR_D */
38
39			/* TIMER B */
40			<72 0 &gpioe 6 0>,		/* TMR_B */
41
42			<73 0 &gpioj 14 0>,		/* GPIO7 */
43			<75 0 &gpioj 12 0>,		/* GPIO5 */
44			<76 0 &gpioj 4 0>,		/* GPIO3 */
45			<77 0 &gpioj 1 0>,		/* GPIO1 */
46
47			/* I2C3 */
48			<78 0 &gpioh 7 0>,		/* SCL_0 */
49			<79 0 &gpioc 9 0>,		/* SDA_0 */
50
51			/* SPI5 */
52			<81 0 &gpioh 6 0>,		/* SPI_CLK  - spi5_sck_ph6 */
53			<82 0 &gpiof 8 0>,		/* SPI_MISO - spi5_miso_pf8 */
54			<83 0 &gpiof 9 0>,		/* SPI_MOSI - spi5_mosi_pf9 */
55			<84 0 &gpiob 6 0>,		/* SPI_SEL_A_N - could be PB6 or PB9 */
56
57			/* SPORT - no driver yet */
58			<86 0 &gpiog 13 0>,		/* SPORT_TSCLK */
59			<87 0 &gpiog 14 0>,		/* SPORT_DT0 */
60			<88 0 &gpioa 8 0>,		/* SPORT_TFS */
61			<89 0 &gpioe 4 0>,		/* SPORT_RFS */
62			<90 0 &gpioe 5 0>,		/* SPORT_DR0 */
63			<91 0 &gpioe 2 0>;		/* SPORT_RSCLK */
64	};
65
66	pmod_spi {
67		compatible = "digilent,pmod";
68		#gpio-cells = <2>;
69		gpio-map-mask = <0xffffffff 0xffffffc0>;
70		gpio-map-pass-thru = <0 0x3f>;
71		gpio-map =	<0 0 &sdp_k1_120_hdr SDP_120_SPI_SEL_A_N 0>,	// IO1
72				<1 0 &sdp_k1_120_hdr SDP_120_SPI_MISO 0>,	// IO2
73				<2 0 &sdp_k1_120_hdr SDP_120_SPI_MOSI 0>,	// IO3
74				<3 0 &sdp_k1_120_hdr SDP_120_SPI_CLK 0>,	// IO4
75				<4 0 &sdp_k1_120_hdr SDP_120_SERIAL_INT 0>,	// IO5
76				<5 0 &sdp_k1_120_hdr SDP_120_GPIO5 0>,		// IO6
77				<6 0 &sdp_k1_120_hdr SDP_120_GPIO6 0>,		// IO7
78				<7 0 &sdp_k1_120_hdr SDP_120_GPIO7 0>;		// IO8
79		status = "disabled";
80	};
81
82	pmod_usart {
83		compatible = "digilent,pmod";
84		#gpio-cells = <2>;
85		gpio-map-mask = <0xffffffff 0xffffffc0>;
86		gpio-map-pass-thru = <0 0x3f>;
87		gpio-map =	<0 0 &sdp_k1_120_hdr SDP_120_GPIO0 0>,		// IO1
88				<1 0 &sdp_k1_120_hdr SDP_120_UART_TX 0>,	// IO2
89				<2 0 &sdp_k1_120_hdr SDP_120_UART_RX 0>,	// IO3
90				<3 0 &sdp_k1_120_hdr SDP_120_GPIO3 0>,		// IO4
91				<4 0 &sdp_k1_120_hdr SDP_120_SERIAL_INT 0>,	// IO5
92				<5 0 &sdp_k1_120_hdr SDP_120_GPIO5 0>,		// IO6
93				<6 0 &sdp_k1_120_hdr SDP_120_GPIO6 0>,		// IO7
94				<7 0 &sdp_k1_120_hdr SDP_120_GPIO7 0>;		// IO8
95		status = "disabled";
96	};
97
98};
99
100/*
101 * Note from sdp-k1 schematic for overlapping signals
102 *
103 *   NOTE: SOME OF THE SPI & QUADSPI SIGNALS ON THE SDP
104 *   CONNECTOR ON PAGE 9 ARE ROUTED TO MULTIPLE PINS ON THE
105 *   STM32F469. TAKE CARE NOT TO ENABLE SPI AND QUADSPI ON
106 *   THE SDP CONNECTOR SIMULTANEOUSLY.
107 */
108
109sdp_spi: &spi5 {
110	pinctrl-0 = <&spi5_sck_ph6 &spi5_miso_pf8 &spi5_mosi_pf9>;
111	pinctrl-names = "default";
112	cs-gpios = <&sdp_k1_120_hdr SDP_120_SPI_SEL_A_N (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
113	status = "okay";
114};
115
116sdp_i2c: &i2c3 { };
117
118sdp_serial: &usart2{ };
119