1/* 2 * Copyright (c) 2020, Linaro Ltd. 3 * Copyright 2024 NXP 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h> 14#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 15#include <arm/armv8-m.dtsi> 16#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 17 18/ { 19 aliases { 20 watchdog0 = &wwdt0; 21 }; 22 23 chosen { 24 zephyr,flash-controller = &iap; 25 }; 26 27 cpus: cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 compatible = "arm,cortex-m33f"; 33 reg = <0>; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 cpu-power-states = <&sleep>; 37 38 mpu: mpu@e000ed90 { 39 compatible = "arm,armv8m-mpu"; 40 reg = <0xe000ed90 0x40>; 41 }; 42 }; 43 cpu@1 { 44 compatible = "arm,cortex-m33"; 45 reg = <1>; 46 }; 47 48 power-states { 49 sleep: sleep { 50 compatible = "zephyr,power-state"; 51 power-state-name = "runtime-idle"; 52 min-residency-us = <4>; 53 exit-latency-us = <4>; 54 }; 55 }; 56 }; 57}; 58 59&sram { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 63 sramx: memory@4000000 { 64 compatible = "mmio-sram"; 65 reg = <0x4000000 DT_SIZE_K(32)>; 66 }; 67 68 /* lpc55S6x Memory configurations: 69 * 70 * RAM blocks SRAM0 through SRAM4 are contiguous address ranges 71 * 72 * LPC55S66: 144KB RAM, RAMX: 32K, SRAM0: 32K 73 * LPC55S69: 320KB RAM, RAMX: 32K, SRAM0: 64K, SRAM1: 64K, 74 * SRAM2: 64K, SRAM3: 64K, SRAM4: 16K 75 */ 76 sram0: memory@20000000 { 77 compatible = "mmio-sram"; 78 reg = <0x20000000 DT_SIZE_K(64)>; 79 }; 80 81 sram1: memory@20010000 { 82 compatible = "mmio-sram"; 83 reg = <0x20010000 DT_SIZE_K(64)>; 84 }; 85 86 sram2: memory@20020000 { 87 compatible = "mmio-sram"; 88 reg = <0x20020000 DT_SIZE_K(64)>; 89 }; 90 91 sram3: memory@20030000 { 92 compatible = "mmio-sram"; 93 reg = <0x20030000 DT_SIZE_K(64)>; 94 }; 95 96 sram4: memory@20040000 { 97 compatible = "mmio-sram"; 98 reg = <0x20040000 DT_SIZE_K(16)>; 99 }; 100}; 101 102&peripheral { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 106 usb_sram: memory@100000 { 107 compatible = "zephyr,memory-region", "mmio-sram"; 108 reg = <0x100000 DT_SIZE_K(16)>; 109 zephyr,memory-region = "USB_SRAM"; 110 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; 111 }; 112 113 syscon: syscon@0 { 114 compatible = "nxp,lpc-syscon"; 115 reg = <0x0 0x1000>; 116 #clock-cells = <1>; 117 reset: reset { 118 compatible = "nxp,lpc-syscon-reset"; 119 #reset-cells = <1>; 120 }; 121 }; 122 123 iap: flash-controller@34000 { 124 compatible = "nxp,iap-fmc55"; 125 reg = <0x34000 0x1000>; 126 #address-cells = <1>; 127 #size-cells = <1>; 128 status = "disabled"; 129 flash0: flash@0 { 130 compatible = "soc-nv-flash"; 131 reg = <0x0 DT_SIZE_K(630)>; 132 erase-block-size = <512>; 133 write-block-size = <512>; 134 }; 135 136 flash_reserved: flash@9D800 { 137 compatible = "soc-nv-flash"; 138 reg = <0x9D800 DT_SIZE_K(9)>; 139 status = "disabled"; 140 }; 141 142 uuid: flash@9fc70 { 143 compatible = "nxp,lpc-uid"; 144 reg = <0x9fc70 0x10>; 145 }; 146 147 boot_rom: flash@3000000 { 148 compatible = "soc-nv-flash"; 149 reg = <0x3000000 DT_SIZE_K(128)>; 150 }; 151 }; 152 153 iocon: iocon@1000 { 154 compatible = "nxp,lpc-iocon"; 155 reg = <0x1000 0x100>; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges = <0x0 0x1000 0x100>; 159 pinctrl: pinctrl { 160 compatible = "nxp,lpc-iocon-pinctrl"; 161 }; 162 }; 163 164 gpio: gpio@8c000 { 165 compatible = "nxp,lpc-gpio"; 166 reg = <0x8c000 0x2488>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 gpio0: gpio@0 { 171 compatible = "nxp,lpc-gpio-port"; 172 reg = <0>; 173 int-source = "pint"; 174 gpio-controller; 175 #gpio-cells = <2>; 176 }; 177 178 gpio1: gpio@1 { 179 compatible = "nxp,lpc-gpio-port"; 180 reg = <1>; 181 int-source = "pint"; 182 gpio-controller; 183 #gpio-cells = <2>; 184 }; 185 }; 186 187 pint: pint@4000 { 188 compatible = "nxp,pint"; 189 reg = <0x4000 0x1000>; 190 interrupt-controller; 191 #interrupt-cells = <1>; 192 #address-cells = <0>; 193 interrupts = <4 2>, <5 2>, <6 2>, <7 2>, 194 <32 2>, <33 2>, <34 2>, <35 2>; 195 num-lines = <8>; 196 num-inputs = <64>; 197 }; 198 199 dma0: dma-controller@82000 { 200 compatible = "nxp,lpc-dma"; 201 reg = <0x82000 0x1000>; 202 interrupts = <1 0>; 203 dma-channels = <23>; 204 nxp,dma-num-of-otrigs = <4>; 205 nxp,dma-otrig-base-address = <LPC55S69_DMA0_OTRIG_BASE>; 206 nxp,dma-itrig-base-address = <LPC55S69_DMA0_ITRIG_BASE>; 207 status = "disabled"; 208 #dma-cells = <1>; 209 }; 210 211 dma1: dma-controller@a7000 { 212 compatible = "nxp,lpc-dma"; 213 reg = <0xa7000 0x1000>; 214 interrupts = <58 0>; 215 dma-channels = <10>; 216 nxp,dma-num-of-otrigs = <4>; 217 nxp,dma-otrig-base-address = <LPC55S69_DMA1_OTRIG_BASE>; 218 nxp,dma-itrig-base-address = <LPC55S69_DMA1_ITRIG_BASE>; 219 status = "disabled"; 220 #dma-cells = <1>; 221 }; 222 223 mailbox0:mailbox@8b000 { 224 compatible = "nxp,lpc-mailbox"; 225 reg = <0x8b000 0xEC>; 226 interrupts = <31 0>; 227 resets = <&reset NXP_SYSCON_RESET(0, 26)>; 228 status = "disabled"; 229 }; 230 231 flexcomm0: flexcomm@86000 { 232 compatible = "nxp,lpc-flexcomm"; 233 reg = <0x86000 0x1000>; 234 interrupts = <14 0>; 235 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 236 resets = <&reset NXP_SYSCON_RESET(1, 11)>; 237 dmas = <&dma0 4>, <&dma0 5>; 238 dma-names = "rx", "tx"; 239 status = "disabled"; 240 }; 241 242 flexcomm1: flexcomm@87000 { 243 compatible = "nxp,lpc-flexcomm"; 244 reg = <0x87000 0x1000>; 245 interrupts = <15 0>; 246 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 247 resets = <&reset NXP_SYSCON_RESET(1, 12)>; 248 dmas = <&dma0 6 &dma0 7>; 249 dma-names = "rx", "tx"; 250 status = "disabled"; 251 }; 252 253 flexcomm2: flexcomm@88000 { 254 compatible = "nxp,lpc-flexcomm"; 255 reg = <0x88000 0x1000>; 256 interrupts = <16 0>; 257 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 258 resets = <&reset NXP_SYSCON_RESET(1, 13)>; 259 dmas = <&dma0 10 &dma0 11>; 260 dma-names = "rx", "tx"; 261 status = "disabled"; 262 }; 263 264 flexcomm3: flexcomm@89000 { 265 compatible = "nxp,lpc-flexcomm"; 266 reg = <0x89000 0x1000>; 267 interrupts = <17 0>; 268 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 269 resets = <&reset NXP_SYSCON_RESET(1, 14)>; 270 dmas = <&dma0 8 &dma0 9>; 271 dma-names = "rx", "tx"; 272 status = "disabled"; 273 }; 274 275 flexcomm4: flexcomm@8a000 { 276 compatible = "nxp,lpc-flexcomm"; 277 reg = <0x8a000 0x1000>; 278 interrupts = <18 0>; 279 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 280 resets = <&reset NXP_SYSCON_RESET(1, 15)>; 281 dmas = <&dma0 12 &dma0 13>; 282 dma-names = "rx", "tx"; 283 status = "disabled"; 284 }; 285 286 flexcomm5: flexcomm@96000 { 287 compatible = "nxp,lpc-flexcomm"; 288 reg = <0x96000 0x1000>; 289 interrupts = <19 0>; 290 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 291 resets = <&reset NXP_SYSCON_RESET(1, 16)>; 292 dmas = <&dma0 14 &dma0 15>; 293 dma-names = "rx", "tx"; 294 status = "disabled"; 295 }; 296 297 flexcomm6: flexcomm@97000 { 298 compatible = "nxp,lpc-flexcomm"; 299 reg = <0x97000 0x1000>; 300 interrupts = <20 0>; 301 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 302 resets = <&reset NXP_SYSCON_RESET(1, 17)>; 303 dmas = <&dma0 16 &dma0 17>; 304 dma-names = "rx", "tx"; 305 status = "disabled"; 306 }; 307 308 flexcomm7: flexcomm@98000 { 309 compatible = "nxp,lpc-flexcomm"; 310 reg = <0x98000 0x1000>; 311 interrupts = <21 0>; 312 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 313 resets = <&reset NXP_SYSCON_RESET(1, 18)>; 314 dmas = <&dma0 18 &dma0 19>; 315 dma-names = "rx", "tx"; 316 status = "disabled"; 317 }; 318 319 sdif: sdif@9b000 { 320 compatible = "nxp,lpc-sdif"; 321 reg = <0x9b000 0x1000>; 322 interrupts = <42 0>; 323 clocks = <&syscon MCUX_SDIF_CLK>; 324 status = "disabled"; 325 }; 326 327 hs_lspi: spi@9f000 { 328 compatible = "nxp,lpc-spi"; 329 /* Enabling cs-gpios below will allow using GPIO CS, 330 rather than Flexcomm SS */ 331 /* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, 332 <&gpio1 1 GPIO_ACTIVE_LOW>, 333 <&gpio1 12 GPIO_ACTIVE_LOW>, 334 <&gpio1 26 GPIO_ACTIVE_LOW>; */ 335 reg = <0x9f000 0x1000>; 336 interrupts = <59 0>; 337 clocks = <&syscon MCUX_HS_SPI_CLK>; 338 resets = <&reset NXP_SYSCON_RESET(2, 28)>; 339 dmas = <&dma0 2 &dma0 3>; 340 dma-names = "rx", "tx"; 341 status = "disabled"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 }; 345 346 rng: rng@3a000 { 347 compatible = "nxp,lpc-rng"; 348 reg = <0x3a000 0x1000>; 349 status = "okay"; 350 }; 351 352 wwdt0: watchdog@c000 { 353 compatible = "nxp,lpc-wwdt"; 354 reg = <0xc000 0x1000>; 355 interrupts = <0 0>; 356 status = "disabled"; 357 clk-divider = <1>; 358 }; 359 360 adc0: adc@A0000 { 361 compatible = "nxp,lpc-lpadc"; 362 reg = <0xA0000 0x1000>; 363 interrupts = <22 0>; 364 status = "disabled"; 365 clk-divider = <8>; 366 clk-source = <0>; 367 voltage-ref= <1>; 368 calibration-average = <128>; 369 power-level = <0>; 370 offset-value-a = <10>; 371 offset-value-b = <10>; 372 #io-channel-cells = <1>; 373 clocks = <&syscon MCUX_LPADC1_CLK>; 374 }; 375 376 usbfs: usbfs@84000 { 377 compatible = "nxp,lpcip3511"; 378 reg = <0x84000 0x1000>; 379 interrupts = <28 1>; 380 num-bidir-endpoints = <5>; 381 maximum-speed = "full-speed"; 382 status = "disabled"; 383 }; 384 385 usbhs: usbhs@94000 { 386 compatible = "nxp,lpcip3511"; 387 reg = <0x94000 0x1000>; 388 interrupts = <47 1>; 389 num-bidir-endpoints = <6>; 390 status = "disabled"; 391 }; 392 393 usbphy1: usbphy@38000 { 394 compatible = "nxp,usbphy"; 395 reg = <0x38000 0x1000>; 396 status = "disabled"; 397 }; 398 399 ctimer0: ctimer@8000 { 400 compatible = "nxp,lpc-ctimer"; 401 reg = <0x8000 0x1000>; 402 interrupts = <10 0>; 403 status = "disabled"; 404 clk-source = <3>; 405 clocks = <&syscon MCUX_CTIMER0_CLK>; 406 mode = <0>; 407 input = <0>; 408 prescale = <0>; 409 }; 410 411 ctimer1: ctimer@9000 { 412 compatible = "nxp,lpc-ctimer"; 413 reg = <0x9000 0x1000>; 414 interrupts = <11 0>; 415 status = "disabled"; 416 clk-source = <3>; 417 clocks = <&syscon MCUX_CTIMER1_CLK>; 418 mode = <0>; 419 input = <0>; 420 prescale = <0>; 421 }; 422 423 ctimer2: ctimer@28000 { 424 compatible = "nxp,lpc-ctimer"; 425 reg = <0x28000 0x1000>; 426 interrupts = <36 0>; 427 status = "disabled"; 428 clk-source = <3>; 429 clocks = <&syscon MCUX_CTIMER2_CLK>; 430 mode = <0>; 431 input = <0>; 432 prescale = <0>; 433 }; 434 435 ctimer3: ctimer@29000 { 436 compatible = "nxp,lpc-ctimer"; 437 reg = <0x29000 0x1000>; 438 interrupts = <13 0>; 439 status = "disabled"; 440 clk-source = <3>; 441 clocks = <&syscon MCUX_CTIMER3_CLK>; 442 mode = <0>; 443 input = <0>; 444 prescale = <0>; 445 }; 446 447 ctimer4: ctimer@2A000 { 448 compatible = "nxp,lpc-ctimer"; 449 reg = <0x2A000 0x1000>; 450 interrupts = <37 0>; 451 status = "disabled"; 452 clk-source = <3>; 453 clocks = <&syscon MCUX_CTIMER4_CLK>; 454 mode = <0>; 455 input = <0>; 456 prescale = <0>; 457 }; 458 459 sc_timer: pwm@85000 { 460 compatible = "nxp,sctimer-pwm"; 461 reg = <0x85000 0x1000>; 462 interrupts = <12 0>; 463 status = "disabled"; 464 clocks = <&syscon MCUX_SCTIMER_CLK>; 465 prescaler = <2>; 466 #pwm-cells = <3>; 467 }; 468 469 mrt: mrt@d000 { 470 compatible = "nxp,mrt"; 471 reg = <0xd000 0x100>; 472 interrupts = <9 0>; 473 num-channels = <4>; 474 num-bits = <24>; 475 clocks = <&syscon MCUX_MRT_CLK>; 476 resets = <&reset NXP_SYSCON_RESET(1, 0)>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 480 mrt_channel0: mrt_channel@0 { 481 compatible = "nxp,mrt-channel"; 482 reg = <0>; 483 status = "disabled"; 484 }; 485 mrt_channel1: mrt_channel@1 { 486 compatible = "nxp,mrt-channel"; 487 reg = <1>; 488 status = "disabled"; 489 }; 490 mrt_channel2: mrt_channel@2 { 491 compatible = "nxp,mrt-channel"; 492 reg = <2>; 493 status = "disabled"; 494 }; 495 mrt_channel3: mrt_channel@3 { 496 compatible = "nxp,mrt-channel"; 497 reg = <3>; 498 status = "disabled"; 499 }; 500 }; 501}; 502 503&nvic { 504 arm,num-irq-priority-bits = <3>; 505}; 506
