1/*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-r.dtsi>
9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	compatible = "renesas,rzt2m-dev";
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-r52";
23			reg = <0>;
24		};
25
26		cpu@1 {
27			device_type = "cpu";
28			compatible = "arm,cortex-r52";
29			reg = <1>;
30		};
31	};
32
33	arch_timer: timer {
34		compatible = "arm,armv8-timer";
35		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
36				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
37				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
38				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
39		interrupt-parent = <&gic>;
40	};
41
42	soc {
43		compatible = "renesas,rzt2m-soc";
44
45		interrupt-parent = <&gic>;
46
47		gic: interrupt-controller@94000000 {
48			compatible = "arm,gic-v3", "arm,gic";
49			reg = <0x94000000 0x10000>,
50				<0x94100000 0x80000>;
51			interrupt-controller;
52			#interrupt-cells = <4>;
53			status = "okay";
54		};
55
56		cpu0_atcm: memory@0 {
57			compatible = "mmio-sram";
58			reg = <0x00000000 DT_SIZE_K(512)>;
59		};
60
61		cpu0_btcm: memory@100000 {
62			compatible = "mmio-sram";
63			reg = <0x00100000 DT_SIZE_K(64)>;
64		};
65
66		sram0: memory@10000000 {
67			compatible = "mmio-sram";
68			reg = <0x10000000 DT_SIZE_M(2)>;
69		};
70
71		gsc: gsc@c0060000 {
72			/* Global System Counter */
73			compatible = "syscon";
74			reg = <0xc0060000 0x30>;
75			reg-io-width = <4>;
76		};
77
78		prcrn: prcrn@80281a10 {
79			/* Non-safety area */
80			compatible = "syscon";
81			reg = <0x80281a10 0x10>;
82			reg-io-width = <4>;
83		};
84
85		prcrs: prcrs@81281a00 {
86			/* Safety area */
87			compatible = "syscon";
88			reg = <0x81281a00 0x10>;
89			reg-io-width = <4>;
90		};
91
92		sckcr: sckcr@80280000 {
93			/* System Clock Control Register*/
94			compatible = "syscon";
95			reg = <0x80280000 0x20>;
96			reg-io-width = <4>;
97		};
98
99		sckcr2: sckcr2@81280004 {
100			/* System Clock Control Register 2 */
101			compatible = "syscon";
102			reg = <0x81280004 0x1a>;
103			reg-io-width = <4>;
104		};
105
106		ns_portnf_md: ns_portnf_md@8009000c {
107			/* Interrupt edge detection setting */
108			compatible = "syscon";
109			reg = <0x8009000c 0x4>;
110			reg-io-width = <4>;
111		};
112
113		uart0: serial@80001000 {
114			compatible = "renesas,rzt2m-uart";
115			reg = <0x80001000 0x1000>;
116			current-speed = <115200>;
117			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
118					<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
119					<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
120					<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
121			interrupt-names = "rx_err", "rx", "tx", "tx_end";
122			status = "disabled";
123		};
124
125		uart3: serial@80001c00 {
126			compatible = "renesas,rzt2m-uart";
127			reg = <0x80001c00 0x1000>;
128			current-speed = <115200>;
129			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
130					<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
131					<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
132					<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
133			interrupt-names = "rx_err", "rx", "tx", "tx_end";
134			status = "disabled";
135		};
136
137		pinctrl: pinctrl@800a0000 {
138			compatible = "renesas,rzt2m-pinctrl";
139			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
140			reg-names = "port_nsr", "ptadr";
141
142			gpio_common: gpio_common {
143				compatible = "renesas,rzt2m-gpio-common";
144				interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
145					<GIC_SPI 7 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
146					<GIC_SPI 8 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
147					<GIC_SPI 9 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
148					<GIC_SPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
149					<GIC_SPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
150					<GIC_SPI 12 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
151					<GIC_SPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
152					<GIC_SPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
153					<GIC_SPI 15 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
154					<GIC_SPI 16 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
155					<GIC_SPI 17 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
156					<GIC_SPI 18 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
157					<GIC_SPI 19 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
158				#address-cells = <1>;
159				#size-cells = <0>;
160
161				gpio10: gpio@a {
162					compatible = "renesas,rzt2m-gpio";
163					gpio-controller;
164					#gpio-cells = <2>;
165					ngpios = <8>;
166					reg = <0xa>;
167					irqs = <4 11>, <5 2>;
168				};
169
170				gpio16: gpio@10 {
171					compatible = "renesas,rzt2m-gpio";
172					gpio-controller;
173					#gpio-cells = <2>;
174					ngpios = <8>;
175					reg = <0x10>;
176					irqs = <3 7>, <6 8>;
177				};
178
179				gpio19: gpio@13 {
180					compatible = "renesas,rzt2m-gpio";
181					gpio-controller;
182					#gpio-cells = <2>;
183					ngpios = <8>;
184					reg = <0x13>;
185					irqs = <2 3>;
186				};
187
188				gpio20: gpio@14 {
189					compatible = "renesas,rzt2m-gpio";
190					gpio-controller;
191					#gpio-cells = <2>;
192					ngpios = <8>;
193					reg = <0x14>;
194				};
195
196				gpio23: gpio@17 {
197					compatible = "renesas,rzt2m-gpio";
198					gpio-controller;
199					#gpio-cells = <2>;
200					ngpios = <8>;
201					reg = <0x17>;
202					irqs = <0 5>, <2 8>;
203				};
204
205			};
206		};
207	};
208};
209