1 /*
2  * Copyright (c) 2023 Nuvoton Technology Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #define DT_DRV_COMPAT nuvoton_npcx_espi_taf
8 
9 #include <soc.h>
10 #include <zephyr/drivers/espi.h>
11 #include <zephyr/drivers/espi_saf.h>
12 #include <zephyr/drivers/flash.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/logging/log.h>
15 
16 LOG_MODULE_REGISTER(espi_taf, CONFIG_ESPI_LOG_LEVEL);
17 
18 static const struct device *const spi_dev = DEVICE_DT_GET(DT_ALIAS(taf_flash));
19 
20 enum ESPI_TAF_ERASE_LEN {
21 	NPCX_ESPI_TAF_ERASE_LEN_4KB,
22 	NPCX_ESPI_TAF_ERASE_LEN_32KB,
23 	NPCX_ESPI_TAF_ERASE_LEN_64KB,
24 	NPCX_ESPI_TAF_ERASE_LEN_128KB,
25 	NPCX_ESPI_TAF_ERASE_LEN_MAX,
26 };
27 
28 struct espi_taf_npcx_config {
29 	uintptr_t base;
30 	uintptr_t mapped_addr;
31 	uintptr_t rx_plsz;
32 	enum NPCX_ESPI_TAF_ERASE_BLOCK_SIZE erase_sz;
33 	enum NPCX_ESPI_TAF_MAX_READ_REQ max_rd_sz;
34 };
35 
36 struct espi_taf_npcx_data {
37 	sys_slist_t *callbacks;
38 	const struct device *host_dev;
39 	uint8_t taf_type;
40 	uint8_t taf_tag;
41 	uint32_t address;
42 	uint16_t length;
43 	uint32_t src[16];
44 	struct k_work work;
45 };
46 
47 static struct espi_taf_npcx_data npcx_espi_taf_data;
48 static struct espi_callback espi_taf_cb;
49 
50 #define HAL_INSTANCE(dev)						\
51 	((struct espi_reg *)((const struct espi_taf_npcx_config *)	\
52 	(dev)->config)->base)
53 
54 #define FLBASE_ADDR (							\
55 	GET_FIELD(inst->FLASHBASE, NPCX_FLASHBASE_FLBASE_ADDR)		\
56 	<< GET_FIELD_POS(NPCX_FLASHBASE_FLBASE_ADDR))
57 
58 #define PRTR_BADDR(i) (							\
59 	GET_FIELD(inst->FLASH_PRTR_BADDR[i], NPCX_FLASH_PRTR_BADDR)	\
60 	<< GET_FIELD_POS(NPCX_FLASH_PRTR_BADDR))
61 
62 #define PRTR_HADDR(i) (							\
63 	GET_FIELD(inst->FLASH_PRTR_HADDR[i], NPCX_FLASH_PRTR_HADDR)	\
64 	<< GET_FIELD_POS(NPCX_FLASH_PRTR_HADDR)) | 0xFFF;
65 
espi_taf_get_pckt(const struct device * dev,struct espi_taf_npcx_data * pckt,struct espi_event event)66 static void espi_taf_get_pckt(const struct device *dev, struct espi_taf_npcx_data *pckt,
67 			      struct espi_event event)
68 {
69 	struct espi_taf_pckt *data_ptr;
70 
71 	data_ptr = (struct espi_taf_pckt *)event.evt_data;
72 
73 	pckt->taf_type = data_ptr->type;
74 	pckt->length = data_ptr->len;
75 	pckt->taf_tag = data_ptr->tag;
76 	pckt->address = data_ptr->addr;
77 
78 	if (data_ptr->type == NPCX_ESPI_TAF_REQ_WRITE) {
79 		memcpy(pckt->src, data_ptr->src, sizeof(pckt->src));
80 	}
81 }
82 
83 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
84 /* Check access region of read request is protected or not */
espi_taf_check_read_protect(const struct device * dev,uint32_t addr,uint32_t len,uint8_t tag)85 static bool espi_taf_check_read_protect(const struct device *dev, uint32_t addr, uint32_t len,
86 					uint8_t tag)
87 {
88 	struct espi_reg *const inst = HAL_INSTANCE(dev);
89 	uint32_t flash_addr = addr;
90 	uint8_t i;
91 	uint16_t override_rd;
92 	uint32_t base, high;
93 	bool rdpr;
94 
95 	flash_addr += FLBASE_ADDR;
96 
97 	for (i = 0; i < CONFIG_ESPI_TAF_PR_NUM; i++) {
98 		base = PRTR_BADDR(i);
99 		high = PRTR_HADDR(i);
100 
101 		rdpr = IS_BIT_SET(inst->FLASH_PRTR_BADDR[i], NPCX_FRGN_RPR);
102 		override_rd = GET_FIELD(inst->FLASH_RGN_TAG_OVR[i], NPCX_FLASH_TAG_OVR_RPR);
103 
104 		if (rdpr && !IS_BIT_SET(override_rd, tag) &&
105 		    (base <= flash_addr + len - 1 && flash_addr <= high)) {
106 			return true;
107 		}
108 	}
109 
110 	return false;
111 }
112 #endif
113 
114 /* Check access region of write request is protected or not */
espi_taf_check_write_protect(const struct device * dev,uint32_t addr,uint32_t len,uint8_t tag)115 static bool espi_taf_check_write_protect(const struct device *dev, uint32_t addr,
116 					 uint32_t len, uint8_t tag)
117 {
118 	struct espi_reg *const inst = HAL_INSTANCE(dev);
119 	uint32_t flash_addr = addr;
120 	uint8_t i;
121 	uint16_t override_wr;
122 	uint32_t base, high;
123 	bool wrpr;
124 
125 	flash_addr += FLBASE_ADDR;
126 
127 	for (i = 0; i < CONFIG_ESPI_TAF_PR_NUM; i++) {
128 		base = PRTR_BADDR(i);
129 		high = PRTR_HADDR(i);
130 
131 		wrpr = IS_BIT_SET(inst->FLASH_PRTR_BADDR[i], NPCX_FRGN_WPR);
132 		override_wr = GET_FIELD(inst->FLASH_RGN_TAG_OVR[i], NPCX_FLASH_TAG_OVR_WPR);
133 
134 		if (wrpr && !IS_BIT_SET(override_wr, tag) &&
135 		    (base <= flash_addr + len - 1 && flash_addr <= high)) {
136 			return true;
137 		}
138 	}
139 
140 	return false;
141 }
142 
espi_taf_npcx_configure(const struct device * dev,const struct espi_saf_cfg * cfg)143 static int espi_taf_npcx_configure(const struct device *dev, const struct espi_saf_cfg *cfg)
144 {
145 	struct espi_reg *const inst = HAL_INSTANCE(dev);
146 
147 	if (cfg->nflash_devices == 0U) {
148 		return -EINVAL;
149 	}
150 
151 #if defined(CONFIG_ESPI_TAF_AUTO_MODE)
152 	inst->FLASHCTL |= BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
153 #else
154 	inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
155 #endif
156 
157 	return 0;
158 }
159 
espi_taf_npcx_set_pr(const struct device * dev,const struct espi_saf_protection * pr)160 static int espi_taf_npcx_set_pr(const struct device *dev, const struct espi_saf_protection *pr)
161 {
162 	struct espi_reg *const inst = HAL_INSTANCE(dev);
163 	const struct espi_saf_pr *preg = pr->pregions;
164 	size_t n = pr->nregions;
165 	uint8_t regnum;
166 	uint16_t bitmask, offset;
167 	uint32_t rw_pr, override_rw;
168 
169 	if ((dev == NULL) || (pr == NULL)) {
170 		return -EINVAL;
171 	}
172 
173 	if (pr->nregions >= CONFIG_ESPI_TAF_PR_NUM) {
174 		return -EINVAL;
175 	}
176 
177 	while (n--) {
178 		regnum = preg->pr_num;
179 
180 		if (regnum >= CONFIG_ESPI_TAF_PR_NUM) {
181 			return -EINVAL;
182 		}
183 
184 		rw_pr = preg->master_bm_we << NPCX_FRGN_WPR;
185 		rw_pr = rw_pr | (preg->master_bm_rd << NPCX_FRGN_RPR);
186 
187 		if (preg->flags) {
188 			bitmask = BIT_MASK(GET_FIELD_SZ(NPCX_FLASH_PRTR_BADDR));
189 			offset = GET_FIELD_POS(NPCX_FLASH_PRTR_BADDR);
190 			inst->FLASH_PRTR_BADDR[regnum] = ((preg->start & bitmask) << offset)
191 							 | rw_pr;
192 			bitmask = BIT_MASK(GET_FIELD_SZ(NPCX_FLASH_PRTR_HADDR));
193 			offset = GET_FIELD_POS(NPCX_FLASH_PRTR_HADDR);
194 			inst->FLASH_PRTR_HADDR[regnum] = (preg->end & bitmask) << offset;
195 		}
196 
197 		override_rw = (preg->override_r << 16) | preg->override_w;
198 		inst->FLASH_RGN_TAG_OVR[regnum] = override_rw;
199 		preg++;
200 	}
201 
202 	return 0;
203 }
204 
espi_taf_npcx_activate(const struct device * dev)205 static int espi_taf_npcx_activate(const struct device *dev)
206 {
207 	struct espi_reg *const inst = HAL_INSTANCE(dev);
208 
209 	inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
210 	inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_BLK_FLASH_NP_FREE);
211 
212 	return 0;
213 }
214 
espi_taf_npcx_channel_ready(const struct device * dev)215 static bool espi_taf_npcx_channel_ready(const struct device *dev)
216 {
217 	struct espi_reg *const inst = HAL_INSTANCE(dev);
218 	uint8_t ret =
219 		GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLCAPA) & NPCX_FLASH_SHARING_CAP_SUPP_TAF;
220 
221 	if (ret != NPCX_FLASH_SHARING_CAP_SUPP_TAF) {
222 		return false;
223 	}
224 
225 	if (!device_is_ready(spi_dev)) {
226 		return false;
227 	}
228 
229 	return true;
230 }
231 
232 /* This routine set FLASH_C_AVAIL for standard request */
taf_set_flash_c_avail(const struct device * dev)233 static void taf_set_flash_c_avail(const struct device *dev)
234 {
235 	struct espi_reg *const inst = HAL_INSTANCE(dev);
236 	uint32_t tmp = inst->FLASHCTL;
237 
238 	/*
239 	 * Clear FLASHCTL_FLASH_NP_FREE to avoid host puts a flash
240 	 * standard request command at here.
241 	 */
242 	tmp &= NPCX_FLASHCTL_ACCESS_MASK;
243 
244 	/* Set FLASHCTL_FLASH_TX_AVAIL */
245 	tmp |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
246 	inst->FLASHCTL = tmp;
247 }
248 
249 /* This routine release FLASH_NP_FREE for standard request */
taf_release_flash_np_free(const struct device * dev)250 static void taf_release_flash_np_free(const struct device *dev)
251 {
252 	struct espi_reg *const inst = HAL_INSTANCE(dev);
253 	uint32_t tmp = inst->FLASHCTL;
254 
255 	/*
256 	 * Clear FLASHCTL_FLASH_TX_AVAIL to avoid host puts a
257 	 * GET_FLASH_C command at here.
258 	 */
259 	tmp &= NPCX_FLASHCTL_ACCESS_MASK;
260 
261 	/* Release FLASH_NP_FREE */
262 	tmp |= BIT(NPCX_FLASHCTL_FLASH_NP_FREE);
263 	inst->FLASHCTL = tmp;
264 }
265 
taf_npcx_completion_handler(const struct device * dev,uint8_t type,uint8_t tag,uint16_t len,uint32_t * buffer)266 static int taf_npcx_completion_handler(const struct device *dev, uint8_t type, uint8_t tag,
267 				       uint16_t len, uint32_t *buffer)
268 {
269 	struct espi_reg *const inst = HAL_INSTANCE(dev);
270 	struct npcx_taf_head taf_head;
271 	uint16_t i, size;
272 	uint32_t tx_buf[16];
273 
274 	taf_head.pkt_len = NPCX_TAF_CMP_HEADER_LEN + len;
275 	taf_head.type = type;
276 	taf_head.tag_hlen = (tag << 4) | ((len & 0xF00) >> 8);
277 	taf_head.llen = len & 0xFF;
278 
279 	memcpy(&tx_buf[0], &taf_head, sizeof(struct npcx_taf_head));
280 
281 	if (type == CYC_SCS_CMP_WITH_DATA_ONLY || type == CYC_SCS_CMP_WITH_DATA_FIRST ||
282 	    type == CYC_SCS_CMP_WITH_DATA_MIDDLE || type == CYC_SCS_CMP_WITH_DATA_LAST) {
283 		memcpy(&tx_buf[1], buffer, (uint8_t)(len));
284 	}
285 
286 	/* Check the Flash Access TX Queue is empty by polling
287 	 * FLASH_TX_AVAIL.
288 	 */
289 	if (WAIT_FOR(!IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL),
290 		     NPCX_FLASH_CHK_TIMEOUT, NULL) == false) {
291 		LOG_ERR("Check TX Queue Is Empty Timeout");
292 		return -EBUSY;
293 	}
294 
295 	/* Write packet to FLASHTXBUF */
296 	size = DIV_ROUND_UP((uint8_t)(tx_buf[0]) + 1, sizeof(uint32_t));
297 	for (i = 0; i < size; i++) {
298 		inst->FLASHTXBUF[i] = tx_buf[i];
299 	}
300 
301 	/* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
302 	taf_set_flash_c_avail(dev);
303 
304 	/* Release FLASH_NP_FREE here to ready get next TAF request */
305 	if ((type != CYC_SCS_CMP_WITH_DATA_FIRST) && (type != CYC_SCS_CMP_WITH_DATA_MIDDLE)) {
306 		taf_release_flash_np_free(dev);
307 	}
308 
309 	return 0;
310 }
311 
312 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
espi_taf_npcx_flash_read(const struct device * dev,struct espi_saf_packet * pckt)313 static int espi_taf_npcx_flash_read(const struct device *dev, struct espi_saf_packet *pckt)
314 {
315 	struct espi_reg *const inst = HAL_INSTANCE(dev);
316 	struct espi_taf_npcx_config *config = ((struct espi_taf_npcx_config *)(dev)->config);
317 	struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
318 	uint8_t cycle_type = CYC_SCS_CMP_WITH_DATA_ONLY;
319 	uint32_t total_len = pckt->len;
320 	uint32_t len = total_len;
321 	uint32_t addr = pckt->flash_addr;
322 	uint8_t flash_req_size = GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLASHREQSIZE);
323 	uint8_t target_max_size = GET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLREQSUP);
324 	uint16_t max_read_req = 32 << flash_req_size;
325 	uint8_t read_buf[64];
326 	int rc;
327 
328 	if (flash_req_size > target_max_size) {
329 		LOG_DBG("Exceeded the maximum supported length");
330 		if (target_max_size == 0) {
331 			target_max_size = 1;
332 		}
333 		max_read_req = 32 << target_max_size;
334 	}
335 
336 	if (total_len > max_read_req) {
337 		LOG_ERR("Exceeded the limitation of read length");
338 		return -EINVAL;
339 	}
340 
341 	if (espi_taf_check_read_protect(dev, addr, len, taf_data_ptr->tag)) {
342 		LOG_ERR("Access protect region");
343 		return -EINVAL;
344 	}
345 
346 	if (total_len <= config->rx_plsz) {
347 		cycle_type = CYC_SCS_CMP_WITH_DATA_ONLY;
348 		len = total_len;
349 	} else {
350 		cycle_type = CYC_SCS_CMP_WITH_DATA_FIRST;
351 		len = config->rx_plsz;
352 	}
353 
354 	do {
355 		rc = flash_read(spi_dev, addr, &read_buf[0], len);
356 		if (rc) {
357 			LOG_ERR("flash read fail 0x%x", rc);
358 			return -EIO;
359 		}
360 
361 		rc = taf_npcx_completion_handler(dev, cycle_type, taf_data_ptr->tag, len,
362 						 (uint32_t *)&read_buf[0]);
363 		if (rc) {
364 			LOG_ERR("espi taf completion handler fail");
365 			return rc;
366 		}
367 
368 		total_len -= len;
369 		addr += len;
370 
371 		if (total_len <= config->rx_plsz) {
372 			cycle_type = CYC_SCS_CMP_WITH_DATA_LAST;
373 			len = total_len;
374 		} else {
375 			cycle_type = CYC_SCS_CMP_WITH_DATA_MIDDLE;
376 		}
377 	} while (total_len);
378 
379 	return 0;
380 }
381 #endif
382 
espi_taf_npcx_flash_write(const struct device * dev,struct espi_saf_packet * pckt)383 static int espi_taf_npcx_flash_write(const struct device *dev, struct espi_saf_packet *pckt)
384 {
385 	struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
386 	uint8_t *data_ptr = (uint8_t *)(taf_data_ptr->data);
387 	int rc;
388 
389 	if (espi_taf_check_write_protect(dev, pckt->flash_addr,
390 					 pckt->len, taf_data_ptr->tag)) {
391 		LOG_ERR("Access protection region");
392 		return -EINVAL;
393 	}
394 
395 	rc = flash_write(spi_dev, pckt->flash_addr, data_ptr, pckt->len);
396 	if (rc) {
397 		LOG_ERR("flash write fail 0x%x", rc);
398 		return -EIO;
399 	}
400 
401 	rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
402 					 NULL);
403 	if (rc) {
404 		LOG_ERR("espi taf completion handler fail");
405 		return rc;
406 	}
407 
408 	return 0;
409 }
410 
espi_taf_npcx_flash_erase(const struct device * dev,struct espi_saf_packet * pckt)411 static int espi_taf_npcx_flash_erase(const struct device *dev, struct espi_saf_packet *pckt)
412 {
413 	int erase_blk[] = {KB(4), KB(32), KB(64), KB(128)};
414 	struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
415 	uint32_t addr = pckt->flash_addr;
416 	uint32_t len;
417 	int rc;
418 
419 	if ((pckt->len < 0) || (pckt->len >= NPCX_ESPI_TAF_ERASE_LEN_MAX)) {
420 		LOG_ERR("Invalid erase block size");
421 		return -EINVAL;
422 	}
423 
424 	len = erase_blk[pckt->len];
425 
426 	if (espi_taf_check_write_protect(dev, addr, len, taf_data_ptr->tag)) {
427 		LOG_ERR("Access protection region");
428 		return -EINVAL;
429 	}
430 
431 	rc = flash_erase(spi_dev, addr, len);
432 	if (rc) {
433 		LOG_ERR("flash erase fail");
434 		return -EIO;
435 	}
436 
437 	rc = taf_npcx_completion_handler(dev, CYC_SCS_CMP_WITHOUT_DATA, taf_data_ptr->tag, 0x0,
438 					 NULL);
439 	if (rc) {
440 		LOG_ERR("espi taf completion handler fail");
441 		return rc;
442 	}
443 
444 	return 0;
445 }
446 
espi_taf_npcx_flash_unsuccess(const struct device * dev,struct espi_saf_packet * pckt)447 static int espi_taf_npcx_flash_unsuccess(const struct device *dev, struct espi_saf_packet *pckt)
448 {
449 	struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
450 	int rc;
451 
452 	rc = taf_npcx_completion_handler(dev, CYC_UNSCS_CMP_WITHOUT_DATA_ONLY, taf_data_ptr->tag,
453 					 0x0, NULL);
454 	if (rc) {
455 		LOG_ERR("espi taf completion handler fail");
456 		return rc;
457 	}
458 
459 	return 0;
460 }
461 
espi_taf_work(struct k_work * item)462 static void espi_taf_work(struct k_work *item)
463 {
464 	struct espi_taf_npcx_data *info = CONTAINER_OF(item, struct espi_taf_npcx_data, work);
465 	int ret = 0;
466 
467 	struct espi_taf_npcx_pckt taf_data;
468 	struct espi_saf_packet pckt_taf;
469 
470 	pckt_taf.flash_addr = info->address;
471 	pckt_taf.len = info->length;
472 	taf_data.tag = info->taf_tag;
473 	if (info->taf_type == NPCX_ESPI_TAF_REQ_WRITE) {
474 		taf_data.data = (uint8_t *)info->src;
475 	} else {
476 		taf_data.data = NULL;
477 	}
478 	pckt_taf.buf = (uint8_t *)&taf_data;
479 
480 	switch (info->taf_type) {
481 #if defined(CONFIG_ESPI_TAF_MANUAL_MODE)
482 	case NPCX_ESPI_TAF_REQ_READ:
483 		ret = espi_taf_npcx_flash_read(info->host_dev, &pckt_taf);
484 		break;
485 #endif
486 	case NPCX_ESPI_TAF_REQ_ERASE:
487 		ret = espi_taf_npcx_flash_erase(info->host_dev, &pckt_taf);
488 		break;
489 	case NPCX_ESPI_TAF_REQ_WRITE:
490 		ret = espi_taf_npcx_flash_write(info->host_dev, &pckt_taf);
491 		break;
492 	}
493 
494 	if (ret != 0) {
495 		ret = espi_taf_npcx_flash_unsuccess(info->host_dev, &pckt_taf);
496 	}
497 }
498 
espi_taf_event_handler(const struct device * dev,struct espi_callback * cb,struct espi_event event)499 static void espi_taf_event_handler(const struct device *dev, struct espi_callback *cb,
500 				   struct espi_event event)
501 {
502 	if ((event.evt_type != ESPI_BUS_TAF_NOTIFICATION) ||
503 	    (event.evt_details != ESPI_CHANNEL_FLASH)) {
504 		return;
505 	}
506 
507 	espi_taf_get_pckt(dev, &npcx_espi_taf_data, event);
508 	k_work_submit(&npcx_espi_taf_data.work);
509 }
510 
npcx_init_taf(const struct device * dev,sys_slist_t * callbacks)511 int npcx_init_taf(const struct device *dev, sys_slist_t *callbacks)
512 {
513 	espi_init_callback(&espi_taf_cb, espi_taf_event_handler, ESPI_BUS_TAF_NOTIFICATION);
514 	espi_add_callback(dev, &espi_taf_cb);
515 
516 	npcx_espi_taf_data.host_dev = dev;
517 	npcx_espi_taf_data.callbacks = callbacks;
518 	k_work_init(&npcx_espi_taf_data.work, espi_taf_work);
519 
520 	return 0;
521 }
522 
espi_taf_npcx_init(const struct device * dev)523 static int espi_taf_npcx_init(const struct device *dev)
524 {
525 	struct espi_reg *const inst = HAL_INSTANCE(dev);
526 	struct espi_taf_npcx_config *config = ((struct espi_taf_npcx_config *)(dev)->config);
527 
528 	SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLCAPA,
529 		  NPCX_FLASH_SHARING_CAP_SUPP_TAF_AND_CAF);
530 	SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_TRGFLEBLKSIZE,
531 		  BIT(config->erase_sz));
532 	SET_FIELD(inst->FLASHCFG, NPCX_FLASHCFG_FLREQSUP,
533 		  config->max_rd_sz);
534 	inst->FLASHBASE = config->mapped_addr;
535 
536 	return 0;
537 }
538 
539 static const struct espi_saf_driver_api espi_taf_npcx_driver_api = {
540 	.config = espi_taf_npcx_configure,
541 	.set_protection_regions = espi_taf_npcx_set_pr,
542 	.activate = espi_taf_npcx_activate,
543 	.get_channel_status = espi_taf_npcx_channel_ready,
544 };
545 
546 static const struct espi_taf_npcx_config espi_taf_npcx_config = {
547 	.base = DT_INST_REG_ADDR(0),
548 	.mapped_addr = DT_INST_PROP(0, mapped_addr),
549 	.rx_plsz = DT_PROP(DT_INST_PARENT(0), rx_plsize),
550 	.erase_sz = DT_INST_STRING_TOKEN(0, erase_sz),
551 	.max_rd_sz = DT_INST_STRING_TOKEN(0, max_read_sz),
552 };
553 
554 DEVICE_DT_INST_DEFINE(0, &espi_taf_npcx_init, NULL,
555 			&npcx_espi_taf_data, &espi_taf_npcx_config,
556 			PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
557 			&espi_taf_npcx_driver_api);
558