1/*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
5 *
6 */
7
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/clock/rts5912_clock.h>
10#include <zephyr/dt-bindings/gpio/realtek-gpio.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu0: cpu@0 {
18			compatible = "arm,cortex-m33f";
19			reg = <0>;
20			cpu-power-states = <&idle &suspend_to_ram>;
21		};
22
23		power-states {
24			idle: idle {
25				compatible = "zephyr,power-state";
26				power-state-name = "suspend-to-idle";
27				min-residency-us = <100000>;
28			};
29
30			suspend_to_ram: suspend_to_ram {
31				compatible = "zephyr,power-state";
32				power-state-name = "suspend-to-ram";
33				min-residency-us = <250000>;
34			};
35		};
36	};
37
38	flash0: flash@20000400 {
39		reg = <0x20000400 0x4FC00>;
40	};
41
42	sram0: memory@20050000 {
43		compatible = "mmio-sram";
44		reg = <0x20050000 0x8000>;
45	};
46
47	clocks {
48		rc25m: rc25m {
49			compatible = "fixed-clock";
50			clock-frequency = <25000000>;
51			#clock-cells = <0>;
52		};
53
54		pll: pll {
55			compatible = "fixed-clock";
56			clock-frequency = <100000000>;
57			#clock-cells = <0>;
58		};
59	};
60
61	soc {
62		#address-cells = <1>;
63		#size-cells = <1>;
64		compatible = "simple-bus";
65		interrupt-parent = <&nvic>;
66		ranges;
67
68		bbram: bb-ram@40005000 {
69			compatible = "realtek,rts5912-bbram";
70			reg = <0x40005000 0x100>;
71			status = "okay";
72		};
73
74		sccon: clock-controller@40020000 {
75			compatible = "realtek,rts5912-sccon";
76			reg = <0x40020000 0xf0>;
77			#clock-cells = <2>;
78			clocks = <&rc25m>, <&pll>;
79			clock-names = "rc25m", "pll";
80		};
81
82		rtc: rtc@4000c100 {
83			compatible = "realtek,rts5912-rtc";
84			reg = <0x4000c100 0x20>;
85			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP2 PERIPH_GRP2_RTC_CLKPWR>;
86			clock-names = "rtc";
87			status = "disabled";
88		};
89
90		slwtmr0: slwtmr0@4000c200 {
91			compatible = "realtek,rts5912-slwtimer";
92			reg = <0x4000c200 0x10>;
93			interrupts = <202 0>;
94			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_SLWTMR0_CLKPWR>;
95			clock-names = "slwtmr";
96			max-value = <0xFFFFFFFF>;
97			clock-frequency = <1000000>;
98			prescaler = <0>;
99			status = "okay";
100		};
101
102		rtmr: rtmr@4000c500 {
103			compatible = "realtek,rts5912-rtmr";
104			reg = <0x4000c500 0x10>;
105			interrupts = <204 0>;
106			status = "okay";
107		};
108
109		uart0: uart@40010100 {
110			compatible = "ns16550";
111			reg = <0x40010100 0x100>;
112			reg-shift = <2>;
113			clock-frequency = <25000000>;
114			interrupts = <191 0>;
115			status = "disabled";
116		};
117
118		uart0_wrapper: uart_wrapper@40010200 {
119			compatible = "realtek,rts5912-uart";
120			reg = <0x40010200 0x0020>;
121			port = <0>;
122			clocks = <&sccon RTS5912_SCCON_UART UART0_CLKPWR>;
123			clock-names = "uart0";
124			status = "disabled";
125		};
126
127		pinctrl: pin-controller@40090000 {
128			compatible = "realtek,rts5912-pinctrl";
129			#address-cells = <1>;
130			#size-cells = <1>;
131			reg = <0x40090000 0x300>;
132
133			/* GPIO0-GPIO15 */
134			gpioa: gpio@40090000 {
135				compatible = "realtek,rts5912-gpio";
136				gpio-controller;
137				#gpio-cells = <2>;
138				reg = <0x40090000 0x40>;
139				ngpios = <16>;
140				interrupts = <0 0 1 0 2 0 3 0
141					      4 0 5 0 6 0 7 0
142					      8 0 9 0 10 0 11 0
143					      12 0 13 0 14 0 15 0>;
144			};
145
146			/* GPIO16-GPIO31 */
147			gpiob: gpio@40090040 {
148				compatible = "realtek,rts5912-gpio";
149				gpio-controller;
150				#gpio-cells = <2>;
151				reg = <0x40090040 0x40>;
152				ngpios = <16>;
153				interrupts = <16 0 17 0 18 0 19 0
154					      20 0 21 0 22 0 23 0
155					      24 0 25 0 26 0 27 0
156					      28 0 29 0 30 0 31 0>;
157			};
158
159			/* GPIO32-GPIO47 */
160			gpioc: gpio@40090080 {
161				compatible = "realtek,rts5912-gpio";
162				gpio-controller;
163				#gpio-cells = <2>;
164				reg = <0x40090080 0x40>;
165				ngpios = <16>;
166				interrupts = <32 0 33 0 34 0 35 0
167					      36 0 37 0 38 0 39 0
168					      40 0 41 0 42 0 43 0
169					      44 0 45 0 46 0 47 0>;
170			};
171
172			/* GPIO48-GPIO63 */
173			gpiod: gpio@400900c0 {
174				compatible = "realtek,rts5912-gpio";
175				gpio-controller;
176				#gpio-cells = <2>;
177				reg = <0x400900c0 0x40>;
178				ngpios = <16>;
179				interrupts = <48 0 49 0 50 0 51 0
180					      52 0 53 0 54 0 55 0
181					      56 0 57 0 58 0 59 0
182					      60 0 61 0 62 0 63 0>;
183			};
184
185			/* GPIO64-GPIO79 */
186			gpioe: gpio@40090100 {
187				compatible = "realtek,rts5912-gpio";
188				gpio-controller;
189				#gpio-cells = <2>;
190				reg = <0x40090100 0x40>;
191				ngpios = <16>;
192				interrupts = <64 0 65 0 66 0 67 0
193					      68 0 69 0 70 0 71 0
194					      72 0 73 0 74 0 75 0
195					      76 0 77 0 78 0 79 0>;
196			};
197
198			/* GPIO80-GPIO95 */
199			gpiof: gpio@40090140 {
200				compatible = "realtek,rts5912-gpio";
201				gpio-controller;
202				#gpio-cells = <2>;
203				reg = <0x40090140 0x40>;
204				ngpios = <16>;
205				interrupts = <80 0 81 0 82 0 83 0
206					      84 0 85 0 86 0 87 0
207					      88 0 89 0 90 0 91 0
208					      92 0 93 0 94 0 95 0>;
209			};
210
211			/* GPIO96-GPIO111 */
212			gpiog: gpio@40090180 {
213				compatible = "realtek,rts5912-gpio";
214				gpio-controller;
215				#gpio-cells = <2>;
216				reg = <0x40090180 0x40>;
217				ngpios = <16>;
218				interrupts = <96 0 97 0 98 0 99 0
219					      100 0 101 0 102 0 103 0
220					      104 0 105 0 106 0 107 0
221					      108 0 109 0 110 0 111 0>;
222			};
223
224			/* GPIO112-GPIO127 */
225			gpioh: gpio@400901c0 {
226				compatible = "realtek,rts5912-gpio";
227				gpio-controller;
228				#gpio-cells = <2>;
229				reg = <0x400901c0 0x40>;
230				ngpios = <16>;
231				interrupts = <112 0 113 0 114 0 115 0
232					      116 0 117 0 118 0 119 0
233					      120 0 121 0 122 0 123 0
234					      124 0 125 0 126 0 127 0>;
235			};
236
237			/* GPIO128-GPIO131 */
238			gpioi: gpio@40090200 {
239				compatible = "realtek,rts5912-gpio";
240				gpio-controller;
241				#gpio-cells = <2>;
242				reg = <0x40090200 0x10>;
243				ngpios = <4>;
244				interrupts = <128 0 129 0 130 0 131 0
245					      132 0 133 0 134 0 135 0
246					      136 0 137 0 138 0 139 0
247					      140 0 141 0 142 0 143 0>;
248			};
249		};
250
251		wdog: watchdog@4000c000 {
252			compatible = "realtek,rts5912-watchdog";
253			reg = <0x4000c000 0x14>;
254			interrupt-parent = <&nvic>;
255			interrupts = <209 0>;
256			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP2 PERIPH_GRP2_WDT_CLKPWR>;
257			clock-names = "watchdog";
258			clk-divider = <33>;
259			status = "disabled";
260		};
261	};
262
263	swj_port: swj-port {
264		compatible = "swj-connector";
265		pinctrl-0 = <&jtag_tdi_gpio87 &jtag_tdo_gpio88 &jtag_rst_gpio89
266			     &jtag_clk_gpio90 &jtag_tms_gpio91>;
267		pinctrl-names = "default";
268	};
269};
270
271&nvic {
272	arm,num-irq-priority-bits = <3>;
273};
274
275&systick {
276	status = "disabled";
277};
278