1 /*
2 * Copyright (c) 2019 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief System/hardware module for Nordic Semiconductor nRF53 family processor
10 *
11 * This module provides routines to initialize and support board-level hardware
12 * for the Nordic Semiconductor nRF53 family processor.
13 */
14
15 #include <zephyr/kernel.h>
16 #include <zephyr/init.h>
17 #include <zephyr/sys/barrier.h>
18 #include <zephyr/dt-bindings/regulator/nrf5x.h>
19 #include <soc/nrfx_coredep.h>
20 #include <zephyr/logging/log.h>
21 #include <nrf_erratas.h>
22 #include <hal/nrf_power.h>
23 #include <hal/nrf_ipc.h>
24 #include <helpers/nrfx_gppi.h>
25 #if defined(CONFIG_SOC_NRF5340_CPUAPP)
26 #include <zephyr/drivers/gpio.h>
27 #include <zephyr/devicetree.h>
28 #include <hal/nrf_cache.h>
29 #include <hal/nrf_gpio.h>
30 #include <hal/nrf_oscillators.h>
31 #include <hal/nrf_regulators.h>
32 #elif defined(CONFIG_SOC_NRF5340_CPUNET)
33 #include <hal/nrf_nvmc.h>
34 #endif
35 #include <hal/nrf_wdt.h>
36 #include <hal/nrf_rtc.h>
37 #include <soc_secure.h>
38
39 #include <cmsis_core.h>
40
41 #define PIN_XL1 0
42 #define PIN_XL2 1
43
44 #define RTC1_PRETICK_CC_CHAN (RTC1_CC_NUM - 1)
45
46 /* Mask of CC channels capable of generating interrupts, see nrf_rtc_timer.c */
47 #define RTC1_PRETICK_SELECTED_CC_MASK BIT_MASK(CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT + 1U)
48 #define RTC0_PRETICK_SELECTED_CC_MASK BIT_MASK(NRF_RTC_CC_COUNT_MAX)
49
50 #ifdef CONFIG_SOC_NRF5340_CPUAPP
51 #define LFXO_NODE DT_NODELABEL(lfxo)
52 #define HFXO_NODE DT_NODELABEL(hfxo)
53
54 /* LFXO config from DT */
55 #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
56 #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL
57 #elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
58 #define LFXO_CAP (DT_ENUM_IDX(LFXO_NODE, load_capacitance_picofarad) + 1U)
59 #else
60 /* LFXO config from legacy Kconfig */
61 #if defined(CONFIG_SOC_LFXO_CAP_INT_6PF)
62 #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_6PF
63 #elif defined(CONFIG_SOC_LFXO_CAP_INT_7PF)
64 #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_7PF
65 #elif defined(CONFIG_SOC_LFXO_CAP_INT_9PF)
66 #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_9PF
67 #else
68 #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL
69 #endif
70 #endif
71
72 /* HFXO config from DT */
73 #if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
74 #define HFXO_CAP_VAL_X2 (DT_PROP(HFXO_NODE, load_capacitance_femtofarad)) * 2U / 1000U
75 #elif defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
76 /* HFXO config from legacy Kconfig */
77 #define HFXO_CAP_VAL_X2 CONFIG_SOC_HFXO_CAP_INT_VALUE_X2
78 #endif
79 #endif /* CONFIG_SOC_NRF5340_CPUAPP */
80
81 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
82 LOG_MODULE_REGISTER(soc);
83
84
85 #if defined(CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND)
86 /* This code prevents the CPU from entering sleep again if it already
87 * entered sleep 5 times within last 200 us.
88 */
nrf53_anomaly_160_check(void)89 static bool nrf53_anomaly_160_check(void)
90 {
91 /* System clock cycles needed to cover 200 us window. */
92 const uint32_t window_cycles =
93 DIV_ROUND_UP(200 * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
94 1000000);
95 static uint32_t timestamps[5];
96 static bool timestamps_filled;
97 static uint8_t current;
98 uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
99 uint32_t now = k_cycle_get_32();
100
101 if (timestamps_filled &&
102 /* + 1 because only fully elapsed cycles need to be counted. */
103 (now - timestamps[oldest]) < (window_cycles + 1)) {
104 return false;
105 }
106
107 /* Check if the CPU actually entered sleep since the last visit here
108 * (WFE/WFI could return immediately if the wake-up event was already
109 * registered).
110 */
111 if (nrf_power_event_check(NRF_POWER, NRF_POWER_EVENT_SLEEPENTER)) {
112 nrf_power_event_clear(NRF_POWER, NRF_POWER_EVENT_SLEEPENTER);
113 /* If so, update the index at which the current timestamp is
114 * to be stored so that it replaces the oldest one, otherwise
115 * (when the CPU did not sleep), the recently stored timestamp
116 * is updated.
117 */
118 current = oldest;
119 if (current == 0) {
120 timestamps_filled = true;
121 }
122 }
123
124 timestamps[current] = k_cycle_get_32();
125
126 return true;
127 }
128 #endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND */
129
130 #if defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET)
131
132 BUILD_ASSERT(!IS_ENABLED(CONFIG_WDT_NRFX),
133 "For CONFIG_SOC_NRF53_RTC_PRETICK watchdog is used internally for the pre-tick workaround on nRF5340 cpunet. Application cannot use the watchdog.");
134
rtc_counter_sub(uint32_t a,uint32_t b)135 static inline uint32_t rtc_counter_sub(uint32_t a, uint32_t b)
136 {
137 return (a - b) & NRF_RTC_COUNTER_MAX;
138 }
139
rtc_ticks_to_next_event_get(NRF_RTC_Type * rtc,uint32_t selected_cc_mask,uint32_t cntr,uint32_t * ticks_to_next_event)140 static bool rtc_ticks_to_next_event_get(NRF_RTC_Type *rtc, uint32_t selected_cc_mask, uint32_t cntr,
141 uint32_t *ticks_to_next_event)
142 {
143 bool result = false;
144
145 /* Let's preload register to speed-up. */
146 uint32_t reg_intenset = rtc->INTENSET;
147
148 /* Note: TICK event not handled. */
149
150 if (reg_intenset & NRF_RTC_INT_OVERFLOW_MASK) {
151 /* Overflow can generate an interrupt. */
152 *ticks_to_next_event = NRF_RTC_COUNTER_MAX + 1U - cntr;
153 result = true;
154 }
155
156 for (uint32_t chan = 0; chan < NRF_RTC_CC_COUNT_MAX; chan++) {
157 if ((selected_cc_mask & (1U << chan)) &&
158 (reg_intenset & NRF_RTC_CHANNEL_INT_MASK(chan))) {
159 /* The CC is in selected mask and is can generate an interrupt. */
160 uint32_t cc = nrf_rtc_cc_get(rtc, chan);
161 uint32_t ticks_to_fire = rtc_counter_sub(cc, cntr);
162
163 if (ticks_to_fire == 0U) {
164 /* When ticks_to_fire == 0, the event should have been just
165 * generated the interrupt can be already handled or be pending.
166 * However the next event is expected to be after counter wraps.
167 */
168 ticks_to_fire = NRF_RTC_COUNTER_MAX + 1U;
169 }
170
171 if (!result) {
172 *ticks_to_next_event = ticks_to_fire;
173 result = true;
174 } else if (ticks_to_fire < *ticks_to_next_event) {
175 *ticks_to_next_event = ticks_to_fire;
176 result = true;
177 } else {
178 /* CC that fires no earlier than already found. */
179 }
180 }
181 }
182
183 return result;
184 }
185
rtc_counter_synchronized_get(NRF_RTC_Type * rtc_a,NRF_RTC_Type * rtc_b,uint32_t * counter_a,uint32_t * counter_b)186 static void rtc_counter_synchronized_get(NRF_RTC_Type *rtc_a, NRF_RTC_Type *rtc_b,
187 uint32_t *counter_a, uint32_t *counter_b)
188 {
189 do {
190 *counter_a = nrf_rtc_counter_get(rtc_a);
191 barrier_dmem_fence_full();
192 *counter_b = nrf_rtc_counter_get(rtc_b);
193 barrier_dmem_fence_full();
194 } while (*counter_a != nrf_rtc_counter_get(rtc_a));
195 }
196
197 static uint8_t cpu_idle_prepare_monitor_dummy;
198 static bool cpu_idle_prepare_allows_sleep;
199
cpu_idle_prepare_monitor_begin(void)200 static void cpu_idle_prepare_monitor_begin(void)
201 {
202 __LDREXB(&cpu_idle_prepare_monitor_dummy);
203 }
204
205 /* Returns 0 if no exception preempted since the last call to cpu_idle_prepare_monitor_begin. */
cpu_idle_prepare_monitor_end(void)206 static bool cpu_idle_prepare_monitor_end(void)
207 {
208 /* The value stored is irrelevant. If any exception took place after
209 * cpu_idle_prepare_monitor_begin, the local monitor is cleared and
210 * the store fails returning 1.
211 * See Arm v8-M Architecture Reference Manual:
212 * Chapter B9.2 The local monitors
213 * Chapter B9.4 Exclusive access instructions and the monitors
214 * See Arm Cortex-M33 Processor Technical Reference Manual
215 * Chapter 3.5 Exclusive monitor
216 */
217 return __STREXB(0U, &cpu_idle_prepare_monitor_dummy);
218 }
219
rtc_pretick_finish_previous(void)220 static void rtc_pretick_finish_previous(void)
221 {
222 NRF_IPC->PUBLISH_RECEIVE[CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET] &=
223 ~IPC_PUBLISH_RECEIVE_EN_Msk;
224
225 nrf_rtc_event_clear(NRF_RTC1, NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN));
226 }
227
228
z_arm_on_enter_cpu_idle_prepare(void)229 void z_arm_on_enter_cpu_idle_prepare(void)
230 {
231 bool ok_to_sleep = true;
232
233 cpu_idle_prepare_monitor_begin();
234
235 uint32_t rtc_counter = 0U;
236 uint32_t rtc_ticks_to_next_event = 0U;
237 uint32_t rtc0_counter = 0U;
238 uint32_t rtc0_ticks_to_next_event = 0U;
239
240 rtc_counter_synchronized_get(NRF_RTC1, NRF_RTC0, &rtc_counter, &rtc0_counter);
241
242 bool rtc_scheduled = rtc_ticks_to_next_event_get(NRF_RTC1, RTC1_PRETICK_SELECTED_CC_MASK,
243 rtc_counter, &rtc_ticks_to_next_event);
244
245 if (rtc_ticks_to_next_event_get(NRF_RTC0, RTC0_PRETICK_SELECTED_CC_MASK, rtc0_counter,
246 &rtc0_ticks_to_next_event)) {
247 /* An event is scheduled on RTC0. */
248 if (!rtc_scheduled) {
249 rtc_ticks_to_next_event = rtc0_ticks_to_next_event;
250 rtc_scheduled = true;
251 } else if (rtc0_ticks_to_next_event < rtc_ticks_to_next_event) {
252 rtc_ticks_to_next_event = rtc0_ticks_to_next_event;
253 } else {
254 /* Event on RTC0 will not happen earlier than already found. */
255 }
256 }
257
258 if (rtc_scheduled) {
259 static bool rtc_pretick_cc_set_on_time;
260 /* The pretick should happen 1 tick before the earliest scheduled event
261 * that can trigger an interrupt.
262 */
263 uint32_t rtc_pretick_cc_val = (rtc_counter + rtc_ticks_to_next_event - 1U)
264 & NRF_RTC_COUNTER_MAX;
265
266 if (rtc_pretick_cc_val != nrf_rtc_cc_get(NRF_RTC1, RTC1_PRETICK_CC_CHAN)) {
267 /* The CC for pretick needs to be updated. */
268 rtc_pretick_finish_previous();
269 nrf_rtc_cc_set(NRF_RTC1, RTC1_PRETICK_CC_CHAN, rtc_pretick_cc_val);
270
271 if (rtc_ticks_to_next_event >= NRF_RTC_COUNTER_MAX/2) {
272 /* Pretick is scheduled so far in the future, assumed on time. */
273 rtc_pretick_cc_set_on_time = true;
274 } else {
275 /* Let's check if we updated CC on time, so that the CC can
276 * take effect.
277 */
278 barrier_dmem_fence_full();
279 rtc_counter = nrf_rtc_counter_get(NRF_RTC1);
280 uint32_t pretick_cc_to_counter =
281 rtc_counter_sub(rtc_pretick_cc_val, rtc_counter);
282
283 if ((pretick_cc_to_counter < 3) ||
284 (pretick_cc_to_counter >= NRF_RTC_COUNTER_MAX/2)) {
285 /* The COUNTER value is close enough to the expected
286 * pretick CC or has just expired, so the pretick event
287 * generation is not guaranteed.
288 */
289 rtc_pretick_cc_set_on_time = false;
290 } else {
291 /* The written rtc_pretick_cc is guaranteed to trigger
292 * compare event.
293 */
294 rtc_pretick_cc_set_on_time = true;
295 }
296 }
297 } else {
298 /* The CC for pretick doesn't need to be updated, however
299 * rtc_pretick_cc_set_on_time still holds if we managed to set it on time.
300 */
301 }
302
303 /* If the CC for pretick is set on time, so the pretick CC event can be reliably
304 * generated then allow to sleep. Otherwise (the CC for pretick cannot be reliably
305 * generated, because CC was set very short to it's fire time) sleep not at all.
306 */
307 ok_to_sleep = rtc_pretick_cc_set_on_time;
308 } else {
309 /* No events on any RTC timers are scheduled. */
310 }
311
312 if (ok_to_sleep) {
313 NRF_IPC->PUBLISH_RECEIVE[CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET] |=
314 IPC_PUBLISH_RECEIVE_EN_Msk;
315 if (!nrf_rtc_event_check(NRF_RTC1,
316 NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN))) {
317 NRF_WDT->TASKS_STOP = 1;
318 /* Check if any event did not occur after we checked for
319 * stopping condition. If yes, we might have stopped WDT
320 * when it should be running. Restart it.
321 */
322 if (nrf_rtc_event_check(NRF_RTC1,
323 NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN))) {
324 NRF_WDT->TASKS_START = 1;
325 }
326 }
327 }
328
329 cpu_idle_prepare_allows_sleep = ok_to_sleep;
330 }
331 #endif /* CONFIG_SOC_NRF53_RTC_PRETICK && CONFIG_SOC_NRF5340_CPUNET */
332
333 #if defined(CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND) || \
334 (defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET))
z_arm_on_enter_cpu_idle(void)335 bool z_arm_on_enter_cpu_idle(void)
336 {
337 bool ok_to_sleep = true;
338
339 #if defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET)
340 if (cpu_idle_prepare_monitor_end() == 0) {
341 /* No exception happened since cpu_idle_prepare_monitor_begin.
342 * We can trust the outcome of. z_arm_on_enter_cpu_idle_prepare
343 */
344 ok_to_sleep = cpu_idle_prepare_allows_sleep;
345 } else {
346 /* Exception happened since cpu_idle_prepare_monitor_begin.
347 * The values which z_arm_on_enter_cpu_idle_prepare could be changed
348 * by the exception, so we can not trust to it's outcome.
349 * Do not sleep at all, let's try in the next iteration of idle loop.
350 */
351 ok_to_sleep = false;
352 }
353 #endif
354
355 #if defined(CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND)
356 if (ok_to_sleep) {
357 ok_to_sleep = nrf53_anomaly_160_check();
358
359 #if (LOG_LEVEL >= LOG_LEVEL_DBG)
360 static bool suppress_message;
361
362 if (ok_to_sleep) {
363 suppress_message = false;
364 } else if (!suppress_message) {
365 LOG_DBG("Anomaly 160 trigger conditions detected.");
366 suppress_message = true;
367 }
368 #endif
369 }
370 #endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND */
371
372 #if defined(CONFIG_SOC_NRF53_RTC_PRETICK) && defined(CONFIG_SOC_NRF5340_CPUNET)
373 if (!ok_to_sleep) {
374 NRF_IPC->PUBLISH_RECEIVE[CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET] &=
375 ~IPC_PUBLISH_RECEIVE_EN_Msk;
376 NRF_WDT->TASKS_STOP = 1;
377 }
378 #endif
379
380 return ok_to_sleep;
381 }
382 #endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND ||
383 * (CONFIG_SOC_NRF53_RTC_PRETICK && CONFIG_SOC_NRF5340_CPUNET)
384 */
385
386 #if CONFIG_SOC_NRF53_RTC_PRETICK
387 #ifdef CONFIG_SOC_NRF5340_CPUAPP
388 /* RTC pretick - application core part. */
rtc_pretick_cpuapp_init(void)389 static int rtc_pretick_cpuapp_init(void)
390 {
391 uint8_t ch;
392 nrfx_err_t err;
393 nrf_ipc_event_t ipc_event =
394 nrf_ipc_receive_event_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET);
395 nrf_ipc_task_t ipc_task =
396 nrf_ipc_send_task_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET);
397 uint32_t task_ipc = nrf_ipc_task_address_get(NRF_IPC, ipc_task);
398 uint32_t evt_ipc = nrf_ipc_event_address_get(NRF_IPC, ipc_event);
399
400 err = nrfx_gppi_channel_alloc(&ch);
401 if (err != NRFX_SUCCESS) {
402 return -ENOMEM;
403 }
404
405 nrf_ipc_receive_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET,
406 BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET));
407 nrf_ipc_send_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET,
408 BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET));
409
410 nrfx_gppi_task_endpoint_setup(ch, task_ipc);
411 nrfx_gppi_event_endpoint_setup(ch, evt_ipc);
412 nrfx_gppi_channels_enable(BIT(ch));
413
414 return 0;
415 }
416 #else /* CONFIG_SOC_NRF5340_CPUNET */
417
rtc_pretick_rtc0_isr_hook(void)418 void rtc_pretick_rtc0_isr_hook(void)
419 {
420 rtc_pretick_finish_previous();
421 }
422
rtc_pretick_rtc1_isr_hook(void)423 void rtc_pretick_rtc1_isr_hook(void)
424 {
425 rtc_pretick_finish_previous();
426 }
427
rtc_pretick_cpunet_init(void)428 static int rtc_pretick_cpunet_init(void)
429 {
430 uint8_t ppi_ch;
431 nrf_ipc_task_t ipc_task =
432 nrf_ipc_send_task_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET);
433 nrf_ipc_event_t ipc_event =
434 nrf_ipc_receive_event_get(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET);
435 uint32_t task_ipc = nrf_ipc_task_address_get(NRF_IPC, ipc_task);
436 uint32_t evt_ipc = nrf_ipc_event_address_get(NRF_IPC, ipc_event);
437 uint32_t task_wdt = nrf_wdt_task_address_get(NRF_WDT, NRF_WDT_TASK_START);
438 uint32_t evt_cc = nrf_rtc_event_address_get(NRF_RTC1,
439 NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN));
440
441 /* Configure Watchdog to allow stopping. */
442 nrf_wdt_behaviour_set(NRF_WDT, WDT_CONFIG_STOPEN_Msk | BIT(4));
443 *((volatile uint32_t *)0x41203120) = 0x14;
444
445 /* Configure IPC */
446 nrf_ipc_receive_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET,
447 BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET));
448 nrf_ipc_send_config_set(NRF_IPC, CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET,
449 BIT(CONFIG_SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET));
450
451 /* Allocate PPI channel for RTC Compare event publishers that starts WDT. */
452 nrfx_err_t err = nrfx_gppi_channel_alloc(&ppi_ch);
453
454 if (err != NRFX_SUCCESS) {
455 return -ENOMEM;
456 }
457
458 nrfx_gppi_event_endpoint_setup(ppi_ch, evt_cc);
459 nrfx_gppi_task_endpoint_setup(ppi_ch, task_ipc);
460 nrfx_gppi_event_endpoint_setup(ppi_ch, evt_ipc);
461 nrfx_gppi_task_endpoint_setup(ppi_ch, task_wdt);
462 nrfx_gppi_channels_enable(BIT(ppi_ch));
463
464 nrf_rtc_event_enable(NRF_RTC1, NRF_RTC_CHANNEL_INT_MASK(RTC1_PRETICK_CC_CHAN));
465 nrf_rtc_event_clear(NRF_RTC1, NRF_RTC_CHANNEL_EVENT_ADDR(RTC1_PRETICK_CC_CHAN));
466
467 return 0;
468 }
469 #endif /* CONFIG_SOC_NRF5340_CPUNET */
470
rtc_pretick_init(void)471 static int rtc_pretick_init(void)
472 {
473 #ifdef CONFIG_SOC_NRF5340_CPUAPP
474 return rtc_pretick_cpuapp_init();
475 #else
476 return rtc_pretick_cpunet_init();
477 #endif
478 }
479 #endif /* CONFIG_SOC_NRF53_RTC_PRETICK */
480
481
nordicsemi_nrf53_init(void)482 static int nordicsemi_nrf53_init(void)
483 {
484 #if defined(CONFIG_SOC_NRF5340_CPUAPP) && defined(CONFIG_NRF_ENABLE_CACHE)
485 #if !defined(CONFIG_BUILD_WITH_TFM)
486 /* Enable the instruction & data cache.
487 * This can only be done from secure code.
488 * This is handled by the TF-M platform so we skip it when TF-M is
489 * enabled.
490 */
491 nrf_cache_enable(NRF_CACHE);
492 #endif
493 #elif defined(CONFIG_SOC_NRF5340_CPUNET) && defined(CONFIG_NRF_ENABLE_CACHE)
494 nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE);
495 #endif
496
497 #ifdef CONFIG_SOC_NRF5340_CPUAPP
498 #if defined(LFXO_CAP)
499 nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, LFXO_CAP);
500 #if !defined(CONFIG_BUILD_WITH_TFM)
501 /* This can only be done from secure code.
502 * This is handled by the TF-M platform so we skip it when TF-M is
503 * enabled.
504 */
505 nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
506 nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);
507 #endif /* !defined(CONFIG_BUILD_WITH_TFM) */
508 #endif /* defined(LFXO_CAP) */
509 #if defined(HFXO_CAP_VAL_X2)
510 /* This register is only accessible from secure code. */
511 uint32_t xosc32mtrim = soc_secure_read_xosc32mtrim();
512 /* The SLOPE field is in the two's complement form, hence this special
513 * handling. Ideally, it would result in just one SBFX instruction for
514 * extracting the slope value, at least gcc is capable of producing such
515 * output, but since the compiler apparently tries first to optimize
516 * additions and subtractions, it generates slightly less than optimal
517 * code.
518 */
519 uint32_t slope_field = (xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk)
520 >> FICR_XOSC32MTRIM_SLOPE_Pos;
521 uint32_t slope_mask = FICR_XOSC32MTRIM_SLOPE_Msk
522 >> FICR_XOSC32MTRIM_SLOPE_Pos;
523 uint32_t slope_sign = (slope_mask - (slope_mask >> 1));
524 int32_t slope = (int32_t)(slope_field ^ slope_sign) - (int32_t)slope_sign;
525 uint32_t offset = (xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk)
526 >> FICR_XOSC32MTRIM_OFFSET_Pos;
527 /* As specified in the nRF5340 PS:
528 * CAPVALUE = (((FICR->XOSC32MTRIM.SLOPE+56)*(CAPACITANCE*2-14))
529 * +((FICR->XOSC32MTRIM.OFFSET-8)<<4)+32)>>6;
530 * where CAPACITANCE is the desired capacitor value in pF, holding any
531 * value between 7.0 pF and 20.0 pF in 0.5 pF steps.
532 */
533 uint32_t capvalue =
534 ((slope + 56) * (HFXO_CAP_VAL_X2 - 14)
535 + ((offset - 8) << 4) + 32) >> 6;
536
537 nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, capvalue);
538 #elif defined(CONFIG_SOC_HFXO_CAP_EXTERNAL) || \
539 DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, external)
540 nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
541 #endif
542 #endif /* CONFIG_SOC_NRF5340_CPUAPP */
543
544 #if defined(CONFIG_SOC_DCDC_NRF53X_APP) || \
545 (DT_PROP(DT_NODELABEL(vregmain), regulator_initial_mode) == NRF5X_REG_MODE_DCDC)
546 nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true);
547 #endif
548 #if defined(CONFIG_SOC_DCDC_NRF53X_NET) || \
549 (DT_PROP(DT_NODELABEL(vregradio), regulator_initial_mode) == NRF5X_REG_MODE_DCDC)
550 nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_RADIO, true);
551 #endif
552 #if defined(CONFIG_SOC_DCDC_NRF53X_HV) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vregh))
553 nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_HIGH, true);
554 #endif
555
556 return 0;
557 }
558
arch_busy_wait(uint32_t time_us)559 void arch_busy_wait(uint32_t time_us)
560 {
561 nrfx_coredep_delay_us(time_us);
562 }
563
564 SYS_INIT(nordicsemi_nrf53_init, PRE_KERNEL_1, 0);
565
566 #ifdef CONFIG_SOC_NRF53_RTC_PRETICK
567 SYS_INIT(rtc_pretick_init, POST_KERNEL, 0);
568 #endif
569
