1 /*
2 * Copyright (c) 2024 Junho Lee <junho@tsnlab.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT raspberrypi_rp1_gpio
8
9 #include <zephyr/arch/common/sys_bitops.h>
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/device.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/drivers/gpio/gpio_utils.h>
14
15 #define GPIO_STATUS(base, n) (base + 0x8 * n)
16 #define GPIO_CTRL(base, n) (GPIO_STATUS(base, n) + 0x4)
17
18 #define GPIO_STATUS_OUT_TO_PAD 0x200
19 #define GPIO_STATUS_OUT_FROM_PERI 0x100
20
21 #define GPIO_CTRL_OUTOVER_MASK 0x3000
22 #define GPIO_CTRL_OUTOVER_PERI 0x0
23
24 #define GPIO_CTRL_OEOVER_MASK 0xc000
25 #define GPIO_CTRL_OEOVER_PERI 0x0
26
27 #define GPIO_CTRL_FUNCSEL_MASK 0x001f
28 #define GPIO_CTRL_FUNCSEL_RIO 0x5
29
30 #define RIO_OUT(base) (base)
31 #define RIO_OE(base) (base + 0x4)
32 #define RIO_IN(base) (base + 0x8)
33
34 #define RIO_SET 0x2000
35 #define RIO_CLR 0x3000
36
37 #define RIO_OUT_SET(base) (RIO_OUT(base) + RIO_SET)
38 #define RIO_OUT_CLR(base) (RIO_OUT(base) + RIO_CLR)
39
40 #define RIO_OE_SET(base) (RIO_OE(base) + RIO_SET)
41 #define RIO_OE_CLR(base) (RIO_OE(base) + RIO_CLR)
42
43 #define PADS_CTRL(base, n) (base + 0x4 * (n + 1))
44
45 #define PADS_OUTPUT_DISABLE 0x80
46 #define PADS_INPUT_ENABLE 0x40
47
48 #define PADS_PULL_UP_ENABLE 0x8
49 #define PADS_PULL_DOWN_ENABLE 0x4
50
51 #define DEV_CFG(dev) ((const struct gpio_rp1_config *)(dev)->config)
52 #define DEV_DATA(dev) ((struct gpio_rp1_data *)(dev)->data)
53
54 struct gpio_rp1_config {
55 struct gpio_driver_config common;
56
57 DEVICE_MMIO_NAMED_ROM(reg_base);
58 mem_addr_t gpio_offset;
59 mem_addr_t rio_offset;
60 mem_addr_t pads_offset;
61
62 uint8_t ngpios;
63 };
64
65 struct gpio_rp1_data {
66 struct gpio_driver_data common;
67
68 DEVICE_MMIO_NAMED_RAM(reg_base);
69 mem_addr_t gpio_base;
70 mem_addr_t rio_base;
71 mem_addr_t pads_base;
72 };
73
gpio_rp1_pin_configure(const struct device * port,gpio_pin_t pin,gpio_flags_t flags)74 static int gpio_rp1_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags)
75 {
76 struct gpio_rp1_data *data = port->data;
77
78 if (flags & GPIO_SINGLE_ENDED) {
79 return -ENOTSUP;
80 }
81
82 /* Let RIO handle the input/output of GPIO */
83 sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OEOVER_MASK);
84 sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OEOVER_PERI);
85
86 sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OUTOVER_MASK);
87 sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OUTOVER_PERI);
88
89 sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_FUNCSEL_MASK);
90 sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_FUNCSEL_RIO);
91
92 /* Set the direction */
93 if (flags & GPIO_OUTPUT) {
94 sys_set_bit(RIO_OE_SET(data->rio_base), pin);
95 sys_clear_bits(PADS_CTRL(data->pads_base, pin),
96 PADS_OUTPUT_DISABLE | PADS_INPUT_ENABLE);
97
98 if (flags & GPIO_OUTPUT_INIT_HIGH) {
99 sys_set_bit(RIO_OUT_SET(data->rio_base), pin);
100 sys_clear_bit(RIO_OUT_CLR(data->rio_base), pin);
101 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
102 sys_set_bit(RIO_OUT_CLR(data->rio_base), pin);
103 sys_clear_bit(RIO_OUT_SET(data->rio_base), pin);
104 }
105 } else if (flags & GPIO_INPUT) {
106 sys_set_bit(RIO_OE_CLR(data->rio_base), pin);
107 sys_set_bits(PADS_CTRL(data->pads_base, pin),
108 PADS_OUTPUT_DISABLE | PADS_INPUT_ENABLE);
109 }
110
111 /* Set pull up/down */
112 sys_clear_bits(PADS_CTRL(data->pads_base, pin),
113 PADS_PULL_UP_ENABLE | PADS_PULL_DOWN_ENABLE);
114
115 if (flags & GPIO_PULL_UP) {
116 sys_set_bits(PADS_CTRL(data->pads_base, pin), PADS_PULL_UP_ENABLE);
117 } else if (flags & GPIO_PULL_DOWN) {
118 sys_set_bits(PADS_CTRL(data->pads_base, pin), PADS_PULL_DOWN_ENABLE);
119 }
120
121 return 0;
122 }
123
gpio_rp1_port_get_raw(const struct device * port,gpio_port_value_t * value)124 static int gpio_rp1_port_get_raw(const struct device *port, gpio_port_value_t *value)
125 {
126 struct gpio_rp1_data *data = port->data;
127
128 *value = sys_read32(RIO_IN(data->rio_base));
129
130 return 0;
131 }
132
gpio_rp1_port_set_masked_raw(const struct device * port,gpio_port_pins_t mask,gpio_port_value_t value)133 static int gpio_rp1_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask,
134 gpio_port_value_t value)
135 {
136 struct gpio_rp1_data *data = port->data;
137
138 sys_clear_bits(RIO_OUT_SET(data->rio_base), mask);
139 sys_set_bits(RIO_OUT_CLR(data->rio_base), mask);
140
141 sys_clear_bits(RIO_OUT_CLR(data->rio_base), (value & mask));
142 sys_set_bits(RIO_OUT_SET(data->rio_base), (value & mask));
143
144 return 0;
145 }
146
gpio_rp1_port_set_bits_raw(const struct device * port,gpio_port_pins_t pins)147 static int gpio_rp1_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins)
148 {
149 struct gpio_rp1_data *data = port->data;
150
151 sys_clear_bits(RIO_OUT_CLR(data->rio_base), pins);
152 sys_set_bits(RIO_OUT_SET(data->rio_base), pins);
153
154 return 0;
155 }
156
gpio_rp1_port_clear_bits_raw(const struct device * port,gpio_port_pins_t pins)157 static int gpio_rp1_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins)
158 {
159 struct gpio_rp1_data *data = port->data;
160
161 sys_clear_bits(RIO_OUT_SET(data->rio_base), pins);
162 sys_set_bits(RIO_OUT_CLR(data->rio_base), pins);
163
164 return 0;
165 }
166
gpio_rp1_port_toggle_bits(const struct device * port,gpio_port_pins_t pins)167 static int gpio_rp1_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
168 {
169 struct gpio_rp1_data *data = port->data;
170 uint32_t val;
171
172 val = sys_read32(RIO_OUT(data->rio_base));
173
174 /* Low to high */
175 sys_set_bits(RIO_OUT_SET(data->rio_base), val ^ pins);
176 sys_clear_bits(RIO_OUT_CLR(data->rio_base), val ^ pins);
177
178 /* High to low */
179 sys_set_bits(RIO_OUT_CLR(data->rio_base), val & pins);
180 sys_clear_bits(RIO_OUT_SET(data->rio_base), val & pins);
181
182 return 0;
183 }
184
185 static DEVICE_API(gpio, gpio_rp1_api) = {
186 .pin_configure = gpio_rp1_pin_configure,
187 .port_get_raw = gpio_rp1_port_get_raw,
188 .port_set_masked_raw = gpio_rp1_port_set_masked_raw,
189 .port_set_bits_raw = gpio_rp1_port_set_bits_raw,
190 .port_clear_bits_raw = gpio_rp1_port_clear_bits_raw,
191 .port_toggle_bits = gpio_rp1_port_toggle_bits,
192 };
193
gpio_rp1_init(const struct device * port)194 static int gpio_rp1_init(const struct device *port)
195 {
196 const struct gpio_rp1_config *config = port->config;
197 struct gpio_rp1_data *data = port->data;
198
199 DEVICE_MMIO_NAMED_MAP(port, reg_base, K_MEM_CACHE_NONE);
200 data->gpio_base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->gpio_offset;
201 data->rio_base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->rio_offset;
202 data->pads_base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->pads_offset;
203
204 return 0;
205 }
206
207 #define GPIO_RP1_INIT(n) \
208 static struct gpio_rp1_data gpio_rp1_data_##n; \
209 \
210 static const struct gpio_rp1_config gpio_rp1_cfg_##n = { \
211 .common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0)}, \
212 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_INST_PARENT(n)), \
213 .gpio_offset = DT_INST_REG_ADDR_BY_IDX(n, 0), \
214 .rio_offset = DT_INST_REG_ADDR_BY_IDX(n, 1), \
215 .pads_offset = DT_INST_REG_ADDR_BY_IDX(n, 2), \
216 .ngpios = DT_INST_PROP(n, ngpios), \
217 }; \
218 \
219 DEVICE_DT_INST_DEFINE(n, gpio_rp1_init, NULL, &gpio_rp1_data_##n, &gpio_rp1_cfg_##n, \
220 POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rp1_api);
221
222 DT_INST_FOREACH_STATUS_OKAY(GPIO_RP1_INIT)
223
