1 /* 2 * Copyright 2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 */ 8 9 #ifndef FSL_FLASH_FFR_H_ 10 #define FSL_FLASH_FFR_H_ 11 12 #include "fsl_flash.h" 13 14 /*! 15 * @addtogroup flash_ffr_driver 16 * @{ 17 */ 18 19 /*! @file */ 20 21 /******************************************************************************* 22 * Definitions 23 ******************************************************************************/ 24 25 /*! @brief Alignment(down) utility. */ 26 #if !defined(ALIGN_DOWN) 27 #define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) 28 #endif 29 30 /*! @brief Alignment(up) utility. */ 31 #if !defined(ALIGN_UP) 32 #define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) 33 #endif 34 35 #define FLASH_FFR_MAX_PAGE_SIZE (512u) 36 #define FLASH_FFR_CUST_ADDRESS (0x200U) 37 #define FLASH_FFR_CUST_PAGE_NUMBER (15u) 38 39 #define FLASH_FFR_HASH_DIGEST_SIZE (32u) 40 #define FLASH_FFR_IV_CODE_SIZE (52u) 41 #define FLASH_FFR_KETBLOB_OFFSET (0x160u) 42 #define FLASH_FFR_KETBLOB_SIZE (0x30u) 43 #define CFPA_HEADER_MARKER (0x9635u) 44 #define CMPA_HEADER_MARKER (0x5963u) 45 #define FLASH_FFR_UUID_SIZE (16u) 46 enum flash_ffr_page_offset 47 { 48 kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ 49 kFfrPageOffset_CFPA_CfgPing = 0, /*!< CFPA Configuration area (Ping page)*/ 50 kFfrPageOffset_CFPA_CfgPong = 1, /*!< Same as CFPA page (Pong page)*/ 51 kFfrPageOffset_CMPA_Cfg = 2, /*!< Customer Manufacturing programmed area*/ 52 kFfrPageOffset_NMPA_Cfg = 3, /*!< Customer Manufacturing programmed area*/ 53 kFfrPageOffset_SBL_Cfg = 4, /*!< SBL recovery programmed area*/ 54 kFfrPageOffset_B0_IFR1_Visible = 128, /*!< Trim programmed area*/ 55 56 }; 57 58 enum flash_ffr_page_num 59 { 60 kFfrSectorNum_CFPA = 2, /*!< Customer In-Field programmed area*/ 61 kFfrSectorNum_CMPA = 1, /*!< Customer Manufacturing programmed area*/ 62 kFfrSectorNum_NMPA = 1, /*!< NXP Manufacturing programmed area*/ 63 kFfrSectorNum_SBL = 4, /*!< SBL Cus programmed area*/ 64 kFfrSectorNum_Total = (kFfrSectorNum_CFPA + kFfrSectorNum_CMPA + kFfrSectorNum_NMPA + kFfrSectorNum_SBL), 65 }; 66 67 enum flash_ffr_block_size 68 { 69 kFfrBlockSize_Key = 52u, 70 kFfrBlockSize_ActivationCode = 1000u, 71 }; 72 73 enum cfpa_cfg_cmpa_prog_status 74 { 75 kFfrCmpaProgStatus_Idle = 0x0u, 76 kFfrCmpaProgStatus_InProgress = 0x5CC55AA5u, 77 }; 78 79 typedef enum 80 { 81 kFfrCmpaProgProcess_Pre = 0x0u, 82 kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, 83 } cmpa_prog_process_t; 84 85 typedef struct 86 { 87 struct 88 { 89 uint32_t cfpa_lc_state : 8; 90 uint32_t cfpa_lc_state_inv : 8; 91 uint32_t header_marker : 16; 92 } header; //!< [0x000-0x003] 93 94 struct //!< [0x004-0x007] 95 { 96 uint32_t version : 24; //!< cfpa version 97 uint32_t img_upd : 2; //!< image cmac update 98 uint32_t reserved0 : 1; 99 uint32_t cmpa_update : 3; //!< CFPA page updated through SB command. 100 uint32_t reserved1 : 1; 101 uint32_t dice_en : 1; //!< Update DICE certificate during next boot 102 } cfpa_page_version; 103 104 uint32_t secureFwVersion; //!< [0x008-0x00b] 105 uint32_t nsFwVersion; //!< [0x00c-0x00f] 106 uint32_t recFwVersion; //!< [0x010-0x013] 107 uint32_t secBootFlags; //!< [0x014-0x01f] 108 uint32_t imageKeyRevoke; //!< [0x018-0x01b] 109 uint32_t lpVectorAddr; //!< [0x01c-0x01f] 110 uint32_t vendorUsage; //!< [0x020-0x02f] 111 uint32_t dcfgNsPin; //!< [0x024-0x027] 112 uint32_t dcfgNsDflt; //!< [0x028-0x02b] 113 uint32_t reserved0; //!< [0x02c-0x02f] 114 uint32_t ivPrince[4]; //!< [0x030-0x03f] 115 uint32_t ivIped[8]; //!< [0x040-0x05f] 116 117 uint32_t errCnt[8]; //!< [0x060-0x07f] 118 119 uint32_t custCtr[8]; //!< [0x080-0x09f] 120 uint32_t mflagCtr[8]; //!< [0x0a0-0x0bf] 121 uint32_t flashAcl[8]; //!< [0x0C0-0x0Df] 122 uint32_t sblImg0Cmac[4]; //!< [0x0E0-0x0Ef] 123 uint32_t img1Cmac[4]; //!< [0x0F0-0x0Ff] 124 uint32_t diceCert[36]; //!< [0x100-0x18f] 125 uint32_t reserved2[23]; //!< [0x190-0x1eb] 126 uint32_t cfpaCrc; //!< [0x1ec-0x1ef] 127 uint32_t cfpaCmac[4]; //!< [0x1f0-0x1ff] 128 } cfpa_cfg_info_t; 129 130 #define FFR_BOOTCFG_USBSPEED_SHIFT (9U) 131 #define FFR_BOOTCFG_USBSPEED_MASK (0x3u << FFR_BOOTCFG_USBSPEED_SHIFT) 132 #define FFR_BOOTCFG_USBSPEED_NMPASEL0 (0x0U) 133 #define FFR_BOOTCFG_USBSPEED_FS (0x1U) 134 #define FFR_BOOTCFG_USBSPEED_HS (0x2U) 135 #define FFR_BOOTCFG_USBSPEED_NMPASEL3 (0x3U) 136 137 #define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) 138 #define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) 139 #define FFR_BOOTCFG_BOOTSPEED_NMPASEL (0x0U) 140 #define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x1U) 141 #define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x2U) 142 143 #define FFR_USBID_VENDORID_MASK (0xFFFFU) 144 #define FFR_USBID_VENDORID_SHIFT (0U) 145 #define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) 146 #define FFR_USBID_PRODUCTID_SHIFT (16U) 147 148 #define FFR_IMAGE0_CMAC_UPDATE_MASK (0x1) 149 #define FFR_IMAGE1_CMAC_UPDATE_MASK (0x2) 150 151 #define FFR_IFR1_PUF_AC_CODE_ADDR (0x01100200UL) 152 #define FFR_IFR1_PUF_AC_CODE_LEN (1024UL) 153 154 #define FFR_IFR1_NXP_CERT_ADDR (0x01100600UL) 155 #define FFR_IFR1_NXP_CERT_LEN (1448UL) 156 157 #define FFR_IFR1_ROM_PATCH_ARRAY0_ADDR (0x01101900UL) 158 #define FFR_IFR1_ROM_PATCH_ARRAY0_LEN (1792UL) 159 160 #define FFR_IFR1_ROM_PATCH_ARRAY1_ADDR (0x01102000UL) 161 #define FFR_IFR1_ROM_PATCH_ARRAY1_LEN (3584UL) 162 163 #define FFR_IFR1_ROM_PATCH_ARRAY2_ADDR (0x01103000UL) 164 #define FFR_IFR1_ROM_PATCH_ARRAY2_LEN (2048UL) 165 166 #define FFR_IFR1_ROM_PATCH_ARRAY3_ADDR (0x01103800UL) 167 #define FFR_IFR1_ROM_PATCH_ARRAY3_LEN (2048UL) 168 169 #define FFR_IFR1_NXP_WRITEABLE_REGION0_START (FFR_IFR1_PUF_AC_CODE_ADDR) 170 #define FFR_IFR1_NXP_WRITEABLE_REGION0_END \ 171 (FFR_IFR1_PUF_AC_CODE_ADDR + FFR_IFR1_PUF_AC_CODE_LEN + FFR_IFR1_NXP_CERT_LEN) 172 #define FFR_IFR1_NXP_WRITEABLE_REGION1_START (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR) 173 #define FFR_IFR1_NXP_WRITEABLE_REGION1_END \ 174 (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR + FFR_IFR1_ROM_PATCH_ARRAY0_LEN + FFR_IFR1_ROM_PATCH_ARRAY1_LEN) 175 #define FFR_IFR1_NXP_WRITEABLE_REGION2_START (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR) 176 #define FFR_IFR1_NXP_WRITEABLE_REGION2_END \ 177 (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR + FFR_IFR1_ROM_PATCH_ARRAY2_LEN + FFR_IFR1_ROM_PATCH_ARRAY3_LEN) 178 179 typedef struct 180 { 181 struct 182 { 183 uint32_t boot_src : 2; 184 uint32_t rsv0 : 2; 185 uint32_t isp_boot_if : 3; 186 uint32_t rsv1 : 1; 187 uint32_t rec_boot_src : 2; 188 uint32_t rsv2 : 2; 189 uint32_t boot_speed : 2; 190 uint32_t rsv3 : 2; 191 uint32_t header_marker : 16; 192 } bootCfg; //!< [0x000-0x003] 193 194 struct 195 { 196 uint32_t flash_remap_size : 5; 197 uint32_t bank1_ifr0_usage : 3; 198 uint32_t reserved : 24; 199 } FlashCfg; //!< [0x004-0x007] 200 201 struct 202 { 203 uint8_t recLed; 204 uint8_t ispLed; 205 uint8_t bootFailLed; 206 uint8_t resv0; 207 } bootLedStatus; //!< [0x008-0x00b] 208 209 struct 210 { 211 uint16_t powerDnTimeout; 212 uint16_t wdogTimeout; 213 } bootTimers; //!< [0x00c-0x00f] 214 215 uint32_t resv2; //!< [0x010-0x013] 216 uint32_t resv3; //!< [0x014-0x017] 217 218 uint32_t recSpiFlashCfg0; //!< [0x018-0x01b] 219 uint32_t recSpiFlashCfg1; //!< [0x01c-0x01f] 220 221 uint32_t isp_uart_cfg; //!< [0x020-0x023] 222 uint32_t isp_i2c_cfg; //!< [0x024-0x027] 223 uint32_t isp_can_cfg; //!< [0x028-0x02b] 224 uint32_t isp_spi_cfg0; //!< [0x02c-0x02f] 225 uint32_t isp_spi_cfg1; //!< [0x030-0x034] 226 227 struct 228 { 229 uint16_t vid; 230 uint16_t pid; 231 } usbId; //!< [0x034-0x037] 232 233 uint32_t isp_usb_cfg; //!< [0x038-0x038] 234 uint32_t isp_misc_cfg; //!< [0x03c-0x03f] 235 uint32_t dcfgPin; //!< [0x040-0x043] 236 uint32_t dcfgDflt; //!< [0x044-0x047] 237 uint32_t dapVendorUsage; //!< [0x048-0x04b] 238 uint32_t resv1; //!< [0x04c-0x04f] 239 uint32_t secureBootCfg; //!< [0x050-0x053] 240 uint32_t rokthUsage; //!< [0x054-0x057] 241 uint32_t resv4; //!< [0x058-0x05b] 242 uint32_t resv5; //!< [0x05c-0x05f] 243 uint32_t rotkh[12]; //!< [0x060-0x08f] 244 245 struct 246 { 247 uint32_t npx_w0; 248 uint32_t npx_w1; 249 } princeSr[4]; //!< [0x090-0x0af] 250 251 struct 252 { 253 uint32_t ipedStartAddr; 254 uint32_t ipedEndAddr; 255 } ipedRegions[8]; //!< [0x0b0-0x11f] 256 257 uint32_t rec_img_exit0; 258 uint32_t rec_img_exit1; 259 260 uint32_t resv6[10]; 261 262 struct 263 { 264 uint32_t set0; 265 uint32_t clr0; 266 } quickSetGpio[6]; //!< [0x120-0x14f] 267 268 uint32_t resv7[4]; //!< [0x150-0x15f] 269 uint32_t cust_key_blob[12]; //!< [0x160-0x18f] 270 271 uint32_t resv8[23]; //!< [0x190-0x1eb] 272 uint32_t cmpaCrc; //!< [0x1ec-0x1ef] 273 uint32_t cmpaCmac[4]; //!< [0x1f0-0x1ff] 274 275 } cmpa_cfg_info_t; 276 277 typedef struct 278 { 279 uint32_t header; 280 uint8_t reserved[4]; 281 } cmpa_key_store_header_t; 282 283 #define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) 284 #define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) 285 #define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) 286 #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) 287 #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) 288 #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) 289 290 #define FFR_USBCFG_USBSPEED_HS (0x0U) 291 #define FFR_USBCFG_USBSPEED_FS (0x1U) 292 #define FFR_USBCFG_USBSPEED_NO (0x2U) 293 294 #define FFR_MCAN_BAUDRATE_MASK (0xF0000U) 295 #define FFR_MCAN_BAUDRATE_SHIFT (16U) 296 297 #define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) 298 #define FFR_PERIPHERALCFG_PERI_SHIFT (0U) 299 #define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) 300 #define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) 301 302 #define FFR_PUF_SRAM_CONFIG_MASK (0x3FFFF07) 303 #define FFR_PUF_SRAM_CONFIG_MASK_SHIFT (0U) 304 #define FFR_PUF_SRAM_VALID_MASK (0x1U) 305 #define FFR_PUF_SRAM_VALID_SHIFT (0U) 306 #define FFR_PUF_SRAM_MODE_MASK (0x2U) 307 #define FFR_PUF_SRAM_MODE_SHIFT (1U) 308 #define FFR_PUF_SRAM_CKGATING_MASK (0x4U) 309 #define FFR_PUF_SRAM_CKGATING_SHIFT (2) 310 #define FFR_PUF_SRAM_SMB_MASK (0x300U) 311 #define FFR_PUF_SRAM_SMB_SHIFT (8U) 312 #define FFR_PUF_SRAM_RM_MASK (0x1C00U) 313 #define FFR_PUF_SRAM_RM_SHIFT (10U) 314 #define FFR_PUF_SRAM_WM_MASK (0xE000U) 315 #define FFR_PUF_SRAM_WM_SHIFT (13U) 316 #define FFR_PUF_SRAM_WRME_MASK (0x10000U) 317 #define FFR_PUF_SRAM_WRME_SHIFT (16U) 318 #define FFR_PUF_SRAM_RAEN_MASK (0x20000U) 319 #define FFR_PUF_SRAM_RAEN_SHIFT (17U) 320 #define FFR_PUF_SRAM_RAM_MASK (0x3C0000U) 321 #define FFR_PUF_SRAM_RAM_SHIFT (18U) 322 #define FFR_PUF_SRAM_WAEN_MASK (0x400000U) 323 #define FFR_PUF_SRAM_WAEN_SHIFT (22U) 324 #define FFR_PUF_SRAM_WAM_MASK (0x1800000U) 325 #define FFR_PUF_SRAM_WAM_SHIFT (23U) 326 #define FFR_PUF_SRAM_STBP_MASK (0x2000000U) 327 #define FFR_PUF_SRAM_STBP_SHIFT (25U) 328 329 typedef struct 330 { 331 uint32_t fro32kCfg; //!< [0x000-0x003] 332 uint32_t puf_cfg; //!< [0x004-0x007] 333 uint32_t bod; //!< [0x008-0x00b] 334 uint32_t trim; //!< [0x00c-0x00f] 335 uint32_t deviceID; //!< [0x010-0x03f] 336 uint32_t peripheralCfg; //!< [0x014-0x017] 337 uint32_t dcdPowerProFileLOW[2]; //!< [0x018-0x01f] 338 uint32_t deviceType; //!< [0x020-0x023] 339 uint32_t ldo_ao; //!< [0x024-0x027] 340 uint32_t gdetDelayCfg; //!< [0x028-0x02b] 341 uint32_t gdetMargin; //!< [0x02c-0x02f] 342 uint32_t gdetTrim1; //!< [0x030-0x033] 343 uint32_t gdetEanble1; //!< [0x034-0x037] 344 uint32_t gdetCtrl1; //!< [0x038-0x03b] 345 uint32_t gdetUpdateTimer; //!< [0x03c-0x03f] 346 uint32_t GpoDataChecksum[4]; //!< [0x040-0x04f] 347 uint32_t finalTestBatchId[4]; //!< [0x050-0x05f] 348 uint32_t ecidBackup[4]; //!< [0x060-0x06f] 349 uint32_t uuid[4]; //!< [0x070-0x07f] 350 uint32_t reserved1[7]; //!< [0x080-0x09b] 351 struct 352 { 353 uint8_t xo32mReadyTimeoutInMs; 354 uint8_t usbSpeed; 355 uint8_t reserved[2]; 356 } usbCfg; //!< [0x09c-0x09f] 357 uint32_t reserved2[80]; //!< [0x0a0-0x1df] 358 uint8_t cmac[16]; //!< [0x1e0-0x1ef] 359 uint32_t pageChecksum[4]; //!< [0x1f0-0x1ff] 360 } nmpa_cfg_info_t; 361 362 typedef struct 363 { 364 uint8_t reserved[1][FLASH_FFR_MAX_PAGE_SIZE]; 365 } ffr_key_store_t; 366 367 typedef enum 368 { 369 kFFR_KeyTypeSbkek = 0x00U, 370 kFFR_KeyTypeUser = 0x01U, 371 kFFR_KeyTypeUds = 0x02U, 372 kFFR_KeyTypePrinceRegion0 = 0x03U, 373 kFFR_KeyTypePrinceRegion1 = 0x04U, 374 kFFR_KeyTypePrinceRegion2 = 0x05U, 375 } ffr_key_type_t; 376 377 typedef enum 378 { 379 kFFR_BankTypeBank0_CFPA0 = 0x00u, 380 kFFR_BankTypeBank0_CFPA1 = 0x01u, 381 kFFR_BankTypeBank0_CMPA = 0x02U, 382 kFFR_BankTypeBank0_NMPA = 0x03U, 383 kFFR_BankTypeBank0_SBL = 0x04U, 384 385 } ffr_bank_type_t; 386 387 /******************************************************************************* 388 * API 389 ******************************************************************************/ 390 391 #if defined(__cplusplus) 392 extern "C" { 393 #endif 394 395 /*! 396 * @name FFR APIs 397 * @{ 398 */ 399 400 /*! 401 * @brief Initializes the global FFR properties structure members. 402 * 403 * @param config A pointer to the storage for the driver runtime state. 404 * 405 * @retval #kStatus_FLASH_Success API was executed successfully. 406 */ 407 status_t FFR_Init(flash_config_t *config); 408 409 /*! 410 * @brief Enable firewall for all flash banks. 411 * 412 * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; 413 * Unless the board is reset again. 414 * 415 * @param config A pointer to the storage for the driver runtime state. 416 * 417 * @retval #kStatus_FLASH_Success An invalid argument is provided. 418 */ 419 status_t FFR_Lock(flash_config_t *config); 420 421 /*! 422 * @brief APIs to access CFPA pages 423 * 424 * This routine will erase CFPA and program the CFPA page with passed data. 425 * 426 * @param config A pointer to the storage for the driver runtime state. 427 * @param page_data A pointer to the source buffer of data that is to be programmed 428 * into the CFPA. 429 * @param valid_len The length, given in bytes, to be programmed. 430 * 431 * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. 432 * @retval #kStatus_FLASH_SizeError Error size 433 * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed 434 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline 435 * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed 436 * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. 437 * @retval #kStatus_FTFx_AddressError Address is out of range. 438 * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. 439 * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. 440 * @retval #kStatus_FLASH_CommandFailure access error. 441 * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported 442 * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. 443 * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. 444 */ 445 status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); 446 447 /*! 448 * @brief APIs to access CFPA pages 449 * 450 * Generic read function, used by customer to read data stored in 'Customer In-field Page'. 451 * 452 * @param config A pointer to the storage for the driver runtime state. 453 * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. 454 * @param offset An offset from the 'Customer In-field Page' start address. 455 * @param len The length, given in bytes, to be read. 456 * 457 * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. 458 * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. 459 * @retval #kStatus_FTFx_AddressError Address is out of range. 460 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. 461 * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed 462 * @retval #kStatus_FLASH_CommandFailure access error. 463 * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported 464 * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. 465 * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. 466 */ 467 status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); 468 469 /*! 470 * @brief APIs to access CMPA pages 471 * 472 * This routine will erase "customer factory page" and program the page with passed data. 473 * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of 474 * the page contents and then programs the pages. 475 * 1.During development customer code uses this API with 'seal_part' set to FALSE. 476 * 2.During manufacturing this parameter should be set to TRUE to seal the part 477 * from further modifications 478 * 3.This routine checks if the page is sealed or not. A page is said to be sealed if 479 * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for 480 * the region if hash is programmed anyways. So, write/erase commands will fail eventually. 481 * 482 * @param config A pointer to the storage for the driver runtime state. 483 * @param page_data A pointer to the source buffer of data that is to be programmed 484 * into the "customer factory page". 485 * @param seal_part Set fasle for During development customer code. 486 * 487 * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. 488 * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. 489 * @retval #kStatus_FTFx_AddressError Address is out of range. 490 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. 491 * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. 492 * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed 493 * @retval #kStatus_Fail Generic status for Fail. 494 * @retval #kStatus_FLASH_CommandFailure access error. 495 * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported 496 * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. 497 * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. 498 */ 499 status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); 500 501 /*! 502 * @brief APIs to access CMPA page 503 * 504 * Read data stored in 'Customer Factory CFG Page'. 505 * 506 * @param config A pointer to the storage for the driver runtime state. 507 * @param pData A pointer to the dest buffer of data that is to be read 508 * from the Customer Factory CFG Page. 509 * @param offset Address offset relative to the CMPA area. 510 * @param len The length, given in bytes to be read. 511 * 512 * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. 513 * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. 514 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. 515 * @retval #kStatus_FTFx_AddressError Address is out of range. 516 * @retval #kStatus_FLASH_CommandFailure access error. 517 * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported 518 * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. 519 * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. 520 * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed 521 */ 522 status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); 523 524 /*! 525 * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C 526 * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. 527 * 528 * @param config A pointer to the storage for the driver runtime state. 529 * @param pData A pointer to the dest buffer of data that is to be read 530 * from the Customer Factory CFG Page. 531 * @param offset Address offset relative to the CMPA area. 532 * @param len The length, given in bytes to be read. 533 * 534 * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. 535 * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. 536 * @retval #kStatus_FTFx_AddressError Address is out of range. 537 * @retval #kStatus_FLASH_AddressError Address is out of range 538 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. 539 * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed 540 * @retval #kStatus_FLASH_CommandFailure access error. 541 * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported 542 * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. 543 * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. 544 */ 545 status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); 546 547 /*! 548 * @brief This routine writes the 3 pages allocated for Key store data. 549 * 550 * @param config A pointer to the storage for the driver runtime state. 551 * @param pKeyStore A pointer to the source buffer of data that is to be programmed 552 * into the "Key store". 553 * 554 * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. 555 * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. 556 * @retval #kStatus_FLASH_CommandFailure access error. 557 * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported 558 * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. 559 * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. 560 * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. 561 * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. 562 * @retval #kStatus_FLASH_AddressError Address is out of range 563 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. 564 * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed 565 */ 566 status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); 567 568 /*! 569 * @brief APIs to access CMPA page 570 * 571 * 1.SW should use this API routine to get the UUID of the chip. 572 * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. 573 * 574 * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. 575 * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. 576 * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed 577 * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. 578 * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported 579 * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. 580 */ 581 status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); 582 583 /*! @} */ 584 585 #ifdef __cplusplus 586 } 587 #endif 588 589 /*! @} */ 590 591 #endif /*! FSL_FLASH_FFR_H_ */ 592
