1 /* Copyright (c) 2021 Intel Corporation
2  * SPDX-License-Identifier: Apache-2.0
3  */
4 #ifndef _ZEPHYR_SOC_INTEL_ADSP_DEBUG_WINDOW
5 #define _ZEPHYR_SOC_INTEL_ADSP_DEBUG_WINDOW
6 
7 #include <mem_window.h>
8 #include <zephyr/debug/sparse.h>
9 #include <zephyr/cache.h>
10 
11 /*
12  * SRAM window for debug info (window 2) is organized in slots,
13  * described in the descriptors available on page 0.
14  *
15  *	------------------------
16  *	| Page0  - descriptors |
17  *	------------------------
18  *	| Page1  - slot0       |
19  *	------------------------
20  *	| Page2  - slot1       |
21  *	------------------------
22  *	|         ...          |
23  *	------------------------
24  *	| Page14  - slot13     |
25  *	------------------------
26  *	| Page15  - slot14     |
27  *	------------------------
28  *
29  * The slot size == page size
30  *
31  * The first page contains descriptors for the remaining slots.
32  * The overall number of slots can vary based on platform.
33  *
34  * The slot descriptor is:
35  * u32 res_id;
36  * u32 type;
37  * u32 vma;
38  */
39 
40 #define ADSP_DW_PAGE_SIZE		0x1000
41 #define ADSP_DW_SLOT_SIZE		ADSP_DW_PAGE_SIZE
42 #define ADSP_DW_SLOT_COUNT		15
43 
44 /* debug window slots usage */
45 #define ADSP_DW_SLOT_NUM_TRACE		1
46 #define ADSP_DW_SLOT_NUM_SHELL		0
47 
48 /* debug log slot types */
49 #define ADSP_DW_SLOT_UNUSED		0x00000000
50 #define ADSP_DW_SLOT_CRITICAL_LOG	0x54524300
51 #define ADSP_DW_SLOT_DEBUG_LOG		0x474f4c00 /* byte 0: core ID */
52 #define ADSP_DW_SLOT_GDB_STUB		0x42444700
53 #define ADSP_DW_SLOT_TELEMETRY		0x4c455400
54 #define ADSP_DW_SLOT_TRACE		0x54524143
55 #define ADSP_DW_SLOT_SHELL		0x73686c6c
56 #define ADSP_DW_SLOT_BROKEN		0x44414544
57 
58  /* for debug and critical types */
59 #define ADSP_DW_SLOT_CORE_MASK		GENMASK(7, 0)
60 #define ADSP_DW_SLOT_TYPE_MASK		GENMASK(31, 8)
61 
62 struct adsp_dw_desc {
63 	uint32_t resource_id;
64 	uint32_t type;
65 	uint32_t vma;
66 } __packed;
67 
68 struct adsp_debug_window {
69 	struct adsp_dw_desc descs[ADSP_DW_SLOT_COUNT];
70 	uint8_t reserved[ADSP_DW_SLOT_SIZE - ADSP_DW_SLOT_COUNT * sizeof(struct adsp_dw_desc)];
71 	uint8_t slots[ADSP_DW_SLOT_COUNT][ADSP_DW_SLOT_SIZE];
72 } __packed;
73 
74 #define WIN2_MBASE DT_REG_ADDR(DT_PHANDLE(DT_NODELABEL(mem_window2), memory))
75 
76 #define ADSP_DW ((volatile struct adsp_debug_window *) \
77 		 (sys_cache_uncached_ptr_get((__sparse_force void __sparse_cache *) \
78 				     (WIN2_MBASE + WIN2_OFFSET))))
79 
80 #endif
81