1 /*
2 * Copyright (c) 2022 Andes Technology Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file I2C driver for AndesTech atciic100 IP
9 */
10
11 #include <string.h>
12 #include <zephyr/drivers/i2c.h>
13 #include <zephyr/irq.h>
14 #include "i2c_andes_atciic100.h"
15
16 #define DT_DRV_COMPAT andestech_atciic100
17
18 typedef void (*atciic100_dt_init_func_t)(void);
19
20 struct i2c_atciic100_config {
21 uint32_t base;
22 uint32_t irq_num;
23 atciic100_dt_init_func_t dt_init_fn;
24 };
25
26 static int i2c_atciic100_controller_send(const struct device *dev,
27 uint16_t addr, const uint8_t *data, uint32_t num, uint8_t flags);
28 static int i2c_atciic100_controller_receive(const struct device *dev,
29 uint16_t addr, uint8_t *data, uint32_t num, uint8_t flags);
30 static void i2c_controller_fifo_write(const struct device *dev,
31 uint8_t is_init);
32 static void i2c_controller_fifo_read(const struct device *dev);
33 static int i2c_atciic100_init(const struct device *dev);
34
35 #if defined(CONFIG_I2C_TARGET)
36 static void i2c_atciic100_target_send(const struct device *dev,
37 const uint8_t *data);
38 static void i2c_atciic100_target_receive(const struct device *dev,
39 uint8_t *data);
40 #endif
41
i2c_atciic100_default_control(const struct device * dev)42 static void i2c_atciic100_default_control(const struct device *dev)
43 {
44 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
45 uint32_t reg = 0;
46
47 k_sem_init(&dev_data->bus_lock, 1, 1);
48 k_sem_init(&dev_data->device_sync_sem, 0, 1);
49
50 /* Reset I2C bus */
51 reg = sys_read32(I2C_CMD(dev));
52 reg &= (~CMD_MSK);
53 reg |= (CMD_RESET_I2C);
54 sys_write32(reg, I2C_CMD(dev));
55
56 /* I2C query FIFO depth */
57 reg = sys_read32(I2C_CFG(dev));
58 switch (reg & 0x3) {
59 case 0x0:
60 dev_data->fifo_depth = 2;
61 break;
62 case 0x1:
63 dev_data->fifo_depth = 4;
64 break;
65 case 0x2:
66 dev_data->fifo_depth = 8;
67 break;
68 case 0x3:
69 dev_data->fifo_depth = 16;
70 break;
71 }
72
73 /*
74 * I2C setting: target mode(default), standard speed
75 * 7-bit, CPU mode
76 */
77 sys_write32(0x0, I2C_SET(dev));
78 reg = sys_read32(I2C_SET(dev));
79 reg |= ((SETUP_T_SUDAT_STD << 24) |
80 (SETUP_T_SP_STD << 21) |
81 (SETUP_T_HDDAT_STD << 16) |
82 (SETUP_T_SCL_RATIO_STD << 13) |
83 (SETUP_T_SCLHI_STD << 4) |
84 SETUP_I2C_EN);
85
86 sys_write32(reg, I2C_SET(dev));
87
88 dev_data->driver_state = I2C_DRV_INIT;
89 dev_data->status.mode = 0;
90 dev_data->status.arbitration_lost = 0;
91 dev_data->status.target_ack = 0;
92 }
93
i2c_atciic100_configure(const struct device * dev,uint32_t dev_config)94 static int i2c_atciic100_configure(const struct device *dev,
95 uint32_t dev_config)
96 {
97 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
98 uint32_t reg = 0;
99 int ret = 0;
100
101 reg = sys_read32(I2C_SET(dev));
102
103 switch (I2C_SPEED_GET(dev_config)) {
104 case I2C_SPEED_STANDARD:
105 reg |= SETUP_SPEED_STD;
106 break;
107
108 case I2C_SPEED_FAST:
109 reg |= SETUP_SPEED_FAST;
110 break;
111
112 case I2C_SPEED_FAST_PLUS:
113 reg |= SETUP_SPEED_FAST_PLUS;
114
115 case I2C_SPEED_HIGH:
116 ret = -EIO;
117 goto unlock;
118 case 0x00:
119 break;
120 default:
121 ret = -EIO;
122 goto unlock;
123 }
124
125 if (dev_config & I2C_MODE_CONTROLLER) {
126 reg |= SETUP_CONTROLLER;
127 dev_data->status.mode = 1;
128 } else {
129 reg &= ~SETUP_CONTROLLER;
130 dev_data->status.mode = 0;
131 }
132
133 if (dev_config & I2C_ADDR_10_BITS) {
134 reg |= SETUP_ADDRESSING;
135 } else {
136 reg &= ~SETUP_ADDRESSING;
137 }
138
139 sys_write32(reg, I2C_SET(dev));
140
141 dev_data->driver_state |= I2C_DRV_CFG_PARAM;
142
143 unlock:
144 k_sem_give(&dev_data->bus_lock);
145
146 return ret;
147 }
148
i2c_atciic100_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)149 static int i2c_atciic100_transfer(const struct device *dev,
150 struct i2c_msg *msgs, uint8_t num_msgs, uint16_t addr)
151 {
152 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
153 int ret = 0;
154 int count = 0;
155 uint8_t burst_write_len = msgs[0].len + msgs[1].len;
156 uint8_t burst_write_buf[I2C_MAX_COUNT + BURST_CMD_COUNT];
157
158 k_sem_take(&dev_data->bus_lock, K_FOREVER);
159
160 if ((msgs[0].flags == I2C_MSG_WRITE)
161 && (msgs[1].flags == (I2C_MSG_WRITE | I2C_MSG_STOP))) {
162
163 burst_write_len = msgs[0].len + msgs[1].len;
164 if (burst_write_len > MAX_XFER_SZ) {
165 return -EIO;
166 }
167 for (count = 0; count < burst_write_len; count++) {
168 if (count < msgs[0].len) {
169 burst_write_buf[count] = msgs[0].buf[count];
170 } else {
171 burst_write_buf[count] =
172 msgs[1].buf[count - msgs[0].len];
173 }
174 }
175 ret = i2c_atciic100_controller_send(dev, addr, burst_write_buf,
176 burst_write_len, true);
177 goto exit;
178 }
179
180 for (uint8_t i = 0; i < num_msgs; i++) {
181 if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
182 ret = i2c_atciic100_controller_send(dev,
183 addr, msgs[i].buf, msgs[i].len, msgs[i].flags);
184 } else {
185 ret = i2c_atciic100_controller_receive(dev,
186 addr, msgs[i].buf, msgs[i].len, msgs[i].flags);
187 }
188
189 if (ret < 0) {
190 goto exit;
191 }
192 }
193
194 exit:
195 /* Wait for transfer complete */
196 k_sem_give(&dev_data->bus_lock);
197 return ret;
198 }
199
200
i2c_atciic100_controller_send(const struct device * dev,uint16_t addr,const uint8_t * data,uint32_t num,uint8_t flags)201 static int i2c_atciic100_controller_send(const struct device *dev,
202 uint16_t addr, const uint8_t *data, uint32_t num, uint8_t flags)
203 {
204 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
205 uint32_t reg = 0;
206
207 /*
208 * Max to 10-bit address.
209 * Parameters data = null or num = 0 means no payload for
210 * acknowledge polling. If no I2C payload, set Phase_data=0x0.
211 */
212 if (addr > 0x3FF) {
213 return -EIO;
214 }
215
216 /* Disable all I2C interrupts */
217 reg = sys_read32(I2C_INTE(dev));
218 reg &= (~IEN_ALL);
219 sys_write32(reg, I2C_INTE(dev));
220
221 dev_data->status.mode = 1;
222 reg = sys_read32(I2C_SET(dev));
223 reg |= SETUP_CONTROLLER;
224 sys_write32(reg, I2C_SET(dev));
225
226 /* Direction => tx:0, rx:1 */
227 dev_data->status.arbitration_lost = 0;
228 dev_data->status.target_ack = 0;
229 dev_data->driver_state = I2C_DRV_CONTROLLER_TX;
230
231 /* Step1, Clear FIFO */
232 reg = sys_read32(I2C_CMD(dev));
233 reg &= (~CMD_MSK);
234 reg |= (CMD_CLEAR_FIFO);
235 sys_write32(reg, I2C_CMD(dev));
236
237 /*
238 * Step2
239 * Enable START, ADDRESS, DATA and STOP phase.
240 * If no payload, clear DATA phase.
241 * STOP condition triggered when transmission finish in controller mode.
242 * The bus is busy until STOP condition triggered.
243 * For 10-bit target address, we must set STOP bit.
244 * I2C direction : controller tx, set xfer DATA count.
245 */
246 reg = sys_read32(I2C_CTRL(dev));
247 reg &= (~(CTRL_PHASE_START | CTRL_PHASE_ADDR | CTRL_PHASE_STOP |
248 CTRL_DIR | CTRL_DATA_COUNT));
249
250 if (flags & I2C_MSG_STOP) {
251 reg |= CTRL_PHASE_STOP;
252 }
253 if ((flags & I2C_MSG_RESTART) == 0) {
254 reg |= (CTRL_PHASE_START | CTRL_PHASE_ADDR);
255 }
256 if (num) {
257 reg |= (CTRL_PHASE_DATA | (num & CTRL_DATA_COUNT));
258 }
259
260 sys_write32(reg, I2C_CTRL(dev));
261
262 /* Step3 init I2C info */
263 dev_data->target_addr = addr;
264 dev_data->xfered_data_wt_ptr = 0;
265 dev_data->xfer_wt_num = num;
266 dev_data->middleware_tx_buf = (uint8_t *)data;
267
268 /* In I2C target address, general call address = 0x0(7-bit or 10-bit) */
269 reg = sys_read32(I2C_ADDR(dev));
270 reg &= (~TARGET_ADDR_MSK);
271 reg |= (dev_data->target_addr & (TARGET_ADDR_MSK));
272 sys_write32(reg, I2C_ADDR(dev));
273
274 /*
275 * Step4 Enable Interrupts: Complete, Arbitration Lose
276 * Enable/Disable the FIFO Empty Interrupt
277 * Fill the FIFO before enabling FIFO Empty Interrupt
278 */
279 reg = sys_read32(I2C_INTE(dev));
280
281 i2c_controller_fifo_write(dev, 1);
282
283 reg |= (IEN_CMPL | IEN_ARB_LOSE | IEN_ADDR_HIT);
284
285 if (num > 0) {
286 reg |= IEN_FIFO_EMPTY;
287 } else {
288 reg &= (~IEN_FIFO_EMPTY);
289 }
290
291 sys_write32(reg, I2C_INTE(dev));
292
293 /*
294 * Step5,
295 * I2C Write 0x1 to the Command register to issue the transaction
296 */
297 reg = sys_read32(I2C_CMD(dev));
298 reg &= (~CMD_MSK);
299 reg |= (CMD_ISSUE_TRANSACTION);
300 sys_write32(reg, I2C_CMD(dev));
301
302 k_sem_take(&dev_data->device_sync_sem, K_FOREVER);
303
304 if (dev_data->status.target_ack != 1) {
305 return -EIO;
306 }
307 dev_data->status.target_ack = 0;
308 return 0;
309 }
310
i2c_atciic100_controller_receive(const struct device * dev,uint16_t addr,uint8_t * data,uint32_t num,uint8_t flags)311 static int i2c_atciic100_controller_receive(const struct device *dev,
312 uint16_t addr, uint8_t *data, uint32_t num, uint8_t flags)
313 {
314 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
315 uint32_t reg = 0;
316
317 /*
318 * Max to 10-bit address.
319 * Parameters data = null or num = 0 means no payload for
320 * acknowledge polling. If no I2C payload, set Phase_data=0x0.
321 */
322 if (addr > 0x3FF) {
323 return -EIO;
324 }
325
326 /* Disable all I2C interrupts */
327 reg = sys_read32(I2C_INTE(dev));
328 reg &= (~IEN_ALL);
329 sys_write32(reg, I2C_INTE(dev));
330
331 dev_data->status.mode = 1;
332 reg = sys_read32(I2C_SET(dev));
333 reg |= SETUP_CONTROLLER;
334 sys_write32(reg, I2C_SET(dev));
335
336 /* Direction => tx:0, rx:1 */
337 dev_data->status.arbitration_lost = 0;
338 dev_data->status.target_ack = 0;
339 dev_data->driver_state = I2C_DRV_CONTROLLER_RX;
340
341 /* Step1, Clear FIFO */
342 reg = sys_read32(I2C_CMD(dev));
343 reg &= (~CMD_MSK);
344 reg |= (CMD_CLEAR_FIFO);
345 sys_write32(reg, I2C_CMD(dev));
346
347 /*
348 * Step2
349 * Enable START, ADDRESS, DATA and STOP phase.
350 * If no payload, clear DATA phase.
351 * STOP condition triggered when transmission finish in Controller mode.
352 * The bus is busy until STOP condition triggered.
353 * For 10-bit target address, we must set STOP bit.
354 * I2C direction : controller rx, set xfer data count.
355 */
356 reg = sys_read32(I2C_CTRL(dev));
357 reg &= (~(CTRL_PHASE_START | CTRL_PHASE_ADDR | CTRL_PHASE_STOP |
358 CTRL_DIR | CTRL_DATA_COUNT));
359 reg |= (CTRL_PHASE_START | CTRL_PHASE_ADDR | CTRL_DIR);
360
361 if (flags & I2C_MSG_STOP) {
362 reg |= CTRL_PHASE_STOP;
363 }
364 if (num) {
365 reg |= (CTRL_PHASE_DATA | (num & CTRL_DATA_COUNT));
366 }
367
368 sys_write32(reg, I2C_CTRL(dev));
369
370 /* Step3 init I2C info */
371 dev_data->target_addr = addr;
372 dev_data->xfered_data_rd_ptr = 0;
373 dev_data->xfer_rd_num = num;
374 dev_data->middleware_rx_buf = (uint8_t *)data;
375
376 /* In I2C target address, general call address = 0x0(7-bit or 10-bit) */
377 reg = sys_read32(I2C_ADDR(dev));
378 reg &= (~TARGET_ADDR_MSK);
379 reg |= (dev_data->target_addr & (TARGET_ADDR_MSK));
380 sys_write32(reg, I2C_ADDR(dev));
381
382 /*
383 * Step4 Enable Interrupts: Complete, Arbitration Lose
384 * Enable/Disable the FIFO Full Interrupt
385 */
386 reg = sys_read32(I2C_INTE(dev));
387 reg |= (IEN_CMPL | IEN_FIFO_FULL | IEN_ARB_LOSE | IEN_ADDR_HIT);
388 sys_write32(reg, I2C_INTE(dev));
389
390 /*
391 * Step5,
392 * I2C write 0x1 to the Command register to issue the transaction
393 */
394 reg = sys_read32(I2C_CMD(dev));
395 reg &= (~CMD_MSK);
396 reg |= (CMD_ISSUE_TRANSACTION);
397 sys_write32(reg, I2C_CMD(dev));
398
399 k_sem_take(&dev_data->device_sync_sem, K_FOREVER);
400 if (dev_data->status.target_ack != 1) {
401 return -EIO;
402 }
403 dev_data->status.target_ack = 0;
404 return 0;
405 }
406
407 #if defined(CONFIG_I2C_TARGET)
i2c_atciic100_target_send(const struct device * dev,const uint8_t * data)408 static void i2c_atciic100_target_send(const struct device *dev,
409 const uint8_t *data)
410 {
411 uint32_t reg = 0;
412
413 /* Clear FIFO */
414 reg = sys_read32(I2C_CMD(dev));
415 reg &= (~CMD_MSK);
416 reg |= (CMD_CLEAR_FIFO);
417 sys_write32(reg, I2C_CMD(dev));
418
419 sys_write32(*data, I2C_DATA(dev));
420 }
421
i2c_atciic100_target_receive(const struct device * dev,uint8_t * data)422 static void i2c_atciic100_target_receive(const struct device *dev,
423 uint8_t *data)
424 {
425 *data = sys_read32(I2C_DATA(dev));
426 }
427 #endif
428
i2c_controller_fifo_write(const struct device * dev,uint8_t is_init)429 static void i2c_controller_fifo_write(const struct device *dev,
430 uint8_t is_init)
431 {
432 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
433 uint32_t i = 0, write_fifo_count = 0, reg = 0;
434 uint8_t write_data;
435
436 write_fifo_count = dev_data->xfer_wt_num - dev_data->xfered_data_wt_ptr;
437
438 if (write_fifo_count >= dev_data->fifo_depth) {
439 write_fifo_count = dev_data->fifo_depth;
440 }
441
442 if (is_init) {
443 write_fifo_count = 2;
444 }
445
446 /* I2C write a patch of data(FIFO_Depth) to FIFO */
447 for (i = 0; i < write_fifo_count; i++) {
448
449 write_data =
450 dev_data->middleware_tx_buf[dev_data->xfered_data_wt_ptr];
451 sys_write32((write_data & DATA_MSK), I2C_DATA(dev));
452 dev_data->xfered_data_wt_ptr++;
453
454 /* Disable the FIFO Empty Interrupt if no more data to send */
455 if (dev_data->xfered_data_wt_ptr == dev_data->xfer_wt_num) {
456 reg = sys_read32(I2C_INTE(dev));
457 reg &= (~IEN_FIFO_EMPTY);
458 sys_write32(reg, I2C_INTE(dev));
459 }
460 }
461 }
462
463 /* Basic fifo read function */
i2c_controller_fifo_read(const struct device * dev)464 static void i2c_controller_fifo_read(const struct device *dev)
465 {
466 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
467 uint32_t i = 0, read_fifo_count = 0, reg = 0;
468 uint8_t read_data;
469
470 read_fifo_count = dev_data->xfer_rd_num - dev_data->xfered_data_rd_ptr;
471
472 if (read_fifo_count >= dev_data->fifo_depth) {
473 read_fifo_count = dev_data->fifo_depth;
474 }
475
476 /* I2C read a patch of data(FIFO_Depth) from FIFO */
477 for (i = 0; i < read_fifo_count; i++) {
478
479 read_data = sys_read32(I2C_DATA(dev)) & DATA_MSK;
480
481 dev_data->middleware_rx_buf[dev_data->xfered_data_rd_ptr] =
482 read_data;
483 dev_data->xfered_data_rd_ptr++;
484
485 /* Disable the FIFO Full Interrupt if no more data to receive */
486 if (dev_data->xfered_data_rd_ptr == dev_data->xfer_rd_num) {
487 reg = sys_read32(I2C_INTE(dev));
488 reg &= (~IEN_FIFO_FULL);
489 sys_write32(reg, I2C_INTE(dev));
490 }
491 }
492 }
493
i2c_fifo_empty_handler(const struct device * dev)494 static void i2c_fifo_empty_handler(const struct device *dev)
495 {
496 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
497
498 if (dev_data->driver_state & I2C_DRV_CONTROLLER_TX) {
499 i2c_controller_fifo_write(dev, 0);
500 }
501 }
502
i2c_fifo_full_handler(const struct device * dev)503 static void i2c_fifo_full_handler(const struct device *dev)
504 {
505 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
506
507 if (dev_data->driver_state & I2C_DRV_CONTROLLER_RX) {
508 i2c_controller_fifo_read(dev);
509 }
510 }
511
i2c_cmpl_handler(const struct device * dev,uint32_t reg_stat)512 static void i2c_cmpl_handler(const struct device *dev, uint32_t reg_stat)
513 {
514 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
515 uint32_t reg_set = 0, reg_ctrl = 0, reg = 0;
516
517 reg_set = sys_read32(I2C_SET(dev));
518
519 /* Controller mode */
520 if (dev_data->status.mode == 1) {
521 /* Disable all I2C interrupts */
522 reg = sys_read32(I2C_INTE(dev));
523 reg &= (~IEN_ALL);
524 sys_write32(reg, I2C_INTE(dev));
525 }
526
527 if (dev_data->driver_state &
528 (I2C_DRV_CONTROLLER_TX | I2C_DRV_CONTROLLER_RX)) {
529
530 /* Get the remain number of data */
531 reg_ctrl = sys_read32(I2C_CTRL(dev)) & CTRL_DATA_COUNT;
532
533 if (dev_data->driver_state & I2C_DRV_CONTROLLER_TX) {
534 /* Clear & set driver state to controller tx complete */
535 dev_data->driver_state = I2C_DRV_CONTROLLER_TX_CMPL;
536 }
537
538 if (dev_data->driver_state & I2C_DRV_CONTROLLER_RX) {
539 i2c_controller_fifo_read(dev);
540 /* Clear & set driver state to controller rx complete */
541 dev_data->driver_state = I2C_DRV_CONTROLLER_RX_CMPL;
542 }
543
544 k_sem_give(&dev_data->device_sync_sem);
545 }
546
547 #if defined(CONFIG_I2C_TARGET)
548 if (dev_data->driver_state & (I2C_DRV_TARGET_TX | I2C_DRV_TARGET_RX)) {
549 reg_set = sys_read32(I2C_SET(dev));
550 reg_ctrl = sys_read32(I2C_CTRL(dev));
551
552 if (dev_data->driver_state & I2C_DRV_TARGET_TX) {
553 dev_data->driver_state = I2C_DRV_TARGET_TX_CMPL;
554 }
555
556 if (dev_data->driver_state & I2C_DRV_TARGET_RX) {
557 dev_data->driver_state = I2C_DRV_TARGET_RX_CMPL;
558 }
559
560 /* If the Completion Interrupt asserts,
561 * clear the FIFO and go next transaction.
562 */
563 uint32_t reg_cmd = 0;
564
565 reg_cmd = sys_read32(I2C_CMD(dev));
566 reg_cmd &= (~CMD_MSK);
567 reg_cmd |= (CMD_CLEAR_FIFO);
568 sys_write32(reg_cmd, I2C_CMD(dev));
569 }
570
571 /* Enable Completion & Address Hit Interrupt */
572 /* Enable Byte Receive & Transfer for default target mode */
573 reg = 0x0;
574 reg |= (IEN_CMPL | IEN_ADDR_HIT | STATUS_BYTE_RECV | STATUS_BYTE_TRANS);
575 sys_write32(reg, I2C_INTE(dev));
576
577 reg = sys_read32(I2C_SET(dev));
578 reg &= ~(SETUP_CONTROLLER);
579 sys_write32(reg, I2C_SET(dev));
580
581 reg &= (~TARGET_ADDR_MSK);
582 reg |= (dev_data->target_config->address & (TARGET_ADDR_MSK));
583 sys_write32(reg, I2C_ADDR(dev));
584
585 dev_data->driver_state = I2C_DRV_INIT;
586 dev_data->status.mode = 0;
587 dev_data->status.arbitration_lost = 0;
588 #endif
589
590 }
591
592 #if defined(CONFIG_I2C_TARGET)
andes_i2c_target_event(const struct device * dev,uint32_t reg_stat,uint32_t reg_ctrl)593 static void andes_i2c_target_event(const struct device *dev,
594 uint32_t reg_stat, uint32_t reg_ctrl)
595 {
596 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
597 uint32_t reg_set = 0;
598 uint8_t val;
599 /*
600 * Here is the entry for target mode driver to detect
601 * target RX/TX action depend on controller TX/RX action.
602 * A new I2C data transaction(START-ADDRESS-DATA-STOP)
603 */
604 if (reg_stat & STATUS_ADDR_HIT) {
605 if (k_sem_take(&dev_data->bus_lock, K_NO_WAIT) != 0) {
606 return;
607 }
608
609 if (((reg_ctrl & CTRL_DIR) >> 8) == I2C_TARGET_TX) {
610 /* Notify middleware to do target rx action */
611 dev_data->driver_state = I2C_DRV_TARGET_TX;
612 dev_data->target_callbacks->read_requested
613 (dev_data->target_config, &val);
614 i2c_atciic100_target_send(dev, &val);
615
616 } else if (((reg_ctrl & CTRL_DIR) >> 8) == I2C_TARGET_RX) {
617 /* Notify middleware to do target tx action */
618 dev_data->driver_state = I2C_DRV_TARGET_RX;
619 dev_data->target_callbacks->write_requested
620 (dev_data->target_config);
621 }
622 reg_set |= (CMD_ACK);
623 sys_write32(reg_set, I2C_CMD(dev));
624 }
625
626 if (reg_stat & STATUS_BYTE_RECV) {
627 i2c_atciic100_target_receive(dev, &val);
628 dev_data->target_callbacks->write_received
629 (dev_data->target_config, val);
630
631 reg_set = 0;
632 if ((reg_stat & STATUS_CMPL) == 0) {
633 reg_set |= (CMD_ACK);
634 sys_write32(reg_set, I2C_CMD(dev));
635 } else {
636 reg_set |= (CMD_NACK);
637 sys_write32(reg_set, I2C_CMD(dev));
638 }
639
640 } else if (reg_stat & STATUS_BYTE_TRANS) {
641 dev_data->target_callbacks->read_processed
642 (dev_data->target_config, &val);
643 i2c_atciic100_target_send(dev, &val);
644 }
645
646 if (reg_stat & STATUS_CMPL) {
647 i2c_cmpl_handler(dev, reg_stat);
648 k_sem_give(&dev_data->bus_lock);
649 }
650 }
651
i2c_atciic100_target_register(const struct device * dev,struct i2c_target_config * cfg)652 static int i2c_atciic100_target_register(const struct device *dev,
653 struct i2c_target_config *cfg)
654 {
655 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
656 uint16_t reg_addr = 0;
657 uint32_t reg;
658
659 reg_addr &= (~TARGET_ADDR_MSK);
660 reg_addr |= (cfg->address & (TARGET_ADDR_MSK));
661
662 sys_write32(reg_addr, I2C_ADDR(dev));
663
664 dev_data->target_callbacks = cfg->callbacks;
665 dev_data->target_config = cfg;
666
667 /* Enable Completion & Address Hit Interrupt */
668 /* Enable Byte Receive & Transfer for default target mode */
669 reg = 0x0;
670 reg |= (IEN_CMPL | IEN_ADDR_HIT | STATUS_BYTE_RECV | STATUS_BYTE_TRANS);
671 sys_write32(reg, I2C_INTE(dev));
672
673 return 0;
674 }
675
i2c_atciic100_target_unregister(const struct device * dev,struct i2c_target_config * cfg)676 static int i2c_atciic100_target_unregister(const struct device *dev,
677 struct i2c_target_config *cfg)
678 {
679 uint32_t reg;
680
681 /* Disable all I2C interrupts */
682 reg = sys_read32(I2C_INTE(dev));
683 reg &= (~IEN_ALL);
684 sys_write32(reg, I2C_INTE(dev));
685
686 sys_write32(0x0, I2C_ADDR(dev));
687
688 return 0;
689 }
690 #endif
691
i2c_atciic100_irq_handler(void * arg)692 static void i2c_atciic100_irq_handler(void *arg)
693 {
694 const struct device *dev = (struct device *)arg;
695 struct i2c_atciic100_dev_data_t *dev_data = dev->data;
696
697 uint32_t reg_set, reg_stat = 0, reg_ctrl = 0;
698
699 reg_stat = sys_read32(I2C_STAT(dev));
700 reg_set = sys_read32(I2C_SET(dev));
701 reg_ctrl = sys_read32(I2C_CTRL(dev));
702
703 /* Clear interrupts status */
704 sys_write32((reg_stat & STATUS_W1C_ALL), I2C_STAT(dev));
705
706 #if defined(CONFIG_I2C_TARGET)
707 if (dev_data->status.mode == 0) {
708 andes_i2c_target_event(dev, reg_stat, reg_ctrl);
709 return;
710 }
711 #endif
712 if (reg_stat & STATUS_ADDR_HIT) {
713 dev_data->status.target_ack = 1;
714 }
715
716 if (reg_stat & STATUS_FIFO_EMPTY) {
717 i2c_fifo_empty_handler(dev);
718 }
719
720 if (reg_stat & STATUS_FIFO_FULL) {
721 /* Store hw receive data count quickly */
722 i2c_fifo_full_handler(dev);
723 }
724
725 if (reg_stat & STATUS_CMPL) {
726 /* Store hw receive data count quickly */
727 i2c_cmpl_handler(dev, reg_stat);
728 }
729
730 if ((reg_stat & STATUS_ARB_LOSE) && (reg_set & SETUP_CONTROLLER)) {
731 dev_data->status.arbitration_lost = 1;
732 }
733 }
734
735 static DEVICE_API(i2c, i2c_atciic100_driver) = {
736 .configure = (i2c_api_configure_t)i2c_atciic100_configure,
737 .transfer = (i2c_api_full_io_t)i2c_atciic100_transfer,
738 #if defined(CONFIG_I2C_TARGET)
739 .target_register = (i2c_api_target_register_t)i2c_atciic100_target_register,
740 .target_unregister = (i2c_api_target_unregister_t)i2c_atciic100_target_unregister,
741 #endif
742 #ifdef CONFIG_I2C_RTIO
743 .iodev_submit = i2c_iodev_submit_fallback,
744 #endif
745 };
746
i2c_atciic100_init(const struct device * dev)747 static int i2c_atciic100_init(const struct device *dev)
748 {
749 const struct i2c_atciic100_config *dev_cfg = dev->config;
750
751 /* Disable all interrupts. */
752 sys_write32(0x00000000, I2C_INTE(dev));
753 /* Clear interrupts status. */
754 sys_write32(0xFFFFFFFF, I2C_STAT(dev));
755
756 dev_cfg->dt_init_fn();
757
758 i2c_atciic100_default_control(dev);
759
760 #if defined(CONFIG_I2C_TARGET)
761 i2c_atciic100_configure(dev, I2C_SPEED_SET(I2C_SPEED_STANDARD));
762 #else
763 i2c_atciic100_configure(dev, I2C_SPEED_SET(I2C_SPEED_STANDARD)
764 | I2C_MODE_CONTROLLER);
765 #endif
766 irq_enable(dev_cfg->irq_num);
767
768 return 0;
769 }
770
771 #define I2C_INIT(n) \
772 static struct i2c_atciic100_dev_data_t \
773 i2c_atciic100_dev_data_##n; \
774 static void i2c_dt_init_##n(void); \
775 static const struct i2c_atciic100_config \
776 i2c_atciic100_config_##n = { \
777 .base = DT_INST_REG_ADDR(n), \
778 .irq_num = DT_INST_IRQN(n), \
779 .dt_init_fn = i2c_dt_init_##n \
780 }; \
781 I2C_DEVICE_DT_INST_DEFINE(n, \
782 i2c_atciic100_init, \
783 NULL, \
784 &i2c_atciic100_dev_data_##n, \
785 &i2c_atciic100_config_##n, \
786 POST_KERNEL, \
787 CONFIG_I2C_INIT_PRIORITY, \
788 &i2c_atciic100_driver); \
789 \
790 static void i2c_dt_init_##n(void) \
791 { \
792 IRQ_CONNECT(DT_INST_IRQN(n), \
793 DT_INST_IRQ(n, priority), \
794 i2c_atciic100_irq_handler, \
795 DEVICE_DT_INST_GET(n), \
796 0); \
797 }
798
799 DT_INST_FOREACH_STATUS_OKAY(I2C_INIT)
800
