1 /*
2 * Copyright 2018, 2020, 2022 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_lpuart.h"
10
11 #include "fsl_adapter_uart.h"
12
13 #if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U))
14 #include "fsl_lpflexcomm.h"
15 #endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */
16
17 /*! @brief MACROs for whether a software idleline detection should be used. */
18 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
19 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
20 #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
21 #define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (1)
22 #else /* HAL_UART_TRANSFER_MODE */
23 #define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (0)
24 #endif /* HAL_UART_TRANSFER_MODE */
25 #else /* UART_ADAPTER_NON_BLOCKING_MODE */
26 #define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (1)
27 #endif /* UART_ADAPTER_NON_BLOCKING_MODE */
28 #endif /* HAL_UART_DMA_ENABLE */
29
30 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
31 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
32 #include "fsl_component_timer_manager.h"
33 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
34 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
35 #include "fsl_lpuart_edma.h"
36 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
37 #include "fsl_lpuart_dma.h"
38 #endif
39 #if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT
40 #include "fsl_dmamux.h"
41 #endif
42 #ifdef DMA_IRQS
43 #define DMA_CHN_IRQS DMA_IRQS
44 #endif
45 #endif /* HAL_UART_DMA_ENABLE */
46
47 /*******************************************************************************
48 * Definitions
49 ******************************************************************************/
50 #ifndef NDEBUG
51 #if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
52 #undef assert
53 #define assert(n)
54 #endif
55 #endif
56
57 #ifndef HAL_UART_ADAPTER_LOWPOWER_RESTORE
58 #define HAL_UART_ADAPTER_LOWPOWER_RESTORE (1)
59 #endif
60
61 #ifndef HAL_UART_DMA_RING_BUFFER_ENABLE
62 #define HAL_UART_DMA_RING_BUFFER_ENABLE (0U)
63 #endif /* HAL_UART_DMA_ENABLE */
64 #ifndef LPUART_RING_BUFFER_SIZE
65 #define LPUART_RING_BUFFER_SIZE (128U)
66 #endif
67
68 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
69 /*! @brief uart RX state structure. */
70 typedef struct _hal_uart_dma_receive_state
71 {
72 uint8_t *volatile buffer;
73 volatile uint32_t bufferLength;
74 volatile uint32_t bufferSofar;
75 volatile uint32_t timeout;
76 volatile bool receiveAll;
77 } hal_uart_dma_receive_state_t;
78
79 /*! @brief uart TX state structure. */
80 typedef struct _hal_uart_dma_send_state
81 {
82 uint8_t *volatile buffer;
83 volatile uint32_t bufferLength;
84 volatile uint32_t bufferSofar;
85 volatile uint32_t timeout;
86 } hal_uart_dma_send_state_t;
87
88 typedef struct _hal_uart_dma_state
89 {
90 struct _hal_uart_dma_state *next;
91 uint8_t instance; /* LPUART instance */
92 hal_uart_dma_transfer_callback_t dma_callback;
93 void *dma_callback_param;
94
95 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
96 lpuart_edma_handle_t edmaHandle;
97 edma_handle_t txEdmaHandle;
98 edma_handle_t rxEdmaHandle;
99 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
100 lpuart_dma_handle_t dmaHandle;
101 dma_handle_t txDmaHandle;
102 dma_handle_t rxDmaHandle;
103 #endif
104 hal_uart_dma_receive_state_t dma_rx;
105 hal_uart_dma_send_state_t dma_tx;
106 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
107 dma_channel_mux_configure_t dma_channel_mux_configure;
108 dma_mux_configure_t dma_mux_configure;
109 hal_uart_dma_config_t hal_uart_dma_config;
110 #endif
111 } hal_uart_dma_state_t;
112
113 typedef struct _lpuart_dma_list
114 {
115 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
116 TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle);
117 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
118 hal_uart_dma_state_t *dma_list;
119 volatile int8_t activeCount;
120 } hal_lpuart_dma_list_t;
121
122 static hal_lpuart_dma_list_t s_dmaHandleList;
123 #endif /* HAL_UART_DMA_ENABLE */
124
125 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
126 /*! @brief uart RX state structure. */
127 typedef struct _hal_uart_receive_state
128 {
129 uint8_t *volatile buffer;
130 volatile uint32_t bufferLength;
131 volatile uint32_t bufferSofar;
132 } hal_uart_receive_state_t;
133
134 /*! @brief uart TX state structure. */
135 typedef struct _hal_uart_send_state
136 {
137 uint8_t *volatile buffer;
138 volatile uint32_t bufferLength;
139 volatile uint32_t bufferSofar;
140 } hal_uart_send_state_t;
141 #endif
142 /*! @brief uart state structure. */
143 typedef struct _hal_uart_state
144 {
145 uint8_t instance;
146 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
147 hal_uart_transfer_callback_t callback;
148 void *callbackParam;
149 #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
150 lpuart_handle_t hardwareHandle;
151 #endif
152 hal_uart_receive_state_t rx;
153 hal_uart_send_state_t tx;
154 #endif
155 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
156 #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U))
157 uint32_t reg_BAUD;
158 uint32_t reg_CTRL;
159 uint32_t reg_WATER;
160 uint32_t reg_MODIR;
161 #else
162 hal_uart_config_t config;
163 #endif
164 #endif
165 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
166 hal_uart_dma_state_t *dmaHandle;
167 #endif /* HAL_UART_DMA_ENABLE */
168 } hal_uart_state_t;
169
170 /*******************************************************************************
171 * Prototypes
172 ******************************************************************************/
173
174 /*******************************************************************************
175 * Variables
176 ******************************************************************************/
177 static LPUART_Type *const s_LpuartAdapterBase[] = LPUART_BASE_PTRS;
178 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
179 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
180 #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U))
181 static const clock_ip_name_t s_LpuartAdapterClock[] = LPUART_CLOCKS;
182 #endif /* HAL_UART_ADAPTER_LOWPOWER_RESTORE */
183 #endif /* HAL_UART_ADAPTER_LOWPOWER */
184 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
185 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
186
187 #if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
188 /* Array of LPUART IRQ number. */
189 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
190 static const IRQn_Type s_LpuartRxIRQ[] = LPUART_RX_IRQS;
191 static const IRQn_Type s_LpuartTxIRQ[] = LPUART_TX_IRQS;
192 #else
193 static const IRQn_Type s_LpuartIRQ[] = LPUART_RX_TX_IRQS;
194 #endif
195 #endif
196
197 #if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
198 static hal_uart_state_t *s_UartState[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)];
199 #endif
200 #endif
201
202 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
203 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
204 #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
205 static hal_uart_dma_state_t *s_UartDmaState[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)] = {0};
206 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
207 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
208 /* allocate ring buffer section. */
209 AT_NONCACHEABLE_SECTION_INIT(
210 static uint8_t s_ringBuffer[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)][LPUART_RING_BUFFER_SIZE]) = {0};
211 /* Allocate TCD memory poll with ring buffer used. */
212 AT_NONCACHEABLE_SECTION_ALIGN(
213 static edma_tcd_t tcdMemoryPoolPtr[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)][1], sizeof(edma_tcd_t));
214
215 static volatile uint32_t ringBufferIndex[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)] = {0U};
216 static void LPUART_StartRingBufferEDMA(hal_uart_handle_t handle);
217 static void LPUART_DMACallbacks(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData);
218 #endif
219 #endif /* HAL_UART_DMA_ENABLE */
220
221 /*******************************************************************************
222 * Code
223 ******************************************************************************/
224
225 #if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \
226 (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)))
HAL_UartGetStatus(status_t status)227 static hal_uart_status_t HAL_UartGetStatus(status_t status)
228 {
229 hal_uart_status_t uartStatus = kStatus_HAL_UartError;
230 switch (status)
231 {
232 case (int32_t)kStatus_Success:
233 uartStatus = kStatus_HAL_UartSuccess;
234 break;
235 case (int32_t)kStatus_LPUART_TxBusy:
236 uartStatus = kStatus_HAL_UartTxBusy;
237 break;
238 case (int32_t)kStatus_LPUART_RxBusy:
239 uartStatus = kStatus_HAL_UartRxBusy;
240 break;
241 case (int32_t)kStatus_LPUART_TxIdle:
242 uartStatus = kStatus_HAL_UartTxIdle;
243 break;
244 case (int32_t)kStatus_LPUART_RxIdle:
245 uartStatus = kStatus_HAL_UartRxIdle;
246 break;
247 case (int32_t)kStatus_LPUART_BaudrateNotSupport:
248 uartStatus = kStatus_HAL_UartBaudrateNotSupport;
249 break;
250 case (int32_t)kStatus_LPUART_NoiseError:
251 case (int32_t)kStatus_LPUART_FramingError:
252 case (int32_t)kStatus_LPUART_ParityError:
253 uartStatus = kStatus_HAL_UartProtocolError;
254 break;
255 default:
256 /*MISRA rule 16.4*/
257 break;
258 }
259 return uartStatus;
260 }
261 #else
HAL_UartGetStatus(status_t status)262 static hal_uart_status_t HAL_UartGetStatus(status_t status)
263 {
264 hal_uart_status_t uartStatus;
265 if ((int32_t)kStatus_Success == status)
266 {
267 uartStatus = kStatus_HAL_UartSuccess; /* Successfully */
268 }
269 else
270 {
271 uartStatus = kStatus_HAL_UartError; /* Error occurs on HAL uart */
272 }
273 return uartStatus;
274 }
275 #endif
276
277 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
278 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
279 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
HAL_UartGetDmaReceivedBytes(uint8_t instance)280 static uint32_t HAL_UartGetDmaReceivedBytes(uint8_t instance)
281 {
282 volatile uint32_t receivedBytes = 0U;
283 uint32_t remainingBytes = 0U;
284 uint32_t newIndex = 0U;
285
286 hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance];
287
288 remainingBytes =
289 EDMA_GetRemainingMajorLoopCount(uartDmaHandle->rxEdmaHandle.base, uartDmaHandle->rxEdmaHandle.channel);
290 if (remainingBytes == LPUART_RING_BUFFER_SIZE)
291 {
292 remainingBytes = 0;
293 }
294 else
295 {
296 newIndex = LPUART_RING_BUFFER_SIZE - remainingBytes;
297 }
298
299 if (newIndex < ringBufferIndex[instance])
300 {
301 newIndex = newIndex + LPUART_RING_BUFFER_SIZE;
302 }
303 receivedBytes = newIndex - ringBufferIndex[instance];
304
305 return receivedBytes;
306 }
307 #endif
308 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
309 #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
HAL_UartDMAIdlelineInterruptHandle(uint8_t instance)310 static void HAL_UartDMAIdlelineInterruptHandle(uint8_t instance)
311 {
312 hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance];
313 hal_dma_callback_msg_t dmaMsg;
314 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
315 uint32_t receiveLength = 0;
316 uint32_t callbackLength = 0;
317 uint32_t remianLength = 0;
318 uint32_t key;
319 #endif /* HAL_UART_DMA_RING_BUFFER_ENABLE */
320 assert(uartDmaHandle);
321 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
322 if ((NULL != uartDmaHandle->dma_callback) && (NULL != uartDmaHandle->dma_rx.buffer))
323 {
324 key = DisableGlobalIRQ();
325 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
326 receiveLength = HAL_UartGetDmaReceivedBytes(instance);
327 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
328
329 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
330 if (uartDmaHandle->dma_rx.receiveAll == true)
331 {
332 if (receiveLength < uartDmaHandle->dma_rx.bufferLength)
333 {
334 LPUART_EnableInterrupts(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_IdleLineInterruptEnable);
335 EnableGlobalIRQ(key);
336 return;
337 }
338 }
339 callbackLength =
340 (receiveLength < uartDmaHandle->dma_rx.bufferLength) ? receiveLength : uartDmaHandle->dma_rx.bufferLength;
341 if (callbackLength != 0U)
342 {
343 dmaMsg.status = kStatus_HAL_UartDmaIdleline;
344 dmaMsg.dataSize = callbackLength;
345
346 if (ringBufferIndex[instance] + callbackLength < LPUART_RING_BUFFER_SIZE)
347 {
348 (void)memcpy(uartDmaHandle->dma_rx.buffer, &s_ringBuffer[instance][ringBufferIndex[instance]],
349 callbackLength);
350 ringBufferIndex[instance] += callbackLength;
351 }
352 else
353 {
354 remianLength = callbackLength + ringBufferIndex[instance] - LPUART_RING_BUFFER_SIZE;
355 (void)memcpy(uartDmaHandle->dma_rx.buffer, &s_ringBuffer[instance][ringBufferIndex[instance]],
356 (callbackLength - remianLength));
357 (void)memcpy(uartDmaHandle->dma_rx.buffer + (callbackLength - remianLength), &s_ringBuffer[instance][0],
358 remianLength);
359 ringBufferIndex[instance] = remianLength;
360 }
361 dmaMsg.data = uartDmaHandle->dma_rx.buffer;
362 uartDmaHandle->dma_rx.buffer = NULL;
363
364 uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param);
365 }
366 EnableGlobalIRQ(key);
367 }
368 #else
369 if ((NULL != uartDmaHandle->dma_callback) && (NULL != uartDmaHandle->dma_rx.buffer))
370 {
371 /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */
372 /* HAL_UartDMAAbortReceive(uartDmaHandle); */
373
374 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
375 (void)LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance],
376 &uartDmaHandle->edmaHandle, &dmaMsg.dataSize);
377 LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle);
378 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
379 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
380 dmaMsg.status = kStatus_HAL_UartDmaIdleline;
381 dmaMsg.data = uartDmaHandle->dma_rx.buffer;
382 uartDmaHandle->dma_rx.buffer = NULL;
383
384 uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param);
385 }
386
387 #endif
388 }
389 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
390 #endif /* HAL_UART_DMA_ENABLE */
391
392 #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
HAL_UartCallback(LPUART_Type * base,lpuart_handle_t * handle,status_t status,void * callbackParam)393 static void HAL_UartCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *callbackParam)
394 {
395 hal_uart_state_t *uartHandle;
396 hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
397 assert(callbackParam);
398
399 uartHandle = (hal_uart_state_t *)callbackParam;
400
401 if (kStatus_HAL_UartProtocolError == uartStatus)
402 {
403 if (0U != uartHandle->hardwareHandle.rxDataSize)
404 {
405 uartStatus = kStatus_HAL_UartError;
406 }
407 }
408
409 if (NULL != uartHandle->callback)
410 {
411 uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
412 }
413 }
414
415 #else /* HAL_UART_TRANSFER_MODE */
416
HAL_UartInterruptHandle(uint8_t instance)417 static void HAL_UartInterruptHandle(uint8_t instance)
418 {
419 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
420 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
421 #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
422 hal_dma_callback_msg_t dmaMsg;
423 hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance];
424 uint32_t sentCount = 0U;
425 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
426 #endif /* HAL_UART_DMA_ENABLE */
427 hal_uart_state_t *uartHandle = s_UartState[instance];
428 uint32_t status;
429 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
430 uint8_t count;
431 #endif
432
433 assert(NULL != uartHandle);
434
435 status = LPUART_GetStatusFlags(s_LpuartAdapterBase[instance]);
436
437 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
438 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
439 #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
440 /* DMA send complete interrupt. */
441 if ((NULL != uartDmaHandle) && (instance == uartDmaHandle->instance))
442 {
443 if (NULL != uartDmaHandle->dma_tx.buffer)
444 {
445 if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) &&
446 (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) &
447 (uint32_t)kLPUART_TransmissionCompleteFlag)))
448
449 {
450 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
451 #elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
452 (void)LPUART_TransferGetSendCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance],
453 &uartDmaHandle->edmaHandle, &sentCount);
454 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
455
456 /* Disable tx complete interrupt */
457 (void)LPUART_DisableInterrupts(s_LpuartAdapterBase[instance],
458 (uint32_t)kLPUART_TransmissionCompleteFlag);
459 uartDmaHandle->edmaHandle.txState = 0;
460 dmaMsg.status = kStatus_HAL_UartDmaTxIdle;
461 dmaMsg.data = uartDmaHandle->dma_tx.buffer;
462 dmaMsg.dataSize = uartDmaHandle->dma_tx.bufferLength;
463 uartDmaHandle->dma_tx.buffer = NULL;
464 uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param);
465 }
466 }
467 /* DMA receive Idleline interrupt. */
468 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
469 if (NULL != uartDmaHandle->dma_rx.buffer)
470 #else
471 if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll))
472 #endif
473 {
474 if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) &&
475 (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) &
476 (uint32_t)kLPUART_IdleLineInterruptEnable)))
477 {
478 HAL_UartDMAIdlelineInterruptHandle(instance);
479 (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_IdleLineFlag);
480 }
481 }
482 }
483
484 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
485 #endif /* HAL_UART_DMA_ENABLE */
486
487 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
488 /* If RX overrun. */
489 if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status))
490 {
491 /* Clear overrun flag, otherwise the RX does not work. */
492 s_LpuartAdapterBase[instance]->STAT =
493 ((s_LpuartAdapterBase[instance]->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
494 }
495 #endif
496 if ((0u != ((uint32_t)kLPUART_NoiseErrorFlag & status)) || (0u != ((uint32_t)kLPUART_FramingErrorFlag & status)) ||
497 (0u != ((uint32_t)kLPUART_ParityErrorFlag & status)))
498 {
499 if (0u != ((uint32_t)kLPUART_NoiseErrorFlag & status))
500 {
501 (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_NoiseErrorFlag);
502 }
503 if (0u != ((uint32_t)kLPUART_FramingErrorFlag & status))
504 {
505 (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_FramingErrorFlag);
506 }
507 if (0u != ((uint32_t)kLPUART_ParityErrorFlag & status))
508 {
509 (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_ParityErrorFlag);
510 }
511
512 /*clean RDRF flag and drop the data with status error*/
513 if (0u != ((uint32_t)(kLPUART_RxDataRegFullFlag)&status))
514 {
515 (void)LPUART_ReadByte(s_LpuartAdapterBase[instance]);
516 }
517 status = LPUART_GetStatusFlags(s_LpuartAdapterBase[instance]);
518 }
519 #if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U))
520 if (((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) &&
521 #else
522 /* Receive data register full */
523 if (((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) &&
524 #endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */
525 (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) &
526 (uint32_t)kLPUART_RxDataRegFullInterruptEnable)))
527 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
528 || ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) &&
529 (0U !=
530 (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable)))
531 #endif
532 )
533 {
534 if (NULL != uartHandle->rx.buffer)
535 {
536 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
537 /* Get the size that can be stored into buffer for this interrupt. */
538 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
539 count = ((uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_RXCOUNT_MASK) >>
540 LPUART_WATER_RXCOUNT_SHIFT));
541 #else
542 if (0U != (status & (uint32_t)kLPUART_RxDataRegFullInterruptEnable))
543 {
544 count = 1U;
545 }
546 else
547 {
548 count = 0U;
549 }
550 #endif
551 while (0u != count)
552 {
553 count--;
554 #endif
555 uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = LPUART_ReadByte(s_LpuartAdapterBase[instance]);
556 if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
557 {
558 LPUART_DisableInterrupts(
559 s_LpuartAdapterBase[instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable |
560 (uint32_t)kLPUART_RxOverrunInterruptEnable
561 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
562 | (uint32_t)kLPUART_IdleLineInterruptEnable
563 #endif
564 );
565 uartHandle->rx.buffer = NULL;
566 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
567 count = 0u;
568 #endif
569 if (NULL != uartHandle->callback)
570 {
571 uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
572 }
573 }
574 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
575 }
576 #endif
577 }
578 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
579 if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) &&
580 (0U !=
581 (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable)))
582 {
583 s_LpuartAdapterBase[instance]->STAT |= ((uint32_t)kLPUART_IdleLineFlag);
584 }
585 #endif
586 }
587
588 /* Send data register empty and the interrupt is enabled. */
589 if ((0U != (LPUART_STAT_TDRE_MASK & status)) && (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) &
590 (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable)))
591 {
592 if (NULL != uartHandle->tx.buffer)
593 {
594 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
595 /* Get the size that transmit buffer for this interrupt. */
596 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
597 count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[instance]) -
598 (uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_TXCOUNT_MASK) >>
599 LPUART_WATER_TXCOUNT_SHIFT);
600 #else
601 count = 1u;
602 #endif
603 while (0u != count)
604 {
605 count--;
606 #endif
607 LPUART_WriteByte(s_LpuartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
608 if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
609 {
610 LPUART_DisableInterrupts(s_LpuartAdapterBase[instance],
611 (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable);
612 uartHandle->tx.buffer = NULL;
613 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
614 count = 0u;
615 #endif
616 if (NULL != uartHandle->callback)
617 {
618 uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
619 }
620 }
621 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
622 }
623 #endif
624 }
625 }
626
627 #if !(defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
628 (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], status);
629 #endif
630 }
631 #endif /* HAL_UART_TRANSFER_MODE */
632 #if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U))
HAL_LpUartInterruptHandle_Wapper(uint32_t instance,void * handle)633 static void HAL_LpUartInterruptHandle_Wapper(uint32_t instance, void *handle)
634 {
635 hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
636 HAL_UartInterruptHandle(uartHandle->instance);
637 }
638 #endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */
639
640 #endif /* UART_ADAPTER_NON_BLOCKING_MODE */
641
HAL_UartInitCommon(hal_uart_handle_t handle,const hal_uart_config_t * uart_config)642 static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *uart_config)
643 {
644 lpuart_config_t lpuartConfig;
645 status_t status;
646 hal_uart_status_t uartStatus = kStatus_HAL_UartSuccess;
647
648 LPUART_GetDefaultConfig(&lpuartConfig);
649 lpuartConfig.baudRate_Bps = uart_config->baudRate_Bps;
650 lpuartConfig.parityMode = (lpuart_parity_mode_t)uart_config->parityMode;
651 lpuartConfig.stopBitCount = (lpuart_stop_bit_count_t)uart_config->stopBitCount;
652 lpuartConfig.enableRx = (bool)uart_config->enableRx;
653 lpuartConfig.enableTx = (bool)uart_config->enableTx;
654 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
655 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
656 if (uart_config->txFifoWatermark > 0U)
657 {
658 lpuartConfig.txFifoWatermark =
659 MIN(uart_config->txFifoWatermark,
660 (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[uart_config->instance])) -
661 1U;
662 }
663 if (uart_config->rxFifoWatermark > 0U)
664 {
665 lpuartConfig.rxFifoWatermark =
666 MIN(uart_config->rxFifoWatermark,
667 (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[uart_config->instance])) -
668 1U;
669 }
670 #endif
671 #endif
672 #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
673 lpuartConfig.enableRxRTS = (bool)uart_config->enableRxRTS;
674 lpuartConfig.enableTxCTS = (bool)uart_config->enableTxCTS;
675 #endif /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */
676
677 /* Idleline config */
678 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
679 #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
680 lpuartConfig.rxIdleType = kLPUART_IdleTypeStopBit;
681 lpuartConfig.rxIdleConfig = kLPUART_IdleCharacter2;
682 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
683
684 status = LPUART_Init(s_LpuartAdapterBase[uart_config->instance], (const lpuart_config_t *)&lpuartConfig, uart_config->srcClock_Hz);
685
686 if ((int32_t)kStatus_Success != status)
687 {
688 uartStatus = HAL_UartGetStatus(status); /*Get current uart status*/
689 }
690
691 return uartStatus;
692 }
693
HAL_UartInit(hal_uart_handle_t handle,const hal_uart_config_t * uart_config)694 hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config)
695 {
696 hal_uart_state_t *uartHandle;
697 hal_uart_status_t uartStatus;
698 assert(NULL != handle);
699 assert(NULL != uart_config);
700 assert(uart_config->instance < (sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)));
701 assert(NULL != s_LpuartAdapterBase[uart_config->instance]);
702 assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t));
703
704 uartStatus = HAL_UartInitCommon(handle, uart_config);
705
706 if (kStatus_HAL_UartSuccess == uartStatus)
707 {
708 uartHandle = (hal_uart_state_t *)handle;
709 uartHandle->instance = uart_config->instance;
710 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
711 uartHandle->dmaHandle = NULL;
712 #endif /* HAL_UART_DMA_ENABLE */
713
714 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
715 #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
716 LPUART_TransferCreateHandle(s_LpuartAdapterBase[uart_config->instance], &uartHandle->hardwareHandle,
717 (lpuart_transfer_callback_t)HAL_UartCallback, handle);
718 #else
719 s_UartState[uartHandle->instance] = uartHandle;
720 #if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U))
721 LP_FLEXCOMM_SetIRQHandler(uart_config->instance, HAL_LpUartInterruptHandle_Wapper, handle,
722 LP_FLEXCOMM_PERIPH_LPUART);
723 #endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */
724
725 /* Enable interrupt in NVIC. */
726 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
727 NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
728 EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
729 NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
730 EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]);
731 #else
732 NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
733 (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]);
734 #endif
735 #endif
736
737 #endif
738 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
739 #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U))
740 uartHandle->reg_BAUD = s_LpuartAdapterBase[uartHandle->instance]->BAUD;
741 uartHandle->reg_CTRL = s_LpuartAdapterBase[uartHandle->instance]->CTRL;
742 uartHandle->reg_WATER = s_LpuartAdapterBase[uartHandle->instance]->WATER;
743 uartHandle->reg_MODIR = s_LpuartAdapterBase[uartHandle->instance]->MODIR;
744 #else
745 (void)memcpy(&uartHandle->config, uart_config, sizeof(hal_uart_config_t));
746 #endif
747 #endif
748 }
749
750 return uartStatus;
751 }
752
HAL_UartDeinit(hal_uart_handle_t handle)753 hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
754 {
755 hal_uart_state_t *uartHandle;
756
757 assert(NULL != handle);
758
759 uartHandle = (hal_uart_state_t *)handle;
760
761 LPUART_Deinit(s_LpuartAdapterBase[uartHandle->instance]); /*LPUART Deinitialization*/
762
763 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
764
765 #if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
766 s_UartState[uartHandle->instance] = NULL;
767 #endif
768
769 #endif
770
771 return kStatus_HAL_UartSuccess;
772 }
773
HAL_UartReceiveBlocking(hal_uart_handle_t handle,uint8_t * data,size_t length)774 hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
775 {
776 hal_uart_state_t *uartHandle;
777 status_t status;
778 assert(NULL != handle);
779 assert(NULL != data);
780 assert(length > 0U);
781
782 uartHandle = (hal_uart_state_t *)handle;
783
784 status = LPUART_ReadBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length);
785
786 return HAL_UartGetStatus(status);
787 }
788
HAL_UartSendBlocking(hal_uart_handle_t handle,const uint8_t * data,size_t length)789 hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
790 {
791 hal_uart_state_t *uartHandle;
792
793 assert(NULL != handle);
794 assert(NULL != data);
795 assert(length > 0U);
796
797 uartHandle = (hal_uart_state_t *)handle;
798
799 (void)LPUART_WriteBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length);
800
801 return kStatus_HAL_UartSuccess;
802 }
803
HAL_UartEnterLowpower(hal_uart_handle_t handle)804 hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
805 {
806 assert(NULL != handle);
807
808 return kStatus_HAL_UartSuccess;
809 }
810
HAL_UartExitLowpower(hal_uart_handle_t handle)811 hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
812 {
813 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
814 hal_uart_state_t *uartHandle;
815 assert(handle);
816
817 uartHandle = (hal_uart_state_t *)handle;
818
819 #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U))
820 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
821 /* Enable lpuart clock */
822 CLOCK_EnableClock(s_LpuartAdapterClock[uartHandle->instance]);
823 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
824 s_LpuartAdapterBase[uartHandle->instance]->BAUD = uartHandle->reg_BAUD;
825 s_LpuartAdapterBase[uartHandle->instance]->WATER = uartHandle->reg_WATER;
826 s_LpuartAdapterBase[uartHandle->instance]->MODIR = uartHandle->reg_MODIR;
827 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
828 /* Enable tx/rx FIFO */
829 s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
830 /* Flush FIFO */
831 s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
832 #endif /* FSL_FEATURE_LPUART_HAS_FIFO */
833 s_LpuartAdapterBase[uartHandle->instance]->CTRL = uartHandle->reg_CTRL;
834 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
835 s_UartState[uartHandle->instance] = handle;
836 /* Enable interrupt in NVIC. */
837 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
838 NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
839 EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
840 NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
841 EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]);
842 #else
843 NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
844 (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]);
845 #endif
846 s_LpuartAdapterBase[uartHandle->instance]->CTRL |= LPUART_CTRL_RIE_MASK;
847 HAL_UartIsrFunction(uartHandle);
848
849 #endif
850 #else
851 (void)HAL_UartInit(handle, &uartHandle->config);
852 #endif
853 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
854 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
855 #else
856 /* Enable RX interrupt for detecting the IDLE line interrupt. */
857 LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], kLPUART_IdleLineInterruptEnable);
858 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
859
860 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
861 HAL_UartDMAInit(uartHandle, uartHandle->dmaHandle, &uartHandle->dmaHandle->hal_uart_dma_config);
862 LPUART_StartRingBufferEDMA(handle);
863 ringBufferIndex[uartHandle->instance] = 0;
864 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
865 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
866 #endif
867 #endif
868 return kStatus_HAL_UartSuccess;
869 }
870
871 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
872
873 #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
874
HAL_UartTransferInstallCallback(hal_uart_handle_t handle,hal_uart_transfer_callback_t callback,void * callbackParam)875 hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
876 hal_uart_transfer_callback_t callback,
877 void *callbackParam)
878 {
879 hal_uart_state_t *uartHandle;
880
881 assert(handle);
882 assert(0U != HAL_UART_TRANSFER_MODE);
883
884 uartHandle = (hal_uart_state_t *)handle;
885
886 uartHandle->callbackParam = callbackParam;
887 uartHandle->callback = callback;
888
889 return kStatus_HAL_UartSuccess;
890 }
891
HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle,hal_uart_transfer_t * transfer)892 hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
893 {
894 hal_uart_state_t *uartHandle;
895 status_t status;
896 assert(handle);
897 assert(transfer);
898 assert(0U != HAL_UART_TRANSFER_MODE);
899
900 uartHandle = (hal_uart_state_t *)handle;
901
902 status = LPUART_TransferReceiveNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
903 (lpuart_transfer_t *)(void *)transfer, NULL);
904
905 return HAL_UartGetStatus(status);
906 }
907
HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle,hal_uart_transfer_t * transfer)908 hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
909 {
910 hal_uart_state_t *uartHandle;
911 status_t status;
912 assert(handle);
913 assert(transfer);
914 assert(0U != HAL_UART_TRANSFER_MODE);
915
916 uartHandle = (hal_uart_state_t *)handle;
917
918 status = LPUART_TransferSendNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
919 (lpuart_transfer_t *)(void *)transfer);
920
921 return HAL_UartGetStatus(status);
922 }
923
HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle,uint32_t * count)924 hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
925 {
926 hal_uart_state_t *uartHandle;
927 status_t status;
928 assert(handle);
929 assert(count);
930 assert(0U != HAL_UART_TRANSFER_MODE);
931
932 uartHandle = (hal_uart_state_t *)handle;
933
934 status =
935 LPUART_TransferGetReceiveCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
936
937 return HAL_UartGetStatus(status);
938 }
939
HAL_UartTransferGetSendCount(hal_uart_handle_t handle,uint32_t * count)940 hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
941 {
942 hal_uart_state_t *uartHandle;
943 status_t status;
944 assert(handle);
945 assert(count);
946 assert(0U != HAL_UART_TRANSFER_MODE);
947
948 uartHandle = (hal_uart_state_t *)handle;
949
950 status = LPUART_TransferGetSendCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
951
952 return HAL_UartGetStatus(status);
953 }
954
HAL_UartTransferAbortReceive(hal_uart_handle_t handle)955 hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
956 {
957 hal_uart_state_t *uartHandle;
958 assert(handle);
959 assert(0U != HAL_UART_TRANSFER_MODE);
960
961 uartHandle = (hal_uart_state_t *)handle;
962
963 LPUART_TransferAbortReceive(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
964
965 return kStatus_HAL_UartSuccess;
966 }
967
HAL_UartTransferAbortSend(hal_uart_handle_t handle)968 hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
969 {
970 hal_uart_state_t *uartHandle;
971 assert(handle);
972 assert(0U != HAL_UART_TRANSFER_MODE);
973
974 uartHandle = (hal_uart_state_t *)handle;
975
976 LPUART_TransferAbortSend(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
977
978 return kStatus_HAL_UartSuccess;
979 }
980
981 #else /* HAL_UART_TRANSFER_MODE */
982
983 /* None transactional API with non-blocking mode. */
HAL_UartInstallCallback(hal_uart_handle_t handle,hal_uart_transfer_callback_t callback,void * callbackParam)984 hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
985 hal_uart_transfer_callback_t callback,
986 void *callbackParam)
987 {
988 hal_uart_state_t *uartHandle;
989
990 assert(NULL != handle);
991 assert(0U == HAL_UART_TRANSFER_MODE);
992
993 uartHandle = (hal_uart_state_t *)handle;
994 uartHandle->callbackParam = callbackParam;
995 uartHandle->callback = callback;
996
997 return kStatus_HAL_UartSuccess;
998 }
999
HAL_UartReceiveNonBlocking(hal_uart_handle_t handle,uint8_t * data,size_t length)1000 hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
1001 {
1002 hal_uart_state_t *uartHandle;
1003 assert(NULL != handle);
1004 assert(NULL != data);
1005 assert(length > 0U);
1006 assert(0U == HAL_UART_TRANSFER_MODE);
1007
1008 uartHandle = (hal_uart_state_t *)handle;
1009 if (NULL != uartHandle->rx.buffer)
1010 {
1011 return kStatus_HAL_UartRxBusy;
1012 }
1013
1014 uartHandle->rx.bufferLength = length;
1015 uartHandle->rx.bufferSofar = 0;
1016 uartHandle->rx.buffer = data;
1017 LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable |
1018 (uint32_t)kLPUART_RxOverrunInterruptEnable
1019 #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
1020 | (uint32_t)kLPUART_IdleLineInterruptEnable
1021 #endif
1022 );
1023 return kStatus_HAL_UartSuccess;
1024 }
1025
HAL_UartSendNonBlocking(hal_uart_handle_t handle,uint8_t * data,size_t length)1026 hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
1027 {
1028 hal_uart_state_t *uartHandle;
1029 assert(NULL != handle);
1030 assert(NULL != data);
1031 assert(length > 0U);
1032 assert(0U == HAL_UART_TRANSFER_MODE);
1033
1034 uartHandle = (hal_uart_state_t *)handle;
1035 if (NULL != uartHandle->tx.buffer)
1036 {
1037 return kStatus_HAL_UartTxBusy;
1038 }
1039 uartHandle->tx.bufferLength = length;
1040 uartHandle->tx.bufferSofar = 0;
1041 uartHandle->tx.buffer = data;
1042 LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable);
1043 return kStatus_HAL_UartSuccess;
1044 }
1045
HAL_UartGetReceiveCount(hal_uart_handle_t handle,uint32_t * reCount)1046 hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
1047 {
1048 hal_uart_state_t *uartHandle;
1049 assert(NULL != handle);
1050 assert(NULL != reCount);
1051 assert(0U == HAL_UART_TRANSFER_MODE);
1052
1053 uartHandle = (hal_uart_state_t *)handle;
1054 if (NULL != uartHandle->rx.buffer)
1055 {
1056 *reCount = uartHandle->rx.bufferSofar;
1057 return kStatus_HAL_UartSuccess;
1058 }
1059 return kStatus_HAL_UartError;
1060 }
1061
HAL_UartGetSendCount(hal_uart_handle_t handle,uint32_t * seCount)1062 hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
1063 {
1064 hal_uart_state_t *uartHandle;
1065 assert(NULL != handle);
1066 assert(NULL != seCount);
1067 assert(0U == HAL_UART_TRANSFER_MODE);
1068
1069 uartHandle = (hal_uart_state_t *)handle;
1070 if (NULL != uartHandle->tx.buffer)
1071 {
1072 *seCount = uartHandle->tx.bufferSofar;
1073 return kStatus_HAL_UartSuccess;
1074 }
1075 return kStatus_HAL_UartError;
1076 }
1077
HAL_UartAbortReceive(hal_uart_handle_t handle)1078 hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
1079 {
1080 hal_uart_state_t *uartHandle;
1081 assert(NULL != handle);
1082 assert(0U == HAL_UART_TRANSFER_MODE);
1083
1084 uartHandle = (hal_uart_state_t *)handle;
1085
1086 if (NULL != uartHandle->rx.buffer)
1087 {
1088 LPUART_DisableInterrupts(
1089 s_LpuartAdapterBase[uartHandle->instance],
1090 (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
1091 uartHandle->rx.buffer = NULL;
1092 }
1093
1094 return kStatus_HAL_UartSuccess;
1095 }
1096
HAL_UartAbortSend(hal_uart_handle_t handle)1097 hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
1098 {
1099 hal_uart_state_t *uartHandle;
1100 assert(NULL != handle);
1101 assert(0U == HAL_UART_TRANSFER_MODE);
1102
1103 uartHandle = (hal_uart_state_t *)handle;
1104
1105 if (NULL != uartHandle->tx.buffer)
1106 {
1107 LPUART_DisableInterrupts(s_LpuartAdapterBase[uartHandle->instance],
1108 (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable);
1109 uartHandle->tx.buffer = NULL;
1110 }
1111
1112 return kStatus_HAL_UartSuccess;
1113 }
1114
1115 #endif /* HAL_UART_TRANSFER_MODE */
1116
1117 #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
1118
HAL_UartIsrFunction(hal_uart_handle_t handle)1119 void HAL_UartIsrFunction(hal_uart_handle_t handle)
1120 {
1121 hal_uart_state_t *uartHandle;
1122 assert(NULL != handle);
1123 assert(0U != HAL_UART_TRANSFER_MODE);
1124
1125 uartHandle = (hal_uart_state_t *)handle;
1126
1127 #if 0
1128 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1129 DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
1130 DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]);
1131 #else
1132 DisableIRQ(s_LpuartIRQ[uartHandle->instance]);
1133 #endif
1134 #endif
1135 LPUART_TransferHandleIRQ(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
1136 #if 0
1137 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1138 NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
1139 EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
1140 NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
1141 EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]);
1142 #else
1143 NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
1144 EnableIRQ(s_LpuartIRQ[uartHandle->instance]);
1145 #endif
1146 #endif
1147 }
1148
1149 #else /* HAL_UART_TRANSFER_MODE */
1150
HAL_UartIsrFunction(hal_uart_handle_t handle)1151 void HAL_UartIsrFunction(hal_uart_handle_t handle)
1152 {
1153 hal_uart_state_t *uartHandle;
1154 assert(NULL != handle);
1155 assert(0U == HAL_UART_TRANSFER_MODE);
1156
1157 uartHandle = (hal_uart_state_t *)handle;
1158 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
1159 hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[uartHandle->instance];
1160 #endif
1161 #if 0
1162 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1163 DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
1164 DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]);
1165 #else
1166 DisableIRQ(s_LpuartIRQ[uartHandle->instance]);
1167 #endif
1168 #endif
1169 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
1170 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
1171 if ((NULL != uartDmaHandle) && (uartDmaHandle->dma_tx.buffer != NULL))
1172 {
1173 EDMA_HandleIRQ(&uartHandle->dmaHandle->txEdmaHandle);
1174 }
1175 #endif
1176 #endif
1177
1178 HAL_UartInterruptHandle(uartHandle->instance);
1179
1180 #if 0
1181 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1182 NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
1183 EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
1184 NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
1185 EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]);
1186 #else
1187 NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
1188 EnableIRQ(s_LpuartIRQ[uartHandle->instance]);
1189 #endif
1190 #endif
1191 }
1192
1193 #if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
1194 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART0_LPUART1_RX_IRQHandler(void)1195 void LPUART0_LPUART1_RX_IRQHandler(void)
1196 {
1197 if ((s_UartState[0]))
1198 {
1199 if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
1200 ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) ||
1201 ((LPUART_STAT_IDLE_MASK & LPUART0->STAT) && (LPUART_STAT_IDLE_MASK & LPUART0->CTRL)))
1202 {
1203 HAL_UartInterruptHandle(0);
1204 }
1205 }
1206 if ((s_UartState[1]))
1207 {
1208 if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
1209 ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) ||
1210 ((LPUART_STAT_IDLE_MASK & LPUART1->STAT) && (LPUART_STAT_IDLE_MASK & LPUART1->CTRL)))
1211 {
1212 HAL_UartInterruptHandle(1);
1213 }
1214 }
1215 SDK_ISR_EXIT_BARRIER;
1216 }
LPUART0_LPUART1_TX_IRQHandler(void)1217 void LPUART0_LPUART1_TX_IRQHandler(void)
1218 {
1219 if ((s_UartState[0]))
1220 {
1221 if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
1222 ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)) ||
1223 ((LPUART_CTRL_TCIE_MASK & LPUART0->STAT) && (LPUART_CTRL_TCIE_MASK & LPUART0->CTRL)))
1224 {
1225 HAL_UartInterruptHandle(0);
1226 }
1227 }
1228 if ((s_UartState[1]))
1229 {
1230 if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
1231 ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)) ||
1232 ((LPUART_CTRL_TCIE_MASK & LPUART1->STAT) && (LPUART_CTRL_TCIE_MASK & LPUART1->CTRL)))
1233 {
1234 HAL_UartInterruptHandle(1);
1235 }
1236 }
1237 SDK_ISR_EXIT_BARRIER;
1238 }
1239 #else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */
1240 void LPUART0_LPUART1_IRQHandler(void);
LPUART0_LPUART1_IRQHandler(void)1241 void LPUART0_LPUART1_IRQHandler(void)
1242 {
1243 uint32_t orMask;
1244 uint32_t rdrfMask;
1245 uint32_t rieMask;
1246 uint32_t tdreMask;
1247 uint32_t tieMask;
1248 uint32_t ilieMask;
1249 uint32_t tcieMask;
1250 if (NULL != (s_UartState[0]))
1251 {
1252 orMask = LPUART_STAT_OR_MASK & LPUART0->STAT;
1253 rdrfMask = LPUART_STAT_RDRF_MASK & LPUART0->STAT;
1254 rieMask = LPUART_CTRL_RIE_MASK & LPUART0->CTRL;
1255 tdreMask = LPUART0->STAT & LPUART_STAT_TDRE_MASK;
1256 tieMask = LPUART0->CTRL & LPUART_CTRL_TIE_MASK;
1257 ilieMask = LPUART0->STAT & LPUART_CTRL_ILIE_MASK;
1258 tcieMask = LPUART0->STAT & LPUART_CTRL_TCIE_MASK;
1259 if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask) || (bool)ilieMask ||
1260 (bool)tcieMask)
1261 {
1262 HAL_UartInterruptHandle(0);
1263 }
1264 }
1265 if (NULL != (s_UartState[1]))
1266 {
1267 orMask = LPUART_STAT_OR_MASK & LPUART1->STAT;
1268 rdrfMask = LPUART_STAT_RDRF_MASK & LPUART1->STAT;
1269 rieMask = LPUART_CTRL_RIE_MASK & LPUART1->CTRL;
1270 tdreMask = LPUART1->STAT & LPUART_STAT_TDRE_MASK;
1271 tieMask = LPUART1->CTRL & LPUART_CTRL_TIE_MASK;
1272 ilieMask = LPUART1->STAT & LPUART_CTRL_ILIE_MASK;
1273 tcieMask = LPUART1->STAT & LPUART_CTRL_TCIE_MASK;
1274 if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask) || (bool)ilieMask ||
1275 (bool)tcieMask)
1276 {
1277 HAL_UartInterruptHandle(1);
1278 }
1279 }
1280 SDK_ISR_EXIT_BARRIER;
1281 }
1282 #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */
1283 #endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */
1284
1285 #if defined(LPUART0)
1286 #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
1287 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART0_TX_IRQHandler(void)1288 void LPUART0_TX_IRQHandler(void)
1289 {
1290 HAL_UartInterruptHandle(0);
1291 SDK_ISR_EXIT_BARRIER;
1292 }
LPUART0_RX_IRQHandler(void)1293 void LPUART0_RX_IRQHandler(void)
1294 {
1295 HAL_UartInterruptHandle(0);
1296 SDK_ISR_EXIT_BARRIER;
1297 }
1298 #else
1299 #if defined(LP_FLEXCOMM0)
1300 void LP_FLEXCOMM0_IRQHandler(void);
LP_FLEXCOMM0_IRQHandler(void)1301 void LP_FLEXCOMM0_IRQHandler(void)
1302 #else /* LP_FLEXCOMM0 */
1303 void LPUART0_IRQHandler(void);
1304 void LPUART0_IRQHandler(void)
1305 #endif /* LP_FLEXCOMM0 */
1306 {
1307 HAL_UartInterruptHandle(0);
1308 SDK_ISR_EXIT_BARRIER;
1309 }
1310 #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */
1311 #endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */
1312 #endif /* LPUART0 */
1313
1314 #if defined(LPUART1)
1315 #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
1316 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART1_TX_IRQHandler(void)1317 void LPUART1_TX_IRQHandler(void)
1318 {
1319 HAL_UartInterruptHandle(1);
1320 SDK_ISR_EXIT_BARRIER;
1321 }
LPUART1_RX_IRQHandler(void)1322 void LPUART1_RX_IRQHandler(void)
1323 {
1324 HAL_UartInterruptHandle(1);
1325 SDK_ISR_EXIT_BARRIER;
1326 }
1327 #else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */
1328 #if defined(LP_FLEXCOMM1)
1329 void LP_FLEXCOMM1_IRQHandler(void);
LP_FLEXCOMM1_IRQHandler(void)1330 void LP_FLEXCOMM1_IRQHandler(void)
1331 #else /* LP_FLEXCOMM1 */
1332 void LPUART1_IRQHandler(void);
1333 void LPUART1_IRQHandler(void)
1334 #endif /* LP_FLEXCOMM1 */
1335 {
1336 HAL_UartInterruptHandle(1);
1337 SDK_ISR_EXIT_BARRIER;
1338 }
1339 #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */
1340 #endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */
1341 #endif /* LPUART1 */
1342
1343 #if defined(LPUART2)
1344 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART2_TX_IRQHandler(void)1345 void LPUART2_TX_IRQHandler(void)
1346 {
1347 HAL_UartInterruptHandle(2);
1348 SDK_ISR_EXIT_BARRIER;
1349 }
LPUART2_RX_IRQHandler(void)1350 void LPUART2_RX_IRQHandler(void)
1351 {
1352 HAL_UartInterruptHandle(2);
1353 SDK_ISR_EXIT_BARRIER;
1354 }
1355 #else
1356 #if defined(LP_FLEXCOMM2)
1357 void LP_FLEXCOMM2_IRQHandler(void);
LP_FLEXCOMM2_IRQHandler(void)1358 void LP_FLEXCOMM2_IRQHandler(void)
1359 #else /* LP_FLEXCOMM2 */
1360 void LPUART2_IRQHandler(void);
1361 void LPUART2_IRQHandler(void)
1362 #endif /* LP_FLEXCOMM2 */
1363 {
1364 HAL_UartInterruptHandle(2);
1365 SDK_ISR_EXIT_BARRIER;
1366 }
1367 #endif
1368 #endif /* LPUART2 */
1369
1370 #if defined(LPUART3)
1371 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART3_TX_IRQHandler(void)1372 void LPUART3_TX_IRQHandler(void)
1373 {
1374 HAL_UartInterruptHandle(3);
1375 SDK_ISR_EXIT_BARRIER;
1376 }
LPUART3_RX_IRQHandler(void)1377 void LPUART3_RX_IRQHandler(void)
1378 {
1379 HAL_UartInterruptHandle(3);
1380 SDK_ISR_EXIT_BARRIER;
1381 }
1382 #else
1383 #if defined(LP_FLEXCOMM3)
1384 void LP_FLEXCOMM3_IRQHandler(void);
LP_FLEXCOMM3_IRQHandler(void)1385 void LP_FLEXCOMM3_IRQHandler(void)
1386 #else /* LP_FLEXCOMM3 */
1387 void LPUART3_IRQHandler(void);
1388 void LPUART3_IRQHandler(void)
1389 #endif /* LP_FLEXCOMM3 */
1390 {
1391 HAL_UartInterruptHandle(3);
1392 SDK_ISR_EXIT_BARRIER;
1393 }
1394 #endif
1395 #endif /* LPUART3 */
1396
1397 #if defined(LPUART4)
1398 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART4_TX_IRQHandler(void)1399 void LPUART4_TX_IRQHandler(void)
1400 {
1401 HAL_UartInterruptHandle(4);
1402 SDK_ISR_EXIT_BARRIER;
1403 }
LPUART4_RX_IRQHandler(void)1404 void LPUART4_RX_IRQHandler(void)
1405 {
1406 HAL_UartInterruptHandle(4);
1407 SDK_ISR_EXIT_BARRIER;
1408 }
1409 #else
1410 #if defined(LP_FLEXCOMM4)
1411 void LP_FLEXCOMM4_IRQHandler(void);
LP_FLEXCOMM4_IRQHandler(void)1412 void LP_FLEXCOMM4_IRQHandler(void)
1413 #else /* LP_FLEXCOMM4 */
1414 void LPUART4_IRQHandler(void);
1415 void LPUART4_IRQHandler(void)
1416 #endif /* LP_FLEXCOMM4 */
1417 {
1418 HAL_UartInterruptHandle(4);
1419 SDK_ISR_EXIT_BARRIER;
1420 }
1421 #endif
1422 #endif /* LPUART4 */
1423
1424 #if defined(LPUART5)
1425 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART5_TX_IRQHandler(void)1426 void LPUART5_TX_IRQHandler(void)
1427 {
1428 HAL_UartInterruptHandle(5);
1429 SDK_ISR_EXIT_BARRIER;
1430 }
LPUART5_RX_IRQHandler(void)1431 void LPUART5_RX_IRQHandler(void)
1432 {
1433 HAL_UartInterruptHandle(5);
1434 SDK_ISR_EXIT_BARRIER;
1435 }
1436 #else
1437 #if defined(LP_FLEXCOMM5)
1438 void LP_FLEXCOMM5_IRQHandler(void);
LP_FLEXCOMM5_IRQHandler(void)1439 void LP_FLEXCOMM5_IRQHandler(void)
1440 #else /* LP_FLEXCOMM5 */
1441 void LPUART5_IRQHandler(void);
1442 void LPUART5_IRQHandler(void)
1443 #endif /* LP_FLEXCOMM5 */
1444 {
1445 HAL_UartInterruptHandle(5);
1446 SDK_ISR_EXIT_BARRIER;
1447 }
1448 #endif
1449 #endif /* LPUART5 */
1450
1451 #if defined(LPUART6)
1452 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART6_TX_IRQHandler(void)1453 void LPUART6_TX_IRQHandler(void)
1454 {
1455 HAL_UartInterruptHandle(6);
1456 SDK_ISR_EXIT_BARRIER;
1457 }
LPUART6_RX_IRQHandler(void)1458 void LPUART6_RX_IRQHandler(void)
1459 {
1460 HAL_UartInterruptHandle(6);
1461 SDK_ISR_EXIT_BARRIER;
1462 }
1463 #else
1464 #if defined(LP_FLEXCOMM6)
1465 void LP_FLEXCOMM6_IRQHandler(void);
LP_FLEXCOMM6_IRQHandler(void)1466 void LP_FLEXCOMM6_IRQHandler(void)
1467 #else /* LP_FLEXCOMM6 */
1468 void LPUART6_IRQHandler(void);
1469 void LPUART6_IRQHandler(void)
1470 #endif /* LP_FLEXCOMM6 */
1471 {
1472 HAL_UartInterruptHandle(6);
1473 SDK_ISR_EXIT_BARRIER;
1474 }
1475 #endif
1476 #endif /* LPUART6 */
1477
1478 #if defined(LPUART7)
1479 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART7_TX_IRQHandler(void)1480 void LPUART7_TX_IRQHandler(void)
1481 {
1482 HAL_UartInterruptHandle(7);
1483 SDK_ISR_EXIT_BARRIER;
1484 }
LPUART7_RX_IRQHandler(void)1485 void LPUART7_RX_IRQHandler(void)
1486 {
1487 HAL_UartInterruptHandle(7);
1488 SDK_ISR_EXIT_BARRIER;
1489 }
1490 #else
1491 #if defined(LP_FLEXCOMM7)
1492 void LP_FLEXCOMM7_IRQHandler(void);
LP_FLEXCOMM7_IRQHandler(void)1493 void LP_FLEXCOMM7_IRQHandler(void)
1494 #else /* LP_FLEXCOMM7 */
1495 void LPUART7_IRQHandler(void);
1496 void LPUART7_IRQHandler(void)
1497 #endif /* LP_FLEXCOMM7 */
1498 {
1499 HAL_UartInterruptHandle(7);
1500 SDK_ISR_EXIT_BARRIER;
1501 }
1502 #endif
1503 #endif /* LPUART7 */
1504
1505 #if defined(LPUART8)
1506 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART8_TX_IRQHandler(void)1507 void LPUART8_TX_IRQHandler(void)
1508 {
1509 HAL_UartInterruptHandle(8);
1510 SDK_ISR_EXIT_BARRIER;
1511 }
LPUART8_RX_IRQHandler(void)1512 void LPUART8_RX_IRQHandler(void)
1513 {
1514 HAL_UartInterruptHandle(8);
1515 SDK_ISR_EXIT_BARRIER;
1516 }
1517 #else
1518 #if defined(LP_FLEXCOMM8)
1519 void LP_FLEXCOMM8_IRQHandler(void);
LP_FLEXCOMM8_IRQHandler(void)1520 void LP_FLEXCOMM8_IRQHandler(void)
1521 #else /* LP_FLEXCOMM8 */
1522 void LPUART8_IRQHandler(void);
1523 void LPUART8_IRQHandler(void)
1524 #endif /* LP_FLEXCOMM8 */
1525 {
1526 HAL_UartInterruptHandle(8);
1527 SDK_ISR_EXIT_BARRIER;
1528 }
1529 #endif
1530 #endif /* LPUART8 */
1531
1532 #if defined(LPUART9)
1533 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART9_TX_IRQHandler(void)1534 void LPUART9_TX_IRQHandler(void)
1535 {
1536 HAL_UartInterruptHandle(9);
1537 SDK_ISR_EXIT_BARRIER;
1538 }
LPUART9_RX_IRQHandler(void)1539 void LPUART9_RX_IRQHandler(void)
1540 {
1541 HAL_UartInterruptHandle(9);
1542 SDK_ISR_EXIT_BARRIER;
1543 }
1544 #else
1545 #if defined(LP_FLEXCOMM9)
1546 void LP_FLEXCOMM9_IRQHandler(void);
LP_FLEXCOMM9_IRQHandler(void)1547 void LP_FLEXCOMM9_IRQHandler(void)
1548 #else /* LP_FLEXCOMM9 */
1549 void LPUART9_IRQHandler(void);
1550 void LPUART9_IRQHandler(void)
1551 #endif /* LP_FLEXCOMM9 */
1552 {
1553 HAL_UartInterruptHandle(9);
1554 SDK_ISR_EXIT_BARRIER;
1555 }
1556 #endif
1557 #endif /* LPUART9 */
1558
1559 #if defined(LPUART10)
1560 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART10_TX_IRQHandler(void)1561 void LPUART10_TX_IRQHandler(void)
1562 {
1563 HAL_UartInterruptHandle(10);
1564 SDK_ISR_EXIT_BARRIER;
1565 }
LPUART10_RX_IRQHandler(void)1566 void LPUART10_RX_IRQHandler(void)
1567 {
1568 HAL_UartInterruptHandle(10);
1569 SDK_ISR_EXIT_BARRIER;
1570 }
1571 #else
1572 #if defined(LP_FLEXCOMM10)
1573 void LP_FLEXCOMM10_IRQHandler(void);
LP_FLEXCOMM10_IRQHandler(void)1574 void LP_FLEXCOMM10_IRQHandler(void)
1575 #else /* LP_FLEXCOMM10 */
1576 void LPUART10_IRQHandler(void);
1577 void LPUART10_IRQHandler(void)
1578 #endif /* LP_FLEXCOMM10 */
1579 {
1580 HAL_UartInterruptHandle(10);
1581 SDK_ISR_EXIT_BARRIER;
1582 }
1583 #endif
1584 #endif /* LPUART10 */
1585
1586 #if defined(LPUART11)
1587 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART11_TX_IRQHandler(void)1588 void LPUART11_TX_IRQHandler(void)
1589 {
1590 HAL_UartInterruptHandle(11);
1591 SDK_ISR_EXIT_BARRIER;
1592 }
LPUART11_RX_IRQHandler(void)1593 void LPUART11_RX_IRQHandler(void)
1594 {
1595 HAL_UartInterruptHandle(11);
1596 SDK_ISR_EXIT_BARRIER;
1597 }
1598 #else
1599 #if defined(LP_FLEXCOMM11)
1600 void LP_FLEXCOMM11_IRQHandler(void);
LP_FLEXCOMM11_IRQHandler(void)1601 void LP_FLEXCOMM11_IRQHandler(void)
1602 #else /* LP_FLEXCOMM11 */
1603 void LPUART11_IRQHandler(void);
1604 void LPUART11_IRQHandler(void)
1605 #endif /* LP_FLEXCOMM11 */
1606 {
1607 HAL_UartInterruptHandle(11);
1608 SDK_ISR_EXIT_BARRIER;
1609 }
1610 #endif
1611 #endif /* LPUART11 */
1612
1613 #if defined(LPUART12)
1614 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART12_TX_IRQHandler(void)1615 void LPUART12_TX_IRQHandler(void)
1616 {
1617 HAL_UartInterruptHandle(12);
1618 SDK_ISR_EXIT_BARRIER;
1619 }
LPUART12_RX_IRQHandler(void)1620 void LPUART12_RX_IRQHandler(void)
1621 {
1622 HAL_UartInterruptHandle(12);
1623 SDK_ISR_EXIT_BARRIER;
1624 }
1625 #else
1626 #if defined(LP_FLEXCOMM12)
1627 void LP_FLEXCOMM12_IRQHandler(void);
LP_FLEXCOMM12_IRQHandler(void)1628 void LP_FLEXCOMM12_IRQHandler(void)
1629 #else /* LP_FLEXCOMM12 */
1630 void LPUART12_IRQHandler(void);
1631 void LPUART12_IRQHandler(void)
1632 #endif /* LP_FLEXCOMM12 */
1633 {
1634 HAL_UartInterruptHandle(12);
1635 SDK_ISR_EXIT_BARRIER;
1636 }
1637 #endif
1638 #endif /* LPUART12 */
1639
1640 #if defined(LPUART13)
1641 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART13_TX_IRQHandler(void)1642 void LPUART13_TX_IRQHandler(void)
1643 {
1644 HAL_UartInterruptHandle(13);
1645 SDK_ISR_EXIT_BARRIER;
1646 }
LPUART13_RX_IRQHandler(void)1647 void LPUART13_RX_IRQHandler(void)
1648 {
1649 HAL_UartInterruptHandle(13);
1650 SDK_ISR_EXIT_BARRIER;
1651 }
1652 #else
1653 #if defined(LP_FLEXCOMM13)
1654 void LP_FLEXCOMM13_IRQHandler(void);
LP_FLEXCOMM13_IRQHandler(void)1655 void LP_FLEXCOMM13_IRQHandler(void)
1656 #else /* LP_FLEXCOMM13 */
1657 void LPUART13_IRQHandler(void);
1658 void LPUART13_IRQHandler(void)
1659 #endif /* LP_FLEXCOMM13 */
1660 {
1661 HAL_UartInterruptHandle(13);
1662 SDK_ISR_EXIT_BARRIER;
1663 }
1664 #endif
1665 #endif /* LPUART13 */
1666
1667 #if defined(LPUART17)
1668 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART17_TX_IRQHandler(void)1669 void LPUART17_TX_IRQHandler(void)
1670 {
1671 HAL_UartInterruptHandle(17);
1672 SDK_ISR_EXIT_BARRIER;
1673 }
LPUART17_RX_IRQHandler(void)1674 void LPUART17_RX_IRQHandler(void)
1675 {
1676 HAL_UartInterruptHandle(17);
1677 SDK_ISR_EXIT_BARRIER;
1678 }
1679 #else
1680 #if defined(LP_FLEXCOMM17)
1681 void LP_FLEXCOMM17_IRQHandler(void);
LP_FLEXCOMM17_IRQHandler(void)1682 void LP_FLEXCOMM17_IRQHandler(void)
1683 #else /* LP_FLEXCOMM17 */
1684 void LPUART17_IRQHandler(void);
1685 void LPUART17_IRQHandler(void)
1686 #endif /* LP_FLEXCOMM17 */
1687 {
1688 HAL_UartInterruptHandle(17);
1689 SDK_ISR_EXIT_BARRIER;
1690 }
1691 #endif
1692 #endif /* LPUART17 */
1693
1694 #if defined(LPUART18)
1695 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART18_TX_IRQHandler(void)1696 void LPUART18_TX_IRQHandler(void)
1697 {
1698 HAL_UartInterruptHandle(18);
1699 SDK_ISR_EXIT_BARRIER;
1700 }
LPUART18_RX_IRQHandler(void)1701 void LPUART18_RX_IRQHandler(void)
1702 {
1703 HAL_UartInterruptHandle(18);
1704 SDK_ISR_EXIT_BARRIER;
1705 }
1706 #else
1707 #if defined(LP_FLEXCOMM18)
1708 void LP_FLEXCOMM18_IRQHandler(void);
LP_FLEXCOMM18_IRQHandler(void)1709 void LP_FLEXCOMM18_IRQHandler(void)
1710 #else /* LP_FLEXCOMM18 */
1711 void LPUART18_IRQHandler(void);
1712 void LPUART18_IRQHandler(void)
1713 #endif /* LP_FLEXCOMM18 */
1714 {
1715 HAL_UartInterruptHandle(18);
1716 SDK_ISR_EXIT_BARRIER;
1717 }
1718 #endif
1719 #endif /* LPUART18 */
1720
1721 #if defined(LPUART19)
1722 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART19_TX_IRQHandler(void)1723 void LPUART19_TX_IRQHandler(void)
1724 {
1725 HAL_UartInterruptHandle(19);
1726 SDK_ISR_EXIT_BARRIER;
1727 }
LPUART19_RX_IRQHandler(void)1728 void LPUART19_RX_IRQHandler(void)
1729 {
1730 HAL_UartInterruptHandle(19);
1731 SDK_ISR_EXIT_BARRIER;
1732 }
1733 #else
1734 #if defined(LP_FLEXCOMM19)
1735 void LP_FLEXCOMM19_IRQHandler(void);
LP_FLEXCOMM19_IRQHandler(void)1736 void LP_FLEXCOMM19_IRQHandler(void)
1737 #else /* LP_FLEXCOMM19 */
1738 void LPUART19_IRQHandler(void);
1739 void LPUART19_IRQHandler(void)
1740 #endif /* LP_FLEXCOMM19 */
1741 {
1742 HAL_UartInterruptHandle(19);
1743 SDK_ISR_EXIT_BARRIER;
1744 }
1745 #endif
1746 #endif /* LPUART19 */
1747
1748 #if defined(LPUART20)
1749 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
LPUART20_TX_IRQHandler(void)1750 void LPUART20_TX_IRQHandler(void)
1751 {
1752 HAL_UartInterruptHandle(20);
1753 SDK_ISR_EXIT_BARRIER;
1754 }
LPUART20_RX_IRQHandler(void)1755 void LPUART20_RX_IRQHandler(void)
1756 {
1757 HAL_UartInterruptHandle(20);
1758 SDK_ISR_EXIT_BARRIER;
1759 }
1760 #else
1761 #if defined(LP_FLEXCOMM20)
1762 void LP_FLEXCOMM20_IRQHandler(void);
LP_FLEXCOMM20_IRQHandler(void)1763 void LP_FLEXCOMM20_IRQHandler(void)
1764 #else /* LP_FLEXCOMM20 */
1765 void LPUART20_IRQHandler(void);
1766 void LPUART20_IRQHandler(void)
1767 #endif /* LP_FLEXCOMM20 */
1768 {
1769 HAL_UartInterruptHandle(20);
1770 SDK_ISR_EXIT_BARRIER;
1771 }
1772 #endif
1773 #endif /* LPUART20 */
1774
1775 #if defined(CM4_0__LPUART)
1776 void M4_0_LPUART_IRQHandler(void);
M4_0_LPUART_IRQHandler(void)1777 void M4_0_LPUART_IRQHandler(void)
1778 {
1779 HAL_UartInterruptHandle(LPUART_GetInstance(CM4_0__LPUART));
1780 SDK_ISR_EXIT_BARRIER;
1781 }
1782 #endif
1783
1784 #if defined(CM4_1__LPUART)
1785 void M4_1_LPUART_IRQHandler(void);
M4_1_LPUART_IRQHandler(void)1786 void M4_1_LPUART_IRQHandler(void)
1787 {
1788 HAL_UartInterruptHandle(LPUART_GetInstance(CM4_1__LPUART));
1789 SDK_ISR_EXIT_BARRIER;
1790 }
1791 #endif
1792
1793 #if defined(CM4__LPUART)
1794 void M4_LPUART_IRQHandler(void);
M4_LPUART_IRQHandler(void)1795 void M4_LPUART_IRQHandler(void)
1796 {
1797 HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(CM4__LPUART));
1798 SDK_ISR_EXIT_BARRIER;
1799 }
1800 #endif
1801
1802 #if defined(DMA__LPUART0)
DMA_UART0_INT_IRQHandler(void)1803 void DMA_UART0_INT_IRQHandler(void)
1804 {
1805 HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART0));
1806 SDK_ISR_EXIT_BARRIER;
1807 }
1808 #endif
1809
1810 #if defined(DMA__LPUART1)
DMA_UART1_INT_IRQHandler(void)1811 void DMA_UART1_INT_IRQHandler(void)
1812 {
1813 HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART1));
1814 SDK_ISR_EXIT_BARRIER;
1815 }
1816 #endif
1817
1818 #if defined(DMA__LPUART2)
DMA_UART2_INT_IRQHandler(void)1819 void DMA_UART2_INT_IRQHandler(void)
1820 {
1821 HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART2));
1822 SDK_ISR_EXIT_BARRIER;
1823 }
1824 #endif
1825
1826 #if defined(DMA__LPUART3)
DMA_UART3_INT_IRQHandler(void)1827 void DMA_UART3_INT_IRQHandler(void)
1828 {
1829 HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART3));
1830 SDK_ISR_EXIT_BARRIER;
1831 }
1832 #endif
1833
1834 #if defined(DMA__LPUART4)
DMA_UART4_INT_IRQHandler(void)1835 void DMA_UART4_INT_IRQHandler(void)
1836 {
1837 HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART4));
1838 SDK_ISR_EXIT_BARRIER;
1839 }
1840 #endif
1841
1842 #if defined(ADMA__LPUART0)
1843 void ADMA_UART0_INT_IRQHandler(void);
ADMA_UART0_INT_IRQHandler(void)1844 void ADMA_UART0_INT_IRQHandler(void)
1845 {
1846 HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART0));
1847 SDK_ISR_EXIT_BARRIER;
1848 }
1849 #endif
1850
1851 #if defined(ADMA__LPUART1)
1852 void ADMA_UART1_INT_IRQHandler(void);
ADMA_UART1_INT_IRQHandler(void)1853 void ADMA_UART1_INT_IRQHandler(void)
1854 {
1855 HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART1));
1856 SDK_ISR_EXIT_BARRIER;
1857 }
1858 #endif
1859
1860 #if defined(ADMA__LPUART2)
1861 void ADMA_UART2_INT_IRQHandler(void);
ADMA_UART2_INT_IRQHandler(void)1862 void ADMA_UART2_INT_IRQHandler(void)
1863 {
1864 HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART2));
1865 SDK_ISR_EXIT_BARRIER;
1866 }
1867 #endif
1868
1869 #if defined(ADMA__LPUART3)
1870 void ADMA_UART3_INT_IRQHandler(void);
ADMA_UART3_INT_IRQHandler(void)1871 void ADMA_UART3_INT_IRQHandler(void)
1872 {
1873 HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART3));
1874 SDK_ISR_EXIT_BARRIER;
1875 }
1876 #endif
1877
1878 #endif /* HAL_UART_TRANSFER_MODE */
1879
1880 #endif /* UART_ADAPTER_NON_BLOCKING_MODE */
1881
1882 #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
1883 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
1884 static volatile uint32_t ringBufferFlag = 0U;
1885 /* LPUART RX EDMA call back. */
LPUART_RxEDMACallback(edma_handle_t * handle,void * param,bool transferDone,uint32_t tcds)1886 static void LPUART_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
1887 {
1888 if (true == transferDone)
1889 {
1890 ringBufferFlag++;
1891 }
1892 }
1893
1894 /* Start ring buffer. */
LPUART_StartRingBufferEDMA(hal_uart_handle_t handle)1895 static void LPUART_StartRingBufferEDMA(hal_uart_handle_t handle)
1896 {
1897 hal_uart_state_t *uartHandle;
1898 hal_uart_dma_state_t *uartDmaHandle;
1899
1900 assert(handle);
1901
1902 uartHandle = (hal_uart_state_t *)handle;
1903 uartDmaHandle = uartHandle->dmaHandle;
1904
1905 edma_transfer_config_t xferConfig;
1906
1907 /* Install TCD memory for using only one TCD queue. */
1908 EDMA_InstallTCDMemory(&uartDmaHandle->rxEdmaHandle, (edma_tcd_t *)&tcdMemoryPoolPtr[uartHandle->instance], 1U);
1909
1910 /* Prepare transfer to receive data to ring buffer. */
1911 EDMA_PrepareTransfer(&xferConfig,
1912 (void *)(uint32_t *)LPUART_GetDataRegisterAddress(s_LpuartAdapterBase[uartHandle->instance]),
1913 sizeof(uint8_t), &s_ringBuffer[uartHandle->instance], sizeof(uint8_t), sizeof(uint8_t),
1914 LPUART_RING_BUFFER_SIZE, kEDMA_PeripheralToMemory);
1915
1916 /* Submit transfer. */
1917 uartDmaHandle->rxEdmaHandle.tcdUsed = 1U;
1918 uartDmaHandle->rxEdmaHandle.tail = 0U;
1919 EDMA_TcdReset(&uartDmaHandle->rxEdmaHandle.tcdPool[0U]);
1920 EDMA_TcdSetTransferConfig(&uartDmaHandle->rxEdmaHandle.tcdPool[0U], &xferConfig,
1921 tcdMemoryPoolPtr[uartHandle->instance]);
1922
1923 /* Enable major interrupt for counting received bytes. */
1924 uartDmaHandle->rxEdmaHandle.tcdPool[0U].CSR |= 0x2U;
1925
1926 /* There is no live chain, TCD block need to be installed in TCD registers. */
1927 EDMA_InstallTCD(uartDmaHandle->rxEdmaHandle.base, uartDmaHandle->rxEdmaHandle.channel,
1928 &uartDmaHandle->rxEdmaHandle.tcdPool[0U]);
1929
1930 /* Setup call back function. */
1931 EDMA_SetCallback(&uartDmaHandle->rxEdmaHandle, LPUART_RxEDMACallback, NULL);
1932
1933 /* Start EDMA transfer. */
1934 EDMA_StartTransfer(&uartDmaHandle->rxEdmaHandle);
1935
1936 /* Enable LPUART RX EDMA. */
1937 LPUART_EnableRxDMA(s_LpuartAdapterBase[uartHandle->instance], true);
1938
1939 /* Enable RX interrupt for detecting the IDLE line interrupt. */
1940 LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable);
1941 // EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
1942 }
1943 #endif
1944 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
LPUART_DMACallbacks(LPUART_Type * base,lpuart_edma_handle_t * handle,status_t status,void * userData)1945 static void LPUART_DMACallbacks(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)
1946 {
1947 hal_uart_dma_state_t *uartDmaHandle;
1948 hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
1949 hal_dma_callback_msg_t dmaMsg;
1950 assert(handle);
1951
1952 uartDmaHandle = (hal_uart_dma_state_t *)userData;
1953
1954 if (NULL != uartDmaHandle->dma_callback)
1955 {
1956 if (kStatus_HAL_UartTxIdle == uartStatus)
1957 {
1958 dmaMsg.status = kStatus_HAL_UartDmaTxIdle;
1959 dmaMsg.data = uartDmaHandle->dma_tx.buffer;
1960 dmaMsg.dataSize = uartDmaHandle->dma_tx.bufferLength;
1961 uartDmaHandle->dma_tx.buffer = NULL;
1962 }
1963 else if (kStatus_HAL_UartRxIdle == uartStatus)
1964 {
1965 dmaMsg.status = kStatus_HAL_UartDmaRxIdle;
1966 dmaMsg.data = uartDmaHandle->dma_rx.buffer;
1967 dmaMsg.dataSize = uartDmaHandle->dma_rx.bufferLength;
1968 uartDmaHandle->dma_rx.buffer = NULL;
1969 }
1970 else
1971 {
1972 /* MISRA */
1973 }
1974
1975 uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param);
1976 }
1977 }
1978 #endif
1979 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
TimeoutTimer_Callbcak(void * param)1980 static void TimeoutTimer_Callbcak(void *param)
1981 {
1982 hal_lpuart_dma_list_t *uartDmaHandleList;
1983 hal_uart_dma_state_t *uartDmaHandle;
1984 hal_dma_callback_msg_t dmaMsg;
1985 uint32_t newReceived = 0U;
1986
1987 uartDmaHandleList = (hal_lpuart_dma_list_t *)param;
1988 uartDmaHandle = uartDmaHandleList->dma_list;
1989
1990 while (NULL != uartDmaHandle)
1991 {
1992 if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll))
1993 {
1994 /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */
1995 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
1996
1997 #elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
1998 LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle,
1999 &dmaMsg.dataSize);
2000 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2001 newReceived = dmaMsg.dataSize - uartDmaHandle->dma_rx.bufferSofar;
2002 uartDmaHandle->dma_rx.bufferSofar = dmaMsg.dataSize;
2003
2004 /* 1, If it is in idle state. */
2005 if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
2006 {
2007 uartDmaHandle->dma_rx.timeout++;
2008 if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT)
2009 {
2010 /* HAL_UartDMAAbortReceive(uartDmaHandle); */
2011 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2012
2013 #elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2014 LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance],
2015 &uartDmaHandle->edmaHandle);
2016 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2017 dmaMsg.data = uartDmaHandle->dma_rx.buffer;
2018 dmaMsg.status = kStatus_HAL_UartDmaIdleline;
2019 uartDmaHandle->dma_rx.buffer = NULL;
2020 uartDmaHandle->dma_callback(uartDmaHandle, &dmaMsg, uartDmaHandle->dma_callback_param);
2021 }
2022 }
2023 /* 2, If got new data again. */
2024 if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
2025 {
2026 uartDmaHandle->dma_rx.timeout = 0U;
2027 }
2028 }
2029
2030 uartDmaHandle = uartDmaHandle->next;
2031 }
2032 }
2033 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2034
HAL_UartDMAInit(hal_uart_handle_t handle,hal_uart_dma_handle_t dmaHandle,hal_uart_dma_config_t * dmaConfig)2035 hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
2036 hal_uart_dma_handle_t dmaHandle,
2037 hal_uart_dma_config_t *dmaConfig)
2038 {
2039 hal_uart_state_t *uartHandle;
2040 hal_uart_dma_state_t *uartDmaHandle;
2041 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2042 #if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U))
2043 edma_config_t config;
2044 #endif /* HAL_UART_DMA_INIT_ENABLE > 0 */
2045 #endif
2046 assert(handle);
2047
2048 uartHandle = (hal_uart_state_t *)handle;
2049 uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle;
2050 uartHandle->dmaHandle = uartDmaHandle;
2051
2052 /* DMA init process. */
2053 uartDmaHandle->instance = dmaConfig->uart_instance;
2054
2055 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2056 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U))
2057 dma_mux_configure_t *dmaMux = dmaConfig->dma_mux_configure;
2058 /* Set channel for LPUART */
2059 DMAMUX_Type *dmaMuxBases[] = DMAMUX_BASE_PTRS;
2060 DMAMUX_Init(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance]);
2061 DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel,
2062 (int32_t)dmaMux->dma_dmamux_configure.tx_request);
2063 DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel,
2064 (int32_t)dmaMux->dma_dmamux_configure.rx_request);
2065 DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel);
2066 DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel);
2067 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
2068 (void)memcpy(&uartDmaHandle->dma_mux_configure, dmaConfig->dma_mux_configure, sizeof(dma_mux_configure_t));
2069 #endif /* HAL_UART_ADAPTER_LOWPOWER */
2070 #endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */
2071 /* Init the EDMA module */
2072 #if defined(EDMA_BASE_PTRS)
2073 EDMA_Type *dmaBases[] = EDMA_BASE_PTRS;
2074 IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS;
2075 #elif (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U))
2076 DMA_Type *dmaBases[] = DMA_BASE_PTRS;
2077 IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
2078 #else
2079 DMA_Type *dmaBases[] = DMA_BASE_PTRS;
2080 IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
2081 #endif
2082
2083 #if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U))
2084 EDMA_GetDefaultConfig(&config);
2085 #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG
2086 edma_channel_config_t channelConfig = {
2087 .enableMasterIDReplication = true,
2088 #if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC)
2089 .securityLevel = kEDMA_ChannelSecurityLevelSecure,
2090 #endif
2091 .protectionLevel = kEDMA_ChannelProtectionLevelPrivileged,
2092 };
2093
2094 config.enableMasterIdReplication = true;
2095 config.channelConfig[dmaConfig->tx_channel] = &channelConfig;
2096 config.channelConfig[dmaConfig->rx_channel] = &channelConfig;
2097 #endif
2098 EDMA_Init(dmaBases[dmaConfig->dma_instance], &config);
2099 #endif /* HAL_UART_DMA_INIT_ENABLE > 0 */
2100 EDMA_CreateHandle(&uartDmaHandle->txEdmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel);
2101 EDMA_CreateHandle(&uartDmaHandle->rxEdmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel);
2102 #if (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U))
2103 #if (defined(FSL_EDMA_SOC_IP_DMA4) && (FSL_EDMA_SOC_IP_DMA4 > 0) && \
2104 defined(FSL_EDMA_SOC_IP_DMA3) && (FSL_EDMA_SOC_IP_DMA3 > 0))
2105 if(dmaBases[dmaConfig->dma_instance] == (EDMA_Type *)DMA4)
2106 {
2107 dma_channel_mux_configure_t *dmaChannelMux = dmaConfig->dma_channel_mux_configure;
2108 EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel,
2109 (dma4_request_source_t)dmaChannelMux->dma_dmamux_configure.dma_tx_channel_mux);
2110 EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel,
2111 (dma4_request_source_t)dmaChannelMux->dma_dmamux_configure.dma_rx_channel_mux);
2112 }
2113 else
2114 {
2115 dma_channel_mux_configure_t *dmaChannelMux = dmaConfig->dma_channel_mux_configure;
2116 EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel,
2117 (dma3_request_source_t)dmaChannelMux->dma_dmamux_configure.dma_tx_channel_mux);
2118 EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel,
2119 (dma3_request_source_t)dmaChannelMux->dma_dmamux_configure.dma_rx_channel_mux);
2120 }
2121 #else
2122 dma_channel_mux_configure_t *dmaChannelMux = dmaConfig->dma_channel_mux_configure;
2123 EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel,
2124 (int32_t)dmaChannelMux->dma_dmamux_configure.dma_tx_channel_mux);
2125 EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel,
2126 (int32_t)dmaChannelMux->dma_dmamux_configure.dma_rx_channel_mux);
2127 #endif
2128 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
2129 (void)memcpy(&uartDmaHandle->dma_channel_mux_configure, dmaConfig->dma_channel_mux_configure,
2130 sizeof(dma_channel_mux_configure_t));
2131 #endif /* HAL_UART_ADAPTER_LOWPOWER */
2132 #endif /* FSL_FEATURE_EDMA_HAS_CHANNEL_MUX */
2133 #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U))
2134 (void)memcpy(&uartDmaHandle->hal_uart_dma_config, dmaConfig, sizeof(hal_uart_dma_config_t));
2135 uartDmaHandle->hal_uart_dma_config.dma_mux_configure = &uartDmaHandle->dma_mux_configure;
2136 uartDmaHandle->hal_uart_dma_config.dma_channel_mux_configure = &uartDmaHandle->dma_channel_mux_configure;
2137 #endif /* HAL_UART_ADAPTER_LOWPOWER */
2138 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2139 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2140 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2141 NVIC_SetPriority(s_edmaIRQNumbers[dmaConfig->dma_instance][dmaConfig->tx_channel], HAL_UART_ISR_PRIORITY);
2142 NVIC_SetPriority(s_edmaIRQNumbers[dmaConfig->dma_instance][dmaConfig->rx_channel], HAL_UART_ISR_PRIORITY);
2143 #endif
2144 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
2145 #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2146 s_UartDmaState[uartDmaHandle->instance] = uartDmaHandle;
2147
2148 /* Enable RX interrupt for detecting the IDLE line interrupt. */
2149 LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable);
2150 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2151 (void)EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]);
2152 #else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */
2153 (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]);
2154 #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */
2155 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2156
2157 if (0 == s_dmaHandleList.activeCount)
2158 {
2159 s_dmaHandleList.dma_list = uartDmaHandle;
2160 uartDmaHandle->next = NULL;
2161 s_dmaHandleList.activeCount++;
2162
2163 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
2164 timer_status_t timerStatus;
2165 timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle);
2166 assert(kStatus_TimerSuccess == timerStatus);
2167
2168 timerStatus = TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak,
2169 &s_dmaHandleList);
2170 assert(kStatus_TimerSuccess == timerStatus);
2171
2172 (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1);
2173
2174 (void)timerStatus;
2175 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2176 }
2177 else
2178 {
2179 uartDmaHandle->next = s_dmaHandleList.dma_list;
2180 s_dmaHandleList.dma_list = uartDmaHandle;
2181 }
2182
2183 return kStatus_HAL_UartDmaSuccess;
2184 }
2185
HAL_UartDMADeinit(hal_uart_handle_t handle)2186 hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle)
2187 {
2188 hal_uart_state_t *uartHandle;
2189 hal_uart_dma_state_t *uartDmaHandle;
2190 hal_uart_dma_state_t *prev;
2191 hal_uart_dma_state_t *curr;
2192
2193 assert(handle);
2194
2195 uartHandle = (hal_uart_state_t *)handle;
2196 uartDmaHandle = uartHandle->dmaHandle;
2197
2198 uartHandle->dmaHandle = NULL;
2199
2200 assert(uartDmaHandle);
2201
2202 /* Abort rx/tx */
2203
2204 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2205 /* Here we should not abort before create transfer handle. */
2206 if (NULL != uartDmaHandle->edmaHandle.rxEdmaHandle)
2207 {
2208 LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle);
2209 }
2210 if (NULL != uartDmaHandle->edmaHandle.txEdmaHandle)
2211 {
2212 LPUART_TransferAbortSendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle);
2213 }
2214 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2215
2216 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2217
2218 /* Disable rx/tx channels */
2219
2220 /* Remove handle from list */
2221 prev = NULL;
2222 curr = s_dmaHandleList.dma_list;
2223 while (curr != NULL)
2224 {
2225 if (curr == uartDmaHandle)
2226 {
2227 /* 1, if it is the first one */
2228 if (prev == NULL)
2229 {
2230 s_dmaHandleList.dma_list = curr->next;
2231 }
2232 /* 2, if it is the last one */
2233 else if (curr->next == NULL)
2234 {
2235 prev->next = NULL;
2236 }
2237 /* 3, if it is in the middle */
2238 else
2239 {
2240 prev->next = curr->next;
2241 }
2242 break;
2243 }
2244
2245 prev = curr;
2246 curr = curr->next;
2247 }
2248
2249 /* Reset all handle data. */
2250 (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t));
2251
2252 s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0;
2253 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
2254 if (0 == s_dmaHandleList.activeCount)
2255 {
2256 (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle);
2257 }
2258 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2259
2260 return kStatus_HAL_UartDmaSuccess;
2261 }
2262
HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,hal_uart_dma_transfer_callback_t callback,void * callbackParam)2263 hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
2264 hal_uart_dma_transfer_callback_t callback,
2265 void *callbackParam)
2266 {
2267 hal_uart_state_t *uartHandle;
2268 hal_uart_dma_state_t *uartDmaHandle;
2269
2270 assert(handle);
2271
2272 uartHandle = (hal_uart_state_t *)handle;
2273 uartDmaHandle = uartHandle->dmaHandle;
2274
2275 assert(uartDmaHandle);
2276
2277 uartDmaHandle->dma_callback = callback;
2278 uartDmaHandle->dma_callback_param = callbackParam;
2279
2280 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2281 LPUART_TransferCreateHandleEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle,
2282 LPUART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txEdmaHandle,
2283 &uartDmaHandle->rxEdmaHandle);
2284
2285 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
2286 #if (defined(FSL_FEATURE_LPUART_IS_LPFLEXCOMM) && (FSL_FEATURE_LPUART_IS_LPFLEXCOMM > 0U))
2287 LP_FLEXCOMM_SetIRQHandler(uartHandle->instance, HAL_LpUartInterruptHandle_Wapper, handle,
2288 LP_FLEXCOMM_PERIPH_LPUART);
2289 #endif /* FSL_FEATURE_LPUART_IS_LPFLEXCOMM */
2290 #endif /* UART_ADAPTER_NON_BLOCKING_MODE */
2291
2292 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
2293 LPUART_StartRingBufferEDMA(handle);
2294 #endif /* HAL_UART_DMA_RING_BUFFER_ENABLE */
2295 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2296 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2297
2298 return kStatus_HAL_UartDmaSuccess;
2299 }
2300
HAL_UartDMATransferReceive(hal_uart_handle_t handle,uint8_t * data,size_t length,bool receiveAll)2301 hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
2302 uint8_t *data,
2303 size_t length,
2304 bool receiveAll)
2305 {
2306 hal_uart_state_t *uartHandle;
2307 hal_uart_dma_state_t *uartDmaHandle;
2308
2309 assert(handle);
2310 assert(data);
2311
2312 uartHandle = (hal_uart_state_t *)handle;
2313 uartDmaHandle = uartHandle->dmaHandle;
2314
2315 assert(uartDmaHandle);
2316
2317 if (NULL == uartDmaHandle->dma_rx.buffer)
2318 {
2319 uartDmaHandle->dma_rx.buffer = data;
2320 uartDmaHandle->dma_rx.bufferLength = length;
2321 uartDmaHandle->dma_rx.bufferSofar = 0U;
2322 uartDmaHandle->dma_rx.timeout = 0U;
2323 uartDmaHandle->dma_rx.receiveAll = receiveAll;
2324 }
2325 else
2326 {
2327 /* Already in reading process. */
2328 return kStatus_HAL_UartDmaRxBusy;
2329 }
2330 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
2331
2332 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
2333 #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2334 HAL_UartDMAIdlelineInterruptHandle(uartHandle->instance);
2335 #endif
2336 #else /* HAL_UART_DMA_RING_BUFFER_ENABLE */
2337 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2338 lpuart_transfer_t xfer;
2339 xfer.data = data;
2340 xfer.dataSize = length;
2341 #endif
2342 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2343
2344 #elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2345 (void)LPUART_ReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, &xfer);
2346 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2347
2348 #endif
2349 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
2350 #else
2351 /* Enable RX interrupt for detecting the IDLE line interrupt. */
2352 LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable);
2353 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2354 return kStatus_HAL_UartDmaSuccess;
2355 }
2356
HAL_UartDMATransferSend(hal_uart_handle_t handle,uint8_t * data,size_t length)2357 hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length)
2358 {
2359 hal_uart_state_t *uartHandle;
2360 hal_uart_dma_state_t *uartDmaHandle;
2361 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2362 lpuart_transfer_t xfer;
2363 #endif
2364 assert(handle);
2365 assert(data);
2366
2367 uartHandle = (hal_uart_state_t *)handle;
2368 uartDmaHandle = uartHandle->dmaHandle;
2369
2370 assert(uartDmaHandle);
2371
2372 if (NULL == uartDmaHandle->dma_tx.buffer)
2373 {
2374 uartDmaHandle->dma_tx.buffer = data;
2375 uartDmaHandle->dma_tx.bufferLength = length;
2376 uartDmaHandle->dma_tx.bufferSofar = 0U;
2377 }
2378 else
2379 {
2380 /* Already in writing process. */
2381 return kStatus_HAL_UartDmaTxBusy;
2382 }
2383
2384 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2385 xfer.data = data;
2386 xfer.dataSize = length;
2387 (void)LPUART_SendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, &xfer);
2388 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2389 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2390
2391 #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U))
2392 #else
2393 /* Enable RX interrupt for detecting the IDLE line interrupt. */
2394 LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable);
2395 #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */
2396
2397 return kStatus_HAL_UartDmaSuccess;
2398 }
2399
HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle,uint32_t * reCount)2400 hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
2401 {
2402 hal_uart_state_t *uartHandle;
2403 hal_uart_dma_state_t *uartDmaHandle;
2404
2405 assert(handle);
2406
2407 uartHandle = (hal_uart_state_t *)handle;
2408 uartDmaHandle = uartHandle->dmaHandle;
2409
2410 assert(uartDmaHandle);
2411 (void)uartDmaHandle;
2412 #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
2413 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
2414
2415 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2416 *reCount = HAL_UartGetDmaReceivedBytes(uartDmaHandle->instance);
2417 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2418 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2419 #else /* HAL_UART_DMA_RING_BUFFER_ENABLE */
2420 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2421 if (kStatus_Success != LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance],
2422 &uartDmaHandle->edmaHandle, reCount))
2423 {
2424 return kStatus_HAL_UartDmaError;
2425 }
2426 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2427 #endif /* FSL_FEATURE_SOC_DMA_COUNT */
2428
2429 #endif
2430 #else
2431 *reCount = 0;
2432
2433 #endif
2434
2435 return kStatus_HAL_UartDmaSuccess;
2436 }
2437
HAL_UartDMAGetSendCount(hal_uart_handle_t handle,uint32_t * seCount)2438 hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
2439 {
2440 hal_uart_state_t *uartHandle;
2441 hal_uart_dma_state_t *uartDmaHandle;
2442
2443 assert(handle);
2444
2445 uartHandle = (hal_uart_state_t *)handle;
2446 uartDmaHandle = uartHandle->dmaHandle;
2447
2448 assert(uartDmaHandle);
2449
2450 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2451 if (kStatus_Success != LPUART_TransferGetSendCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance],
2452 &uartDmaHandle->edmaHandle, seCount))
2453 {
2454 return kStatus_HAL_UartDmaError;
2455 }
2456 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2457
2458 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2459
2460 return kStatus_HAL_UartDmaSuccess;
2461 }
2462
HAL_UartDMAAbortReceive(hal_uart_handle_t handle)2463 hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle)
2464 {
2465 hal_uart_state_t *uartHandle;
2466 hal_uart_dma_state_t *uartDmaHandle;
2467
2468 assert(handle);
2469
2470 uartHandle = (hal_uart_state_t *)handle;
2471 uartDmaHandle = uartHandle->dmaHandle;
2472
2473 assert(uartDmaHandle);
2474
2475 #if (defined(HAL_UART_DMA_RING_BUFFER_ENABLE) && (HAL_UART_DMA_RING_BUFFER_ENABLE > 0U))
2476 /* Make sure to re-initialize the ring bufferIndex */
2477 ringBufferIndex[uartDmaHandle->instance] = 0U;
2478 #endif
2479
2480 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2481 LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle);
2482 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2483 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2484
2485 return kStatus_HAL_UartDmaSuccess;
2486 }
2487
HAL_UartDMAAbortSend(hal_uart_handle_t handle)2488 hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle)
2489 {
2490 hal_uart_state_t *uartHandle;
2491 hal_uart_dma_state_t *uartDmaHandle;
2492
2493 assert(handle);
2494
2495 uartHandle = (hal_uart_state_t *)handle;
2496 uartDmaHandle = uartHandle->dmaHandle;
2497
2498 assert(uartDmaHandle);
2499
2500 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
2501 LPUART_TransferAbortSendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle);
2502 #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
2503 #endif /* FSL_FEATURE_SOC_EDMA_COUNT */
2504
2505 return kStatus_HAL_UartDmaSuccess;
2506 }
2507 #endif /* HAL_UART_DMA_ENABLE */
2508
