1 /*
2 * Copyright 2020,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_flexspi_nor
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/drivers/flash.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/sys/util.h>
14 #include "spi_nor.h"
15 #include "jesd216.h"
16 #include "memc_mcux_flexspi.h"
17
18 #ifdef CONFIG_HAS_MCUX_CACHE
19 #include <fsl_cache.h>
20 #endif
21
22 #define NOR_WRITE_SIZE 1
23 #define NOR_ERASE_VALUE 0xff
24
25 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
26 static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
27 #endif
28
29 /*
30 * NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
31 * called while interacting with the flexspi MUST be relocated to SRAM or ITCM
32 * at runtime, so that the chip does not access the flexspi to read program
33 * instructions while it is being written to
34 *
35 * Additionally, no data used by this driver should be stored in flash.
36 */
37 #if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0)
38 #warning "Enabling flash driver logging and XIP mode simultaneously can cause \
39 read-while-write hazards. This configuration is not recommended."
40 #endif
41
42 LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
43
44 enum {
45 READ,
46 PAGE_PROGRAM,
47 READ_STATUS,
48 WRITE_ENABLE,
49 ERASE_SECTOR,
50 ERASE_BLOCK,
51 READ_ID,
52 READ_STATUS_REG,
53 ERASE_CHIP,
54 READ_JESD216,
55 /* Entries after this should be for scratch commands */
56 FLEXSPI_INSTR_PROG_END,
57 /* Used for temporary commands during initialization */
58 SCRATCH_CMD = FLEXSPI_INSTR_PROG_END,
59 SCRATCH_CMD2,
60 /* Must be last entry */
61 FLEXSPI_INSTR_END,
62 };
63
64 struct flash_flexspi_nor_config {
65 /* Note: don't use this controller reference in code. It is
66 * only used during init to copy the device structure from ROM
67 * into a RAM structure
68 */
69 const struct device *controller;
70 };
71
72 /* Device variables used in critical sections should be in this structure */
73 struct flash_flexspi_nor_data {
74 struct device controller;
75 flexspi_device_config_t config;
76 flexspi_port_t port;
77 bool legacy_poll;
78 struct flash_pages_layout layout;
79 struct flash_parameters flash_parameters;
80 };
81
82 /* Initial LUT table */
83 static const uint32_t flash_flexspi_nor_base_lut[][MEMC_FLEXSPI_CMD_PER_SEQ] = {
84 /* 1S-1S-1S flash read command, should be compatible with all SPI nor flashes */
85 [READ] = {
86 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_READ,
87 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
88 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1,
89 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
90 },
91 [READ_JESD216] = {
92 /* Install read SFDP command */
93 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, JESD216_CMD_READ_SFDP,
94 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
95 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 8,
96 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x4),
97 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0,
98 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
99 },
100 /* Standard 1S-1S-1S flash write command, can be switched to 1S-1S-4S when QE is set */
101 [PAGE_PROGRAM] = {
102 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP,
103 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
104 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
105 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
106 },
107
108 [WRITE_ENABLE] = {
109 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WREN,
110 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
111 },
112
113 [ERASE_SECTOR] = {
114 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE,
115 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
116 },
117
118 [ERASE_BLOCK] = {
119 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE,
120 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
121 },
122
123 [ERASE_CHIP] = {
124 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_CE,
125 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
126 },
127
128 [READ_ID] = {
129 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDID,
130 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
131 },
132
133 [READ_STATUS_REG] = {
134 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
135 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
136 },
137 };
138
139 /* Helper so we can read flash ID without flash access for XIP */
flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data * data,uint8_t * vendor_id)140 static int flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data *data,
141 uint8_t *vendor_id)
142 {
143 uint32_t buffer = 0;
144 int ret;
145
146 flexspi_transfer_t transfer = {
147 .deviceAddress = 0,
148 .port = data->port,
149 .cmdType = kFLEXSPI_Read,
150 .SeqNumber = 1,
151 .seqIndex = READ_ID,
152 .data = &buffer,
153 .dataSize = 3,
154 };
155
156 LOG_DBG("Reading id");
157
158 ret = memc_flexspi_transfer(&data->controller, &transfer);
159 if (ret < 0) {
160 return ret;
161 }
162
163 memcpy(vendor_id, &buffer, 3);
164
165 return ret;
166 }
167
flash_flexspi_nor_read_id(const struct device * dev,uint8_t * vendor_id)168 static int flash_flexspi_nor_read_id(const struct device *dev, uint8_t *vendor_id)
169 {
170 struct flash_flexspi_nor_data *data = dev->data;
171
172 return flash_flexspi_nor_read_id_helper(data, vendor_id);
173 }
174
flash_flexspi_nor_read_status(struct flash_flexspi_nor_data * data,uint32_t * status)175 static int flash_flexspi_nor_read_status(struct flash_flexspi_nor_data *data,
176 uint32_t *status)
177 {
178 flexspi_transfer_t transfer = {
179 .deviceAddress = 0,
180 .port = data->port,
181 .cmdType = kFLEXSPI_Read,
182 .SeqNumber = 1,
183 .seqIndex = READ_STATUS_REG,
184 .data = status,
185 .dataSize = 1,
186 };
187
188 LOG_DBG("Reading status register");
189
190 return memc_flexspi_transfer(&data->controller, &transfer);
191 }
192
flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data * data)193 static int flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data *data)
194 {
195 flexspi_transfer_t transfer = {
196 .deviceAddress = 0,
197 .port = data->port,
198 .cmdType = kFLEXSPI_Command,
199 .SeqNumber = 1,
200 .seqIndex = WRITE_ENABLE,
201 .data = NULL,
202 .dataSize = 0,
203 };
204
205 LOG_DBG("Enabling write");
206
207 return memc_flexspi_transfer(&data->controller, &transfer);
208 }
209
flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data * data,off_t offset)210 static int flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data *data,
211 off_t offset)
212 {
213 flexspi_transfer_t transfer = {
214 .deviceAddress = offset,
215 .port = data->port,
216 .cmdType = kFLEXSPI_Command,
217 .SeqNumber = 1,
218 .seqIndex = ERASE_SECTOR,
219 .data = NULL,
220 .dataSize = 0,
221 };
222
223 LOG_DBG("Erasing sector at 0x%08zx", (ssize_t) offset);
224
225 return memc_flexspi_transfer(&data->controller, &transfer);
226 }
227
flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data * data,off_t offset)228 static int flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data *data,
229 off_t offset)
230 {
231 flexspi_transfer_t transfer = {
232 .deviceAddress = offset,
233 .port = data->port,
234 .cmdType = kFLEXSPI_Command,
235 .SeqNumber = 1,
236 .seqIndex = ERASE_BLOCK,
237 .data = NULL,
238 .dataSize = 0,
239 };
240
241 LOG_DBG("Erasing block at 0x%08zx", (ssize_t) offset);
242
243 return memc_flexspi_transfer(&data->controller, &transfer);
244 }
245
flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data * data)246 static int flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data *data)
247 {
248 flexspi_transfer_t transfer = {
249 .deviceAddress = 0,
250 .port = data->port,
251 .cmdType = kFLEXSPI_Command,
252 .SeqNumber = 1,
253 .seqIndex = ERASE_CHIP,
254 .data = NULL,
255 .dataSize = 0,
256 };
257
258 LOG_DBG("Erasing chip");
259
260 return memc_flexspi_transfer(&data->controller, &transfer);
261 }
262
flash_flexspi_nor_page_program(struct flash_flexspi_nor_data * data,off_t offset,const void * buffer,size_t len)263 static int flash_flexspi_nor_page_program(struct flash_flexspi_nor_data *data,
264 off_t offset, const void *buffer, size_t len)
265 {
266 flexspi_transfer_t transfer = {
267 .deviceAddress = offset,
268 .port = data->port,
269 .cmdType = kFLEXSPI_Write,
270 .SeqNumber = 1,
271 .seqIndex = PAGE_PROGRAM,
272 .data = (uint32_t *) buffer,
273 .dataSize = len,
274 };
275
276 LOG_DBG("Page programming %d bytes to 0x%08zx", len, (ssize_t) offset);
277
278 return memc_flexspi_transfer(&data->controller, &transfer);
279 }
280
flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data * data)281 static int flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data *data)
282 {
283 uint32_t status = 0;
284 int ret;
285
286 while (1) {
287 ret = flash_flexspi_nor_read_status(data, &status);
288 LOG_DBG("status: 0x%x", status);
289 if (ret) {
290 LOG_ERR("Could not read status");
291 return ret;
292 }
293
294 if (data->legacy_poll) {
295 if ((status & BIT(0)) == 0) {
296 break;
297 }
298 } else {
299 if (status & BIT(7)) {
300 break;
301 }
302 }
303 }
304
305 return 0;
306 }
307
flash_flexspi_nor_read(const struct device * dev,off_t offset,void * buffer,size_t len)308 static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
309 void *buffer, size_t len)
310 {
311 struct flash_flexspi_nor_data *data = dev->data;
312 uint8_t *src = memc_flexspi_get_ahb_address(&data->controller,
313 data->port,
314 offset);
315
316 memcpy(buffer, src, len);
317
318 return 0;
319 }
320
flash_flexspi_nor_write(const struct device * dev,off_t offset,const void * buffer,size_t len)321 static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
322 const void *buffer, size_t len)
323 {
324 struct flash_flexspi_nor_data *data = dev->data;
325 size_t size = len;
326 uint8_t *src = (uint8_t *) buffer;
327 int i;
328 unsigned int key = 0;
329
330 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
331 data->port,
332 offset);
333
334 if (memc_flexspi_is_running_xip(&data->controller)) {
335 /*
336 * ==== ENTER CRITICAL SECTION ====
337 * No flash access should be performed in critical section. All
338 * code and data accessed must reside in ram.
339 */
340 key = irq_lock();
341 }
342
343 while (len) {
344 /* If the offset isn't a multiple of the NOR page size, we first need
345 * to write the remaining part that fits, otherwise the write could
346 * be wrapped around within the same page
347 */
348 i = MIN(SPI_NOR_PAGE_SIZE - (offset % SPI_NOR_PAGE_SIZE), len);
349 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
350 memcpy(nor_write_buf, src, i);
351 #endif
352 flash_flexspi_nor_write_enable(data);
353 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
354 flash_flexspi_nor_page_program(data, offset, nor_write_buf, i);
355 #else
356 flash_flexspi_nor_page_program(data, offset, src, i);
357 #endif
358 flash_flexspi_nor_wait_bus_busy(data);
359 memc_flexspi_reset(&data->controller);
360 src += i;
361 offset += i;
362 len -= i;
363 }
364
365 if (memc_flexspi_is_running_xip(&data->controller)) {
366 /* ==== EXIT CRITICAL SECTION ==== */
367 irq_unlock(key);
368 }
369
370 #ifdef CONFIG_HAS_MCUX_CACHE
371 DCACHE_InvalidateByRange((uint32_t) dst, size);
372 #endif
373
374 return 0;
375 }
376
flash_flexspi_nor_erase(const struct device * dev,off_t offset,size_t size)377 static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
378 size_t size)
379 {
380 struct flash_flexspi_nor_data *data = dev->data;
381 const size_t num_sectors = size / SPI_NOR_SECTOR_SIZE;
382 const size_t num_blocks = size / SPI_NOR_BLOCK_SIZE;
383
384 int i;
385 unsigned int key = 0;
386
387 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
388 data->port,
389 offset);
390
391 if (offset % SPI_NOR_SECTOR_SIZE) {
392 LOG_ERR("Invalid offset");
393 return -EINVAL;
394 }
395
396 if (size % SPI_NOR_SECTOR_SIZE) {
397 LOG_ERR("Invalid size");
398 return -EINVAL;
399 }
400
401 if (memc_flexspi_is_running_xip(&data->controller)) {
402 /*
403 * ==== ENTER CRITICAL SECTION ====
404 * No flash access should be performed in critical section. All
405 * code and data accessed must reside in ram.
406 */
407 key = irq_lock();
408 }
409
410 if ((offset == 0) && (size == data->config.flashSize * KB(1))) {
411 flash_flexspi_nor_write_enable(data);
412 flash_flexspi_nor_erase_chip(data);
413 flash_flexspi_nor_wait_bus_busy(data);
414 memc_flexspi_reset(&data->controller);
415 } else if ((0 == (offset % SPI_NOR_BLOCK_SIZE)) && (0 == (size % SPI_NOR_BLOCK_SIZE))) {
416 for (i = 0; i < num_blocks; i++) {
417 flash_flexspi_nor_write_enable(data);
418 flash_flexspi_nor_erase_block(data, offset);
419 flash_flexspi_nor_wait_bus_busy(data);
420 memc_flexspi_reset(&data->controller);
421 offset += SPI_NOR_BLOCK_SIZE;
422 }
423 } else {
424 for (i = 0; i < num_sectors; i++) {
425 flash_flexspi_nor_write_enable(data);
426 flash_flexspi_nor_erase_sector(data, offset);
427 flash_flexspi_nor_wait_bus_busy(data);
428 memc_flexspi_reset(&data->controller);
429 offset += SPI_NOR_SECTOR_SIZE;
430 }
431 }
432
433 if (memc_flexspi_is_running_xip(&data->controller)) {
434 /* ==== EXIT CRITICAL SECTION ==== */
435 irq_unlock(key);
436 }
437
438 #ifdef CONFIG_HAS_MCUX_CACHE
439 DCACHE_InvalidateByRange((uint32_t) dst, size);
440 #endif
441
442 return 0;
443 }
444
flash_flexspi_nor_get_parameters(const struct device * dev)445 static const struct flash_parameters *flash_flexspi_nor_get_parameters(
446 const struct device *dev)
447 {
448 struct flash_flexspi_nor_data *data = dev->data;
449
450 return &data->flash_parameters;
451 }
452
453 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_flexspi_nor_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)454 static void flash_flexspi_nor_pages_layout(const struct device *dev,
455 const struct flash_pages_layout **layout, size_t *layout_size)
456 {
457 struct flash_flexspi_nor_data *data = dev->data;
458
459 *layout = &data->layout;
460 *layout_size = 1;
461 }
462 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
463
464
465 /*
466 * This function enables quad mode, when supported. Otherwise it
467 * returns an error.
468 * @param dev: Flexspi device
469 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
470 * @param qer: DW15 quad enable parameter
471 * @return 0 if quad mode was entered, or -ENOTSUP if quad mode is not supported
472 */
flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint8_t qer)473 static int flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data *data,
474 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
475 uint8_t qer)
476 {
477 int ret;
478 uint32_t buffer = 0;
479 uint16_t bit = 0;
480 uint8_t rd_size, wr_size;
481 flexspi_transfer_t transfer = {
482 .deviceAddress = 0,
483 .port = data->port,
484 .SeqNumber = 1,
485 .data = &buffer,
486 };
487 flexspi_device_config_t config = {
488 .flexspiRootClk = MHZ(50),
489 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
490 .ARDSeqNumber = 1,
491 .ARDSeqIndex = READ,
492 };
493
494 switch (qer) {
495 case JESD216_DW15_QER_VAL_NONE:
496 /* No init needed */
497 return 0;
498 case JESD216_DW15_QER_VAL_S2B1v1:
499 case JESD216_DW15_QER_VAL_S2B1v4:
500 /* Install read and write status command */
501 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
502 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
503 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
504 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
505 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
506 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
507
508 /* Set bit 1 of status register 2 */
509 bit = BIT(9);
510 rd_size = 2;
511 wr_size = 2;
512 break;
513 case JESD216_DW15_QER_VAL_S1B6:
514 /* Install read and write status command */
515 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
516 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
517 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
518 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
519 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
520 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
521
522 /* Set bit 6 of status register 1 */
523 bit = BIT(6);
524 rd_size = 1;
525 wr_size = 1;
526 break;
527 case JESD216_DW15_QER_VAL_S2B7:
528 /* Install read and write status command */
529 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
530 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3F,
531 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
532 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
533 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3E,
534 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
535
536 /* Set bit 7 of status register 2 */
537 bit = BIT(7);
538 rd_size = 1;
539 wr_size = 1;
540 break;
541 case JESD216_DW15_QER_VAL_S2B1v5:
542 /* Install read and write status command */
543 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
544 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
545 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
546 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
547 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
548 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
549
550 /* Set bit 1 of status register 2 */
551 bit = BIT(9);
552 rd_size = 1;
553 wr_size = 2;
554 break;
555 case JESD216_DW15_QER_VAL_S2B1v6:
556 /* Install read and write status command */
557 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
558 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
559 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
560 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
561 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR2,
562 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
563
564 /* Set bit 7 of status register 2 */
565 bit = BIT(7);
566 rd_size = 1;
567 wr_size = 1;
568 break;
569 default:
570 return -ENOTSUP;
571 }
572 ret = memc_flexspi_set_device_config(&data->controller,
573 &config,
574 (uint32_t *)flexspi_lut,
575 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
576 data->port);
577 if (ret < 0) {
578 return ret;
579 }
580 transfer.dataSize = rd_size;
581 transfer.seqIndex = SCRATCH_CMD;
582 transfer.cmdType = kFLEXSPI_Read;
583 /* Read status register */
584 ret = memc_flexspi_transfer(&data->controller, &transfer);
585 if (ret < 0) {
586 return ret;
587 }
588 buffer |= bit;
589 transfer.dataSize = wr_size;
590 transfer.seqIndex = SCRATCH_CMD2;
591 transfer.cmdType = kFLEXSPI_Write;
592 return memc_flexspi_transfer(&data->controller, &transfer);
593 }
594
595 /*
596 * This function enables 4 byte addressing, when supported. Otherwise it
597 * returns an error.
598 * @param dev: Flexspi device
599 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
600 * @param en4b: DW16 enable 4 byte mode parameter
601 * @return 0 if 4 byte mode was entered, or -ENOTSUP if 4 byte mode was not supported
602 */
flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint32_t en4b)603 static int flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data *data,
604 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
605 uint32_t en4b)
606 {
607 int ret;
608 uint32_t buffer = 0;
609 flexspi_transfer_t transfer = {
610 .deviceAddress = 0,
611 .port = data->port,
612 .SeqNumber = 1,
613 .data = &buffer,
614 };
615 flexspi_device_config_t config = {
616 .flexspiRootClk = MHZ(50),
617 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
618 .ARDSeqNumber = 1,
619 .ARDSeqIndex = READ,
620 };
621 if (en4b & BIT(6)) {
622 /* Flash is always in 4 byte mode. We just need to configure LUT */
623 return 0;
624 } else if (en4b & BIT(5)) {
625 /* Dedicated vendor instruction set, which we don't support. Exit here */
626 return -ENOTSUP;
627 } else if (en4b & BIT(4)) {
628 /* Set bit 0 of 16 bit configuration register */
629 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
630 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB5,
631 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
632 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
633 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB1,
634 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
635 ret = memc_flexspi_set_device_config(&data->controller,
636 &config,
637 (uint32_t *)flexspi_lut,
638 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
639 data->port);
640 if (ret < 0) {
641 return ret;
642 }
643 transfer.dataSize = 2;
644 transfer.seqIndex = SCRATCH_CMD;
645 transfer.cmdType = kFLEXSPI_Read;
646 /* Read config register */
647 ret = memc_flexspi_transfer(&data->controller, &transfer);
648 if (ret < 0) {
649 return ret;
650 }
651 buffer |= BIT(0);
652 /* Set config register */
653 transfer.seqIndex = SCRATCH_CMD2;
654 transfer.cmdType = kFLEXSPI_Read;
655 return memc_flexspi_transfer(&data->controller, &transfer);
656 } else if (en4b & BIT(1)) {
657 /* Issue write enable, then instruction 0xB7 */
658 flash_flexspi_nor_write_enable(data);
659 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
660 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
661 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
662 ret = memc_flexspi_set_device_config(&data->controller,
663 &config,
664 (uint32_t *)flexspi_lut,
665 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
666 data->port);
667 if (ret < 0) {
668 return ret;
669 }
670 transfer.dataSize = 0;
671 transfer.seqIndex = SCRATCH_CMD;
672 transfer.cmdType = kFLEXSPI_Command;
673 return memc_flexspi_transfer(&data->controller, &transfer);
674 } else if (en4b & BIT(0)) {
675 /* Issue instruction 0xB7 */
676 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
677 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
678 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
679 ret = memc_flexspi_set_device_config(&data->controller,
680 &config,
681 (uint32_t *)flexspi_lut,
682 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
683 data->port);
684 if (ret < 0) {
685 return ret;
686 }
687 transfer.dataSize = 0;
688 transfer.seqIndex = SCRATCH_CMD;
689 transfer.cmdType = kFLEXSPI_Command;
690 return memc_flexspi_transfer(&data->controller, &transfer);
691 }
692 /* Other methods not supported */
693 return -ENOTSUP;
694 }
695
696 /*
697 * This function configures the FlexSPI to manage the flash device
698 * based on values in SFDP header
699 * @param data: Flexspi device data
700 * @param header: SFDP header for flash
701 * @param bfp: basic flash parameters for flash
702 * @param flexspi_lut: LUT table, filled with READ LUT command
703 * @return 0 on success, or negative value on error
704 */
flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data * data,struct jesd216_sfdp_header * header,struct jesd216_bfp * bfp,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])705 static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
706 struct jesd216_sfdp_header *header,
707 struct jesd216_bfp *bfp,
708 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
709 {
710 struct jesd216_instr instr;
711 struct jesd216_bfp_dw16 dw16;
712 struct jesd216_bfp_dw15 dw15;
713 struct jesd216_bfp_dw14 dw14;
714 uint8_t addr_width;
715 uint8_t mode_cmd;
716 int ret;
717
718 addr_width = jesd216_bfp_addrbytes(bfp) ==
719 JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B ? 32 : 24;
720
721 /* Check to see if we can enable 4 byte addressing */
722 ret = jesd216_bfp_decode_dw16(&header->phdr[0], bfp, &dw16);
723 if (ret == 0) {
724 /* Attempt to enable 4 byte addressing */
725 ret = flash_flexspi_nor_4byte_enable(data, flexspi_lut,
726 dw16.enter_4ba);
727 if (ret == 0) {
728 /* Use 4 byte address width */
729 addr_width = 32;
730 /* Update LUT for ERASE_SECTOR and ERASE_BLOCK to use 32 bit addr */
731 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
732 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
733 SPI_NOR_CMD_SE, kFLEXSPI_Command_RADDR_SDR,
734 kFLEXSPI_1PAD, addr_width);
735 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
736 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
737 SPI_NOR_CMD_BE, kFLEXSPI_Command_RADDR_SDR,
738 kFLEXSPI_1PAD, addr_width);
739 }
740 }
741 /* Extract the read command.
742 * Note- enhanced XIP not currently supported, nor is 4-4-4 mode.
743 */
744 if (jesd216_bfp_read_support(&header->phdr[0], bfp,
745 JESD216_MODE_144, &instr) > 0) {
746 LOG_DBG("Enable 144 mode");
747 /* Configure for 144 QUAD read mode */
748 if (instr.mode_clocks == 2) {
749 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
750 } else if (instr.mode_clocks == 1) {
751 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
752 } else if (instr.mode_clocks == 0) {
753 /* Just send dummy cycles during mode clock period */
754 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
755 } else {
756 return -ENOTSUP;
757 }
758 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
759 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
760 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, addr_width);
761 /* Note- we always set mode bits to 0x0 */
762 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
763 mode_cmd, kFLEXSPI_4PAD, 0x00,
764 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, instr.wait_states);
765 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
766 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04,
767 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
768 /* Read 1S-4S-4S enable method */
769 ret = jesd216_bfp_decode_dw15(&header->phdr[0], bfp, &dw15);
770 if (ret == 0) {
771 ret = flash_flexspi_nor_quad_enable(data, flexspi_lut,
772 dw15.qer);
773 if (ret == 0) {
774 /* Now, install 1S-1S-4S page program command */
775 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
776 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD,
777 SPI_NOR_CMD_PP_1_1_4, kFLEXSPI_Command_RADDR_SDR,
778 kFLEXSPI_1PAD, addr_width);
779 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
780 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD,
781 0x4, kFLEXSPI_Command_STOP,
782 kFLEXSPI_1PAD, 0x0);
783 }
784 }
785
786 } else if (jesd216_bfp_read_support(&header->phdr[0], bfp,
787 JESD216_MODE_122, &instr) > 0) {
788 LOG_DBG("Enable 122 mode");
789 if (instr.mode_clocks == 4) {
790 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
791 } else if (instr.mode_clocks == 2) {
792 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
793 } else if (instr.mode_clocks == 1) {
794 mode_cmd = kFLEXSPI_Command_MODE2_SDR;
795 } else if (instr.mode_clocks == 0) {
796 /* Just send dummy cycles during mode clock period */
797 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
798 } else {
799 return -ENOTSUP;
800 }
801 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
802 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
803 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_2PAD, addr_width);
804 /* Note- we always set mode bits to 0x0 */
805 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
806 mode_cmd, kFLEXSPI_2PAD, 0x0,
807 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_2PAD, instr.wait_states);
808 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
809 kFLEXSPI_Command_READ_SDR, kFLEXSPI_2PAD, 0x02,
810 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
811 /* Now, install 1S-1S-2S page program command */
812 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
813 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_2,
814 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
815 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
816 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_2PAD, 0x4,
817 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
818 }
819 /* Default to 111 mode if no support exists, leave READ/WRITE untouched */
820
821 /* Now, read DW14 to determine the polling method we should use while programming */
822 ret = jesd216_bfp_decode_dw14(&header->phdr[0], bfp, &dw14);
823 if (ret < 0) {
824 /* Default to legacy polling mode */
825 dw14.poll_options = 0x0;
826 }
827 if (dw14.poll_options & BIT(1)) {
828 /* Read instruction used for polling is 0x70 */
829 data->legacy_poll = false;
830 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
831 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x70,
832 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
833 } else {
834 /* Read instruction used for polling is 0x05 */
835 data->legacy_poll = true;
836 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
837 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
838 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
839 }
840
841 return 0;
842 }
843
844 /* Helper so we can avoid flash access while performing SFDP probe */
flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data * dev_data,off_t offset,void * data,size_t len)845 static int flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data *dev_data,
846 off_t offset, void *data, size_t len)
847 {
848 flexspi_transfer_t transfer = {
849 .deviceAddress = offset,
850 .port = dev_data->port,
851 .cmdType = kFLEXSPI_Read,
852 .seqIndex = READ_JESD216,
853 .SeqNumber = 1,
854 .data = (uint32_t *)data,
855 .dataSize = len,
856 };
857
858 /* Get SFDP data */
859 return memc_flexspi_transfer(&dev_data->controller, &transfer);
860 }
861
862
863 #if defined(CONFIG_FLASH_JESD216_API)
864
flash_flexspi_nor_sfdp_read(const struct device * dev,off_t offset,void * data,size_t len)865 static int flash_flexspi_nor_sfdp_read(const struct device *dev,
866 off_t offset, void *data, size_t len)
867 {
868 struct flash_flexspi_nor_data *dev_data = dev->data;
869
870 return flash_flexspi_nor_sfdp_read_helper(dev_data, offset, data, len);
871 }
872
873 #endif
874
875 /* Checks JEDEC ID of flash. If supported, installs custom LUT table */
flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])876 static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
877 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
878 {
879 int ret;
880 uint32_t vendor_id;
881
882 ret = flash_flexspi_nor_read_id_helper(data, (uint8_t *)&vendor_id);
883 if (ret < 0) {
884 return ret;
885 }
886
887 /* Switch on manufacturer and vendor ID */
888 switch (vendor_id & 0xFFFF) {
889 case 0x25C2:
890 /* MX25 flash, use 4 byte read/write */
891 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
892 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
893 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
894 /* Flash needs 10 dummy cycles */
895 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
896 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 10,
897 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
898 /* Only 1S-4S-4S page program supported */
899 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
900 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_4_4_4B,
901 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
902 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
903 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
904 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
905 /* Update ERASE commands for 4 byte mode */
906 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
907 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
908 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
909 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
910 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
911 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
912 /* Read instruction used for polling is 0x05 */
913 data->legacy_poll = true;
914 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
915 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
916 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
917 /* Device uses bit 6 of status reg 1 for QE */
918 return flash_flexspi_nor_quad_enable(data, flexspi_lut, JESD216_DW15_QER_VAL_S1B6);
919 default:
920 return -ENOTSUP;
921 }
922 }
923
924 /* Probe parameters from flash SFDP header, and use them to configure the FlexSPI */
flash_flexspi_nor_probe(struct flash_flexspi_nor_data * data)925 static int flash_flexspi_nor_probe(struct flash_flexspi_nor_data *data)
926 {
927 uint32_t flexspi_lut[FLEXSPI_INSTR_END][MEMC_FLEXSPI_CMD_PER_SEQ] = {0};
928 /* JESD216B defines up to 23 basic flash parameters */
929 uint32_t param_buf[23];
930 /* Space to store SFDP header and first parameter header */
931 uint8_t sfdp_buf[JESD216_SFDP_SIZE(1)] __aligned(4);
932 struct jesd216_bfp *bfp = (struct jesd216_bfp *)param_buf;
933 struct jesd216_sfdp_header *header = (struct jesd216_sfdp_header *)sfdp_buf;
934 int ret;
935 unsigned int key = 0U;
936
937 flexspi_device_config_t config = {
938 .flexspiRootClk = MHZ(50),
939 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
940 .ARDSeqNumber = 1,
941 .ARDSeqIndex = READ,
942 };
943
944 if (memc_flexspi_is_running_xip(&data->controller)) {
945 /*
946 * ==== ENTER CRITICAL SECTION ====
947 * No flash access should be performed in critical section. All
948 * code and data accessed must reside in ram.
949 */
950 key = irq_lock();
951 memc_flexspi_wait_bus_idle(&data->controller);
952 }
953
954 /* SFDP spec requires that we downclock the FlexSPI to 50MHz or less */
955 ret = memc_flexspi_update_clock(&data->controller, &config,
956 data->port, MHZ(50));
957 if (ret < 0) {
958 goto _exit;
959 }
960
961 /* Setup initial LUT table and FlexSPI configuration */
962 memcpy(flexspi_lut, flash_flexspi_nor_base_lut, sizeof(flash_flexspi_nor_base_lut));
963
964 ret = memc_flexspi_set_device_config(&data->controller, &config,
965 (uint32_t *)flexspi_lut,
966 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
967 data->port);
968 if (ret < 0) {
969 goto _exit;
970 }
971
972 /* First, check if the JEDEC ID of this flash has explicit support
973 * in this driver
974 */
975 ret = flash_flexspi_nor_check_jedec(data, flexspi_lut);
976 if (ret == 0) {
977 /* Flash was supported, SFDP probe not needed */
978 goto _program_lut;
979 }
980
981 ret = flash_flexspi_nor_sfdp_read_helper(data, 0, sfdp_buf, sizeof(sfdp_buf));
982 if (ret < 0) {
983 goto _exit;
984 }
985
986 LOG_DBG("SFDP header magic: 0x%x", header->magic);
987 if (jesd216_sfdp_magic(header) != JESD216_SFDP_MAGIC) {
988 /* Header was read incorrectly */
989 LOG_WRN("Invalid header, using legacy SPI mode");
990 data->legacy_poll = true;
991 goto _program_lut;
992 }
993
994 if (header->phdr[0].len_dw > ARRAY_SIZE(param_buf)) {
995 /* Not enough space to read parameter table */
996 ret = -ENOBUFS;
997 goto _exit;
998 }
999
1000 /* Read basic flash parameter table */
1001 ret = flash_flexspi_nor_sfdp_read_helper(data,
1002 jesd216_param_addr(&header->phdr[0]),
1003 param_buf,
1004 sizeof(uint32_t) * header->phdr[0].len_dw);
1005 if (ret < 0) {
1006 goto _exit;
1007 }
1008
1009 /* Configure flash */
1010 ret = flash_flexspi_nor_config_flash(data, header, bfp, flexspi_lut);
1011 if (ret < 0) {
1012 goto _exit;
1013 }
1014
1015 _program_lut:
1016 /*
1017 * Update the FlexSPI with the config structure provided
1018 * from devicetree and the configured LUT
1019 */
1020 ret = memc_flexspi_set_device_config(&data->controller, &data->config,
1021 (uint32_t *)flexspi_lut,
1022 FLEXSPI_INSTR_PROG_END * MEMC_FLEXSPI_CMD_PER_SEQ,
1023 data->port);
1024 if (ret < 0) {
1025 return ret;
1026 }
1027
1028 _exit:
1029 memc_flexspi_reset(&data->controller);
1030
1031 if (memc_flexspi_is_running_xip(&data->controller)) {
1032 /* ==== EXIT CRITICAL SECTION ==== */
1033 irq_unlock(key);
1034 }
1035
1036 return ret;
1037 }
1038
flash_flexspi_nor_init(const struct device * dev)1039 static int flash_flexspi_nor_init(const struct device *dev)
1040 {
1041 const struct flash_flexspi_nor_config *config = dev->config;
1042 struct flash_flexspi_nor_data *data = dev->data;
1043 uint32_t vendor_id;
1044
1045 /* First step- use ROM pointer to controller device to create
1046 * a copy of the device structure in RAM we can use while in
1047 * critical sections of code.
1048 */
1049 memcpy(&data->controller, config->controller, sizeof(struct device));
1050
1051 if (!device_is_ready(&data->controller)) {
1052 LOG_ERR("Controller device is not ready");
1053 return -ENODEV;
1054 }
1055
1056 if (flash_flexspi_nor_probe(data)) {
1057 if (memc_flexspi_is_running_xip(&data->controller)) {
1058 /* We can't continue from here- the LUT stored in
1059 * the FlexSPI will be invalid so we cannot XIP.
1060 * Instead, spin here
1061 */
1062 while (1) {
1063 /* Spin */
1064 }
1065 }
1066 LOG_ERR("SFDP probe failed");
1067 return -EIO;
1068 }
1069
1070 /* Set the FlexSPI to full clock speed */
1071 if (memc_flexspi_update_clock(&data->controller, &data->config,
1072 data->port, data->config.flexspiRootClk)) {
1073 LOG_ERR("Could not set flexspi clock speed");
1074 return -ENOTSUP;
1075 }
1076
1077
1078 memc_flexspi_reset(&data->controller);
1079
1080 if (flash_flexspi_nor_read_id(dev, (uint8_t *)&vendor_id)) {
1081 LOG_ERR("Could not read vendor id");
1082 return -EIO;
1083 }
1084 LOG_DBG("Vendor id: 0x%0x", vendor_id);
1085
1086 return 0;
1087 }
1088
1089 static const struct flash_driver_api flash_flexspi_nor_api = {
1090 .erase = flash_flexspi_nor_erase,
1091 .write = flash_flexspi_nor_write,
1092 .read = flash_flexspi_nor_read,
1093 .get_parameters = flash_flexspi_nor_get_parameters,
1094 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
1095 .page_layout = flash_flexspi_nor_pages_layout,
1096 #endif
1097 #if defined(CONFIG_FLASH_JESD216_API)
1098 .sfdp_read = flash_flexspi_nor_sfdp_read,
1099 .read_jedec_id = flash_flexspi_nor_read_id,
1100 #endif
1101 };
1102
1103 #define CONCAT3(x, y, z) x ## y ## z
1104
1105 #define CS_INTERVAL_UNIT(unit) \
1106 CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
1107
1108 #define AHB_WRITE_WAIT_UNIT(unit) \
1109 CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
1110
1111 #define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
1112 { \
1113 .flexspiRootClk = DT_INST_PROP(n, spi_max_frequency), \
1114 .flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
1115 .CSIntervalUnit = \
1116 CS_INTERVAL_UNIT( \
1117 DT_INST_PROP(n, cs_interval_unit)), \
1118 .CSInterval = DT_INST_PROP(n, cs_interval), \
1119 .CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
1120 .CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
1121 .dataValidTime = DT_INST_PROP(n, data_valid_time), \
1122 .columnspace = DT_INST_PROP(n, column_space), \
1123 .enableWordAddress = DT_INST_PROP(n, word_addressable), \
1124 .AWRSeqIndex = 0, \
1125 .AWRSeqNumber = 0, \
1126 .ARDSeqIndex = READ, \
1127 .ARDSeqNumber = 1, \
1128 .AHBWriteWaitUnit = \
1129 AHB_WRITE_WAIT_UNIT( \
1130 DT_INST_PROP(n, ahb_write_wait_unit)), \
1131 .AHBWriteWaitInterval = \
1132 DT_INST_PROP(n, ahb_write_wait_interval), \
1133 } \
1134
1135 #define FLASH_FLEXSPI_NOR(n) \
1136 static const struct flash_flexspi_nor_config \
1137 flash_flexspi_nor_config_##n = { \
1138 .controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
1139 }; \
1140 static struct flash_flexspi_nor_data \
1141 flash_flexspi_nor_data_##n = { \
1142 .config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
1143 .port = DT_INST_REG_ADDR(n), \
1144 .layout = { \
1145 .pages_count = DT_INST_PROP(n, size) / 8 \
1146 / SPI_NOR_SECTOR_SIZE, \
1147 .pages_size = SPI_NOR_SECTOR_SIZE, \
1148 }, \
1149 .flash_parameters = { \
1150 .write_block_size = NOR_WRITE_SIZE, \
1151 .erase_value = NOR_ERASE_VALUE, \
1152 }, \
1153 }; \
1154 \
1155 DEVICE_DT_INST_DEFINE(n, \
1156 flash_flexspi_nor_init, \
1157 NULL, \
1158 &flash_flexspi_nor_data_##n, \
1159 &flash_flexspi_nor_config_##n, \
1160 POST_KERNEL, \
1161 CONFIG_FLASH_INIT_PRIORITY, \
1162 &flash_flexspi_nor_api);
1163
1164 DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)
1165
