1 /*
2 * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT neorv32_uart
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/syscon.h>
11 #include <zephyr/drivers/uart.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/pm/device.h>
15 #include <zephyr/spinlock.h>
16 #include <zephyr/sys/sys_io.h>
17
18 #include <soc.h>
19
20 LOG_MODULE_REGISTER(uart_neorv32, CONFIG_UART_LOG_LEVEL);
21
22 /* NEORV32 UART registers offsets */
23 #define NEORV32_UART_CTRL 0x00
24 #define NEORV32_UART_DATA 0x04
25
26 /* NEORV32 UART CTRL register bits */
27 #define NEORV32_UART_CTRL_EN BIT(0)
28 #define NEORV32_UART_CTRL_SIM_MODE BIT(1)
29 #define NEORV32_UART_CTRL_HWFC_EN BIT(2)
30 #define NEORV32_UART_CTRL_PRSC GENMASK(5, 3)
31 #define NEORV32_UART_CTRL_BAUD GENMASK(15, 6)
32 #define NEORV32_UART_CTRL_RX_NEMPTY BIT(16)
33 #define NEORV32_UART_CTRL_RX_HALF BIT(17)
34 #define NEORV32_UART_CTRL_RX_FULL BIT(18)
35 #define NEORV32_UART_CTRL_TX_EMPTY BIT(19)
36 #define NEORV32_UART_CTRL_TX_NHALF BIT(20)
37 #define NEORV32_UART_CTRL_TX_FULL BIT(21)
38 #define NEORV32_UART_CTRL_IRQ_RX_NEMPTY BIT(22)
39 #define NEORV32_UART_CTRL_IRQ_RX_HALF BIT(23)
40 #define NEORV32_UART_CTRL_IRQ_RX_FULL BIT(24)
41 #define NEORV32_UART_CTRL_IRQ_TX_EMPTY BIT(25)
42 #define NEORV32_UART_CTRL_IRQ_TX_NHALF BIT(26)
43 #define NEORV32_UART_CTRL_UART_CTRL_RX_CLR BIT(28)
44 #define NEORV32_UART_CTRL_UART_CTRL_TX_CLR BIT(29)
45 #define NEORV32_UART_CTRL_RX_OVER BIT(30)
46 #define NEORV32_UART_CTRL_TX_BUSY BIT(31)
47
48 /* NEORV32 UART DATA register bits */
49 #define NEORV32_UART_DATA_RTX GENMASK(7, 0)
50 #define NEORV32_UART_DATA_RX_FIFO_SIZE GENMASK(11, 8)
51 #define NEORV32_UART_DATA_TX_FIFO_SIZE GENMASK(15, 12)
52
53 struct neorv32_uart_config {
54 const struct device *syscon;
55 uint32_t feature_mask;
56 mm_reg_t base;
57 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
58 void (*irq_config_func)(const struct device *dev);
59 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
60 };
61
62 struct neorv32_uart_data {
63 struct uart_config uart_cfg;
64 struct k_spinlock lock;
65 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
66 uart_irq_callback_user_data_t callback;
67 void *callback_data;
68 uint32_t last_ctrl;
69 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
70 };
71
neorv32_uart_read_ctrl(const struct device * dev)72 static inline uint32_t neorv32_uart_read_ctrl(const struct device *dev)
73 {
74 const struct neorv32_uart_config *config = dev->config;
75
76 return sys_read32(config->base + NEORV32_UART_CTRL);
77 }
78
neorv32_uart_write_ctrl(const struct device * dev,uint32_t ctrl)79 static inline void neorv32_uart_write_ctrl(const struct device *dev, uint32_t ctrl)
80 {
81 const struct neorv32_uart_config *config = dev->config;
82
83 sys_write32(ctrl, config->base + NEORV32_UART_CTRL);
84 }
85
neorv32_uart_read_data(const struct device * dev)86 static inline uint32_t neorv32_uart_read_data(const struct device *dev)
87 {
88 const struct neorv32_uart_config *config = dev->config;
89
90 return sys_read32(config->base + NEORV32_UART_DATA);
91 }
92
neorv32_uart_write_data(const struct device * dev,uint32_t data)93 static inline void neorv32_uart_write_data(const struct device *dev, uint32_t data)
94 {
95 const struct neorv32_uart_config *config = dev->config;
96
97 sys_write32(data, config->base + NEORV32_UART_DATA);
98 }
99
neorv32_uart_poll_in(const struct device * dev,unsigned char * c)100 static int neorv32_uart_poll_in(const struct device *dev, unsigned char *c)
101 {
102 uint32_t ctrl;
103
104 ctrl = neorv32_uart_read_ctrl(dev);
105 if ((ctrl & NEORV32_UART_CTRL_RX_NEMPTY) != 0U) {
106 *c = neorv32_uart_read_data(dev) & NEORV32_UART_DATA_RTX;
107 return 0;
108 }
109
110 return -1;
111 }
112
neorv32_uart_poll_out(const struct device * dev,unsigned char c)113 static void neorv32_uart_poll_out(const struct device *dev, unsigned char c)
114 {
115 while ((neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_TX_FULL) != 0U) {
116 }
117
118 neorv32_uart_write_data(dev, c);
119 }
120
neorv32_uart_configure(const struct device * dev,const struct uart_config * cfg)121 static int neorv32_uart_configure(const struct device *dev, const struct uart_config *cfg)
122 {
123 const uint16_t baudxx_max = FIELD_GET(NEORV32_UART_CTRL_BAUD, NEORV32_UART_CTRL_BAUD);
124 const uint8_t prscx_max = FIELD_GET(NEORV32_UART_CTRL_PRSC, NEORV32_UART_CTRL_PRSC);
125 const struct neorv32_uart_config *config = dev->config;
126 struct neorv32_uart_data *data = dev->data;
127 k_spinlock_key_t key;
128 uint16_t baudxx = 0;
129 uint8_t prscx = 0;
130 uint32_t ctrl;
131 bool hwfc_en;
132 uint32_t clk;
133 int err;
134
135 __ASSERT_NO_MSG(cfg != NULL);
136
137 if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
138 LOG_ERR("hardware only supports one stop bit");
139 return -ENOTSUP;
140 }
141
142 if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
143 LOG_ERR("hardware only supports 8 data bits");
144 return -ENOTSUP;
145 }
146
147 if (cfg->parity != UART_CFG_PARITY_NONE) {
148 LOG_ERR("hardware only supports parity mode none");
149 return -ENOTSUP;
150 }
151
152 switch (cfg->flow_ctrl) {
153 case UART_CFG_FLOW_CTRL_NONE:
154 hwfc_en = false;
155 break;
156 case UART_CFG_FLOW_CTRL_RTS_CTS:
157 hwfc_en = true;
158 break;
159 default:
160 LOG_ERR("unsupported flow control mode %d", cfg->flow_ctrl);
161 return -ENOTSUP;
162 }
163
164 err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_CLK, &clk);
165 if (err < 0) {
166 LOG_ERR("failed to determine clock rate (err %d)", err);
167 return -EIO;
168 }
169
170 if (cfg->baudrate == 0) {
171 LOG_ERR("invalid baud rate 0");
172 return -EINVAL;
173 }
174
175 /*
176 * Calculate clock prescaler and baud prescaler. Initial prscx = 0 is
177 * clock / 2.
178 */
179 baudxx = clk / (2 * cfg->baudrate);
180 while (baudxx >= baudxx_max) {
181 if ((prscx == 2) || (prscx == 4)) {
182 baudxx >>= 3;
183 } else {
184 baudxx >>= 1;
185 }
186
187 prscx++;
188 }
189
190 if (prscx > prscx_max) {
191 LOG_ERR("unsupported baud rate %d", cfg->baudrate);
192 return -ENOTSUP;
193 }
194
195 key = k_spin_lock(&data->lock);
196
197 ctrl = neorv32_uart_read_ctrl(dev);
198 ctrl |= NEORV32_UART_CTRL_EN;
199
200 if (hwfc_en) {
201 ctrl |= NEORV32_UART_CTRL_HWFC_EN;
202 } else {
203 ctrl &= ~NEORV32_UART_CTRL_HWFC_EN;
204 }
205
206 ctrl &= ~(NEORV32_UART_CTRL_BAUD | NEORV32_UART_CTRL_PRSC);
207 ctrl |= FIELD_PREP(NEORV32_UART_CTRL_BAUD, baudxx - 1U) |
208 FIELD_PREP(NEORV32_UART_CTRL_PRSC, prscx);
209
210 neorv32_uart_write_ctrl(dev, ctrl);
211 data->uart_cfg = *cfg;
212
213 k_spin_unlock(&data->lock, key);
214
215 return 0;
216 }
217
218 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
neorv32_uart_config_get(const struct device * dev,struct uart_config * cfg)219 static int neorv32_uart_config_get(const struct device *dev, struct uart_config *cfg)
220 {
221 struct neorv32_uart_data *data = dev->data;
222
223 __ASSERT_NO_MSG(cfg != NULL);
224
225 *cfg = data->uart_cfg;
226
227 return 0;
228 }
229 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
230
231 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
neorv32_uart_fifo_fill(const struct device * dev,const uint8_t * tx_data,int size)232 static int neorv32_uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
233 {
234 int count = 0;
235
236 if (size <= 0) {
237 return 0;
238 }
239
240 __ASSERT_NO_MSG(tx_data != NULL);
241
242 while (count < size && (neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_TX_FULL) == 0U) {
243 neorv32_uart_write_data(dev, tx_data[count++]);
244 }
245
246 return count;
247 }
248
neorv32_uart_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)249 static int neorv32_uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
250 {
251 int count = 0;
252
253 if (size <= 0) {
254 return 0;
255 }
256
257 __ASSERT_NO_MSG(rx_data != NULL);
258
259 while (count < size && (neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_RX_NEMPTY) != 0U) {
260 rx_data[count++] = neorv32_uart_read_data(dev) & NEORV32_UART_DATA_RTX;
261 }
262
263 return count;
264 }
265
neorv32_uart_irq_tx_enable(const struct device * dev)266 static void neorv32_uart_irq_tx_enable(const struct device *dev)
267 {
268 struct neorv32_uart_data *data = dev->data;
269 k_spinlock_key_t key;
270 uint32_t ctrl;
271
272 key = k_spin_lock(&data->lock);
273
274 ctrl = neorv32_uart_read_ctrl(dev);
275 ctrl |= NEORV32_UART_CTRL_IRQ_TX_EMPTY;
276 neorv32_uart_write_ctrl(dev, ctrl);
277
278 k_spin_unlock(&data->lock, key);
279 }
280
neorv32_uart_irq_tx_disable(const struct device * dev)281 static void neorv32_uart_irq_tx_disable(const struct device *dev)
282 {
283 struct neorv32_uart_data *data = dev->data;
284 k_spinlock_key_t key;
285 uint32_t ctrl;
286
287 key = k_spin_lock(&data->lock);
288
289 ctrl = neorv32_uart_read_ctrl(dev);
290 ctrl &= ~NEORV32_UART_CTRL_IRQ_TX_EMPTY;
291 neorv32_uart_write_ctrl(dev, ctrl);
292
293 k_spin_unlock(&data->lock, key);
294 }
295
neorv32_uart_irq_tx_ready(const struct device * dev)296 static int neorv32_uart_irq_tx_ready(const struct device *dev)
297 {
298 struct neorv32_uart_data *data = dev->data;
299
300 if ((data->last_ctrl & NEORV32_UART_CTRL_IRQ_TX_EMPTY) == 0U) {
301 return 0;
302 }
303
304 return (data->last_ctrl & NEORV32_UART_CTRL_TX_FULL) == 0U;
305 }
306
neorv32_uart_irq_rx_enable(const struct device * dev)307 static void neorv32_uart_irq_rx_enable(const struct device *dev)
308 {
309 struct neorv32_uart_data *data = dev->data;
310 k_spinlock_key_t key;
311 uint32_t ctrl;
312
313 key = k_spin_lock(&data->lock);
314
315 ctrl = neorv32_uart_read_ctrl(dev);
316 ctrl |= NEORV32_UART_CTRL_IRQ_RX_NEMPTY;
317 neorv32_uart_write_ctrl(dev, ctrl);
318
319 k_spin_unlock(&data->lock, key);
320 }
321
neorv32_uart_irq_rx_disable(const struct device * dev)322 static void neorv32_uart_irq_rx_disable(const struct device *dev)
323 {
324 struct neorv32_uart_data *data = dev->data;
325 k_spinlock_key_t key;
326 uint32_t ctrl;
327
328 key = k_spin_lock(&data->lock);
329
330 ctrl = neorv32_uart_read_ctrl(dev);
331 ctrl &= ~NEORV32_UART_CTRL_IRQ_RX_NEMPTY;
332 neorv32_uart_write_ctrl(dev, ctrl);
333
334 k_spin_unlock(&data->lock, key);
335 }
336
neorv32_uart_irq_tx_complete(const struct device * dev)337 static int neorv32_uart_irq_tx_complete(const struct device *dev)
338 {
339 struct neorv32_uart_data *data = dev->data;
340
341 return (data->last_ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0U;
342 }
343
neorv32_uart_irq_rx_ready(const struct device * dev)344 static int neorv32_uart_irq_rx_ready(const struct device *dev)
345 {
346 struct neorv32_uart_data *data = dev->data;
347
348 if ((data->last_ctrl & NEORV32_UART_CTRL_IRQ_RX_NEMPTY) == 0U) {
349 return 0;
350 }
351
352 return (data->last_ctrl & NEORV32_UART_CTRL_RX_NEMPTY) != 0U;
353 }
354
neorv32_uart_irq_is_pending(const struct device * dev)355 static int neorv32_uart_irq_is_pending(const struct device *dev)
356 {
357 return (neorv32_uart_irq_tx_ready(dev) ||
358 neorv32_uart_irq_rx_ready(dev));
359 }
360
neorv32_uart_irq_update(const struct device * dev)361 static int neorv32_uart_irq_update(const struct device *dev)
362 {
363 struct neorv32_uart_data *data = dev->data;
364
365 /* Cache the CTRL register for use in the following functions:
366 * - neorv32_uart_irq_tx_complete()
367 * - neorv32_uart_irq_tx_ready()
368 * - neorv32_uart_irq_rx_ready()
369 */
370 data->last_ctrl = neorv32_uart_read_ctrl(dev);
371
372 return 1;
373 }
374
neorv32_uart_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * user_data)375 static void neorv32_uart_irq_callback_set(const struct device *dev,
376 uart_irq_callback_user_data_t cb, void *user_data)
377 {
378 struct neorv32_uart_data *data = dev->data;
379
380 data->callback = cb;
381 data->callback_data = user_data;
382 }
383
neorv32_uart_isr(const struct device * dev)384 static void neorv32_uart_isr(const struct device *dev)
385 {
386 struct neorv32_uart_data *data = dev->data;
387 uart_irq_callback_user_data_t callback = data->callback;
388
389 if (callback) {
390 callback(dev, data->callback_data);
391 }
392 }
393 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
394
neorv32_uart_init(const struct device * dev)395 static int neorv32_uart_init(const struct device *dev)
396 {
397 const struct neorv32_uart_config *config = dev->config;
398 struct neorv32_uart_data *data = dev->data;
399 uint32_t features;
400 int err;
401
402 if (!device_is_ready(config->syscon)) {
403 LOG_ERR("syscon device not ready");
404 return -EINVAL;
405 }
406
407 err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_SOC, &features);
408 if (err < 0) {
409 LOG_ERR("failed to determine implemented features (err %d)", err);
410 return -EIO;
411 }
412
413 if ((features & config->feature_mask) == 0) {
414 LOG_ERR("neorv32 uart instance not supported");
415 return -ENODEV;
416 }
417
418 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
419 config->irq_config_func(dev);
420 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
421
422 return neorv32_uart_configure(dev, &data->uart_cfg);
423 }
424
425 #ifdef CONFIG_PM_DEVICE
neorv32_uart_pm_action(const struct device * dev,enum pm_device_action action)426 static int neorv32_uart_pm_action(const struct device *dev,
427 enum pm_device_action action)
428 {
429 struct neorv32_uart_data *data = dev->data;
430 k_spinlock_key_t key;
431 uint32_t ctrl;
432
433 key = k_spin_lock(&data->lock);
434 ctrl = neorv32_uart_read_ctrl(dev);
435
436 switch (action) {
437 case PM_DEVICE_ACTION_SUSPEND:
438 ctrl &= ~(NEORV32_UART_CTRL_EN);
439 break;
440 case PM_DEVICE_ACTION_RESUME:
441 ctrl |= NEORV32_UART_CTRL_EN;
442 break;
443 default:
444 return -ENOTSUP;
445 }
446
447 neorv32_uart_write_ctrl(dev, ctrl);
448 k_spin_unlock(&data->lock, key);
449
450 return 0;
451 }
452 #endif /* CONFIG_PM_DEVICE */
453
454 static DEVICE_API(uart, neorv32_uart_driver_api) = {
455 .poll_in = neorv32_uart_poll_in,
456 .poll_out = neorv32_uart_poll_out,
457 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
458 .configure = neorv32_uart_configure,
459 .config_get = neorv32_uart_config_get,
460 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
461 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
462 .fifo_fill = neorv32_uart_fifo_fill,
463 .fifo_read = neorv32_uart_fifo_read,
464 .irq_tx_enable = neorv32_uart_irq_tx_enable,
465 .irq_tx_disable = neorv32_uart_irq_tx_disable,
466 .irq_tx_ready = neorv32_uart_irq_tx_ready,
467 .irq_rx_enable = neorv32_uart_irq_rx_enable,
468 .irq_rx_disable = neorv32_uart_irq_rx_disable,
469 .irq_tx_complete = neorv32_uart_irq_tx_complete,
470 .irq_rx_ready = neorv32_uart_irq_rx_ready,
471 .irq_is_pending = neorv32_uart_irq_is_pending,
472 .irq_update = neorv32_uart_irq_update,
473 .irq_callback_set = neorv32_uart_irq_callback_set,
474 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
475 };
476
477 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
478 #define NEORV32_UART_CONFIG_FUNC(node_id, n) \
479 static void neorv32_uart_config_func_##n(const struct device *dev) \
480 { \
481 IRQ_CONNECT(DT_IRQ_BY_NAME(node_id, tx, irq), \
482 DT_IRQ_BY_NAME(node_id, tx, priority), \
483 neorv32_uart_isr, \
484 DEVICE_DT_GET(node_id), 0); \
485 irq_enable(DT_IRQ_BY_NAME(node_id, tx, irq)); \
486 \
487 IRQ_CONNECT(DT_IRQ_BY_NAME(node_id, rx, irq), \
488 DT_IRQ_BY_NAME(node_id, rx, priority), \
489 neorv32_uart_isr, \
490 DEVICE_DT_GET(node_id), 0); \
491 irq_enable(DT_IRQ_BY_NAME(node_id, rx, irq)); \
492 }
493 #define NEORV32_UART_CONFIG_INIT(node_id, n) \
494 .irq_config_func = neorv32_uart_config_func_##n,
495 #else
496 #define NEORV32_UART_CONFIG_FUNC(node_id, n)
497 #define NEORV32_UART_CONFIG_INIT(node_id, n)
498 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
499
500 #define NEORV32_UART_INIT(node_id, n) \
501 NEORV32_UART_CONFIG_FUNC(node_id, n) \
502 \
503 static struct neorv32_uart_data neorv32_uart_##n##_data = { \
504 .uart_cfg = { \
505 .baudrate = DT_PROP(node_id, current_speed), \
506 .parity = DT_ENUM_IDX(node_id, parity), \
507 .stop_bits = UART_CFG_STOP_BITS_1, \
508 .data_bits = UART_CFG_DATA_BITS_8, \
509 .flow_ctrl = DT_PROP(node_id, hw_flow_control) ? \
510 UART_CFG_FLOW_CTRL_RTS_CTS : \
511 UART_CFG_FLOW_CTRL_NONE, \
512 }, \
513 }; \
514 \
515 static const struct neorv32_uart_config neorv32_uart_##n##_config = { \
516 .syscon = DEVICE_DT_GET(DT_PHANDLE(node_id, syscon)), \
517 .feature_mask = NEORV32_SYSINFO_SOC_IO_UART##n, \
518 .base = DT_REG_ADDR(node_id), \
519 NEORV32_UART_CONFIG_INIT(node_id, n) \
520 }; \
521 \
522 PM_DEVICE_DT_DEFINE(node_id, neorv32_uart_pm_action); \
523 \
524 DEVICE_DT_DEFINE(node_id, &neorv32_uart_init, \
525 PM_DEVICE_DT_GET(node_id), \
526 &neorv32_uart_##n##_data, \
527 &neorv32_uart_##n##_config, \
528 PRE_KERNEL_1, \
529 CONFIG_SERIAL_INIT_PRIORITY, \
530 &neorv32_uart_driver_api)
531
532 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(uart0), DT_DRV_COMPAT, okay)
533 NEORV32_UART_INIT(DT_NODELABEL(uart0), 0);
534 #endif
535
536 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(uart1), DT_DRV_COMPAT, okay)
537 NEORV32_UART_INIT(DT_NODELABEL(uart1), 1);
538 #endif
539
