1/* 2 * Copyright (c) 2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8.1-m.dtsi> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 10#include <zephyr/dt-bindings/clock/stm32n6_clock.h> 11#include <zephyr/dt-bindings/dma/stm32_dma.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/reset/stm32n6_reset.h> 14#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h> 15#include <zephyr/dt-bindings/gpio/gpio.h> 16#include <freq.h> 17 18/ { 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-m55"; 26 reg = <0>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 30 mpu: mpu@e000ed90 { 31 compatible = "arm,armv8.1m-mpu"; 32 reg = <0xe000ed90 0x40>; 33 }; 34 }; 35 }; 36 37 axisram1: memory@34000000 { 38 compatible = "mmio-sram"; 39 }; 40 41 axisram2: memory@34180400 { 42 compatible = "mmio-sram"; 43 }; 44 45 clocks { 46 clk_hse: clk-hse { 47 #clock-cells = <0>; 48 compatible = "st,stm32n6-hse-clock"; 49 status = "disabled"; 50 }; 51 52 clk_hsi: clk-hsi { 53 #clock-cells = <0>; 54 compatible = "st,stm32h7-hsi-clock"; 55 clock-frequency = <DT_FREQ_M(64)>; 56 status = "disabled"; 57 }; 58 59 clk_lse: clk-lse { 60 #clock-cells = <0>; 61 compatible = "st,stm32-lse-clock"; 62 clock-frequency = <32768>; 63 driving-capability = <2>; 64 status = "disabled"; 65 }; 66 67 clk_lsi: clk-lsi { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <DT_FREQ_K(32)>; 71 status = "disabled"; 72 }; 73 74 pll1: pll: pll { 75 #clock-cells = <0>; 76 compatible = "st,stm32n6-pll-clock"; 77 status = "disabled"; 78 }; 79 80 pll2: pll2 { 81 #clock-cells = <0>; 82 compatible = "st,stm32n6-pll-clock"; 83 status = "disabled"; 84 }; 85 86 pll3: pll3 { 87 #clock-cells = <0>; 88 compatible = "st,stm32n6-pll-clock"; 89 status = "disabled"; 90 }; 91 92 pll4: pll4 { 93 #clock-cells = <0>; 94 compatible = "st,stm32n6-pll-clock"; 95 status = "disabled"; 96 }; 97 98 cpusw: cpusw { 99 #clock-cells = <0>; 100 compatible = "st,stm32n6-cpu-clock-mux", "st,stm32-clock-mux"; 101 status = "disabled"; 102 }; 103 104 perck: perck { 105 #clock-cells = <0>; 106 compatible = "st,stm32-clock-mux"; 107 status = "disabled"; 108 }; 109 110 ic1: ic1 { 111 #clock-cells = <0>; 112 compatible = "st,stm32n6-ic-clock-mux"; 113 status = "disabled"; 114 }; 115 116 ic2: ic2 { 117 #clock-cells = <0>; 118 compatible = "st,stm32n6-ic-clock-mux"; 119 status = "disabled"; 120 }; 121 122 ic3: ic3 { 123 #clock-cells = <0>; 124 compatible = "st,stm32n6-ic-clock-mux"; 125 status = "disabled"; 126 }; 127 128 ic4: ic4 { 129 #clock-cells = <0>; 130 compatible = "st,stm32n6-ic-clock-mux"; 131 status = "disabled"; 132 }; 133 134 ic5: ic5 { 135 #clock-cells = <0>; 136 compatible = "st,stm32n6-ic-clock-mux"; 137 status = "disabled"; 138 }; 139 140 ic6: ic6 { 141 #clock-cells = <0>; 142 compatible = "st,stm32n6-ic-clock-mux"; 143 status = "disabled"; 144 }; 145 146 ic7: ic7 { 147 #clock-cells = <0>; 148 compatible = "st,stm32n6-ic-clock-mux"; 149 status = "disabled"; 150 }; 151 152 ic8: ic8 { 153 #clock-cells = <0>; 154 compatible = "st,stm32n6-ic-clock-mux"; 155 status = "disabled"; 156 }; 157 158 ic9: ic9 { 159 #clock-cells = <0>; 160 compatible = "st,stm32n6-ic-clock-mux"; 161 status = "disabled"; 162 }; 163 164 ic10: ic10 { 165 #clock-cells = <0>; 166 compatible = "st,stm32n6-ic-clock-mux"; 167 status = "disabled"; 168 }; 169 170 ic11: ic11 { 171 #clock-cells = <0>; 172 compatible = "st,stm32n6-ic-clock-mux"; 173 status = "disabled"; 174 }; 175 176 ic12: ic12 { 177 #clock-cells = <0>; 178 compatible = "st,stm32n6-ic-clock-mux"; 179 status = "disabled"; 180 }; 181 182 ic13: ic13 { 183 #clock-cells = <0>; 184 compatible = "st,stm32n6-ic-clock-mux"; 185 status = "disabled"; 186 }; 187 188 ic14: ic14 { 189 #clock-cells = <0>; 190 compatible = "st,stm32n6-ic-clock-mux"; 191 status = "disabled"; 192 }; 193 194 ic15: ic15 { 195 #clock-cells = <0>; 196 compatible = "st,stm32n6-ic-clock-mux"; 197 status = "disabled"; 198 }; 199 200 ic16: ic16 { 201 #clock-cells = <0>; 202 compatible = "st,stm32n6-ic-clock-mux"; 203 status = "disabled"; 204 }; 205 206 ic17: ic17 { 207 #clock-cells = <0>; 208 compatible = "st,stm32n6-ic-clock-mux"; 209 status = "disabled"; 210 }; 211 212 ic18: ic18 { 213 #clock-cells = <0>; 214 compatible = "st,stm32n6-ic-clock-mux"; 215 status = "disabled"; 216 }; 217 218 ic19: ic19 { 219 #clock-cells = <0>; 220 compatible = "st,stm32n6-ic-clock-mux"; 221 status = "disabled"; 222 }; 223 224 ic20: ic20 { 225 #clock-cells = <0>; 226 compatible = "st,stm32n6-ic-clock-mux"; 227 status = "disabled"; 228 }; 229 }; 230 231 soc { 232 rcc: rcc@56028000 { 233 compatible = "st,stm32n6-rcc"; 234 clocks-controller; 235 #clock-cells = <2>; 236 reg = <0x56028000 0x2000>; 237 238 rctl: reset-controller { 239 compatible = "st,stm32-rcc-rctl"; 240 #reset-cells = <1>; 241 }; 242 }; 243 244 exti: interrupt-controller@56025000 { 245 compatible = "st,stm32g0-exti", "st,stm32-exti"; 246 interrupt-controller; 247 #interrupt-cells = <1>; 248 #address-cells = <1>; 249 reg = <0x56025000 0x400>; 250 num-lines = <16>; 251 interrupts = <20 0>, <21 0>, <22 0>, <23 0>, 252 <24 0>, <25 0>, <26 0>, <27 0>, 253 <28 0>, <29 0>, <30 0>, <31 0>, 254 <32 0>, <33 0>, <34 0>, <35 0>; 255 interrupt-names = "line0", "line1", "line2", "line3", 256 "line4", "line5", "line6", "line7", 257 "line8", "line9", "line10", "line11", 258 "line12", "line13", "line14", "line15"; 259 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 260 <4 1>, <5 1>, <6 1>, <7 1>, 261 <8 1>, <9 1>, <10 1>, <11 1>, 262 <12 1>, <13 1>, <14 1>, <15 1>; 263 }; 264 265 pinctrl: pin-controller@56020000 { 266 compatible = "st,stm32-pinctrl"; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 reg = <0x56020000 0x2000>; 270 271 gpioa: gpio@56020000 { 272 compatible = "st,stm32-gpio"; 273 gpio-controller; 274 #gpio-cells = <2>; 275 reg = <0x56020000 0x400>; 276 clocks = <&rcc STM32_CLOCK(AHB4, 0)>; 277 }; 278 279 gpiob: gpio@56020400 { 280 compatible = "st,stm32-gpio"; 281 gpio-controller; 282 #gpio-cells = <2>; 283 reg = <0x56020400 0x400>; 284 clocks = <&rcc STM32_CLOCK(AHB4, 1)>; 285 }; 286 287 gpioc: gpio@56020800 { 288 compatible = "st,stm32-gpio"; 289 gpio-controller; 290 #gpio-cells = <2>; 291 reg = <0x56020800 0x400>; 292 clocks = <&rcc STM32_CLOCK(AHB4, 2)>; 293 }; 294 295 gpiod: gpio@56020c00 { 296 compatible = "st,stm32-gpio"; 297 gpio-controller; 298 #gpio-cells = <2>; 299 reg = <0x56020c00 0x400>; 300 clocks = <&rcc STM32_CLOCK(AHB4, 3)>; 301 }; 302 303 gpioe: gpio@56021000 { 304 compatible = "st,stm32-gpio"; 305 gpio-controller; 306 #gpio-cells = <2>; 307 reg = <0x56021000 0x400>; 308 clocks = <&rcc STM32_CLOCK(AHB4, 4)>; 309 }; 310 311 gpiof: gpio@56021400 { 312 compatible = "st,stm32-gpio"; 313 gpio-controller; 314 #gpio-cells = <2>; 315 reg = <0x56021400 0x400>; 316 clocks = <&rcc STM32_CLOCK(AHB4, 5)>; 317 }; 318 319 gpiog: gpio@56021800 { 320 compatible = "st,stm32-gpio"; 321 gpio-controller; 322 #gpio-cells = <2>; 323 reg = <0x56021800 0x400>; 324 clocks = <&rcc STM32_CLOCK(AHB4, 6)>; 325 }; 326 327 gpioh: gpio@56021c00 { 328 compatible = "st,stm32-gpio"; 329 gpio-controller; 330 #gpio-cells = <2>; 331 reg = <0x56021c00 0x400>; 332 clocks = <&rcc STM32_CLOCK(AHB4, 7)>; 333 }; 334 335 gpion: gpio@56023400 { 336 compatible = "st,stm32-gpio"; 337 gpio-controller; 338 #gpio-cells = <2>; 339 reg = <0x56023400 0x400>; 340 clocks = <&rcc STM32_CLOCK(AHB4, 13)>; 341 }; 342 343 gpioo: gpio@56023800 { 344 compatible = "st,stm32-gpio"; 345 gpio-controller; 346 #gpio-cells = <2>; 347 reg = <0x56023800 0x400>; 348 clocks = <&rcc STM32_CLOCK(AHB4, 14)>; 349 }; 350 351 gpiop: gpio@56023c00 { 352 compatible = "st,stm32-gpio"; 353 gpio-controller; 354 #gpio-cells = <2>; 355 reg = <0x56023C00 0x400>; 356 clocks = <&rcc STM32_CLOCK(AHB4, 15)>; 357 }; 358 359 gpioq: gpio@56024000 { 360 compatible = "st,stm32-gpio"; 361 gpio-controller; 362 #gpio-cells = <2>; 363 reg = <0x56024000 0x400>; 364 clocks = <&rcc STM32_CLOCK(AHB4, 16)>; 365 }; 366 }; 367 368 adc1: adc@50022000 { 369 compatible = "st,stm32n6-adc", "st,stm32-adc"; 370 reg = <0x50022000 0x400>; 371 clocks = <&rcc STM32_CLOCK(AHB1, 5)>; 372 interrupts = <46 0>; 373 status = "disabled"; 374 #io-channel-cells = <1>; 375 resolutions = <STM32_ADC_RES(12, 0x00) 376 STM32_ADC_RES(10, 0x01) 377 STM32_ADC_RES(8, 0x02) 378 STM32_ADC_RES(6, 0x03)>; 379 sampling-times = <2 3 7 12 14 47 247 1500>; 380 st,adc-sequencer = "FULLY_CONFIGURABLE"; 381 st,adc-oversampler = "OVERSAMPLER_EXTENDED"; 382 }; 383 384 adc2: adc@50022100 { 385 compatible = "st,stm32n6-adc", "st,stm32-adc"; 386 reg = <0x50022100 0x300>; 387 clocks = <&rcc STM32_CLOCK(AHB1, 5)>; 388 interrupts = <46 0>; 389 status = "disabled"; 390 #io-channel-cells = <1>; 391 resolutions = <STM32_ADC_RES(12, 0x00) 392 STM32_ADC_RES(10, 0x01) 393 STM32_ADC_RES(8, 0x02) 394 STM32_ADC_RES(6, 0x03)>; 395 sampling-times = <2 3 7 12 14 47 247 1500>; 396 st,adc-sequencer = "FULLY_CONFIGURABLE"; 397 st,adc-oversampler = "OVERSAMPLER_EXTENDED"; 398 }; 399 400 fdcan1: can@5000a000 { 401 compatible = "st,stm32h7-fdcan"; 402 reg = <0x5000A000 0x400>, <0x5000C000 0xd54>; 403 reg-names = "m_can", "message_ram"; 404 clocks = <&rcc STM32_CLOCK(APB1_2, 8)>; 405 interrupts = <180 0>, <181 0>, <186 0>; 406 interrupt-names = "int0", "int1", "calib"; 407 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; 408 status = "disabled"; 409 }; 410 411 fdcan2: can@5000a400 { 412 compatible = "st,stm32h7-fdcan"; 413 reg = <0x5000A400 0x400>, <0x5000C000 0x1aa8>; 414 reg-names = "m_can", "message_ram"; 415 clocks = <&rcc STM32_CLOCK(APB1_2, 8)>; 416 interrupts = <182 0>, <183 0>; 417 interrupt-names = "int0", "int1"; 418 bosch,mram-cfg = <0xd54 28 8 3 3 0 3 3>; 419 status = "disabled"; 420 }; 421 422 fdcan3: can@5000e800 { 423 compatible = "st,stm32h7-fdcan"; 424 reg = <0x5000E800 0x400>, <0x5000C000 0x2800>; 425 reg-names = "m_can", "message_ram"; 426 clocks = <&rcc STM32_CLOCK(APB1_2, 8)>; 427 interrupts = <184 0>, <185 0>; 428 interrupt-names = "int0", "int1"; 429 bosch,mram-cfg = <0x1aa8 28 8 3 3 0 3 3>; 430 status = "disabled"; 431 }; 432 433 usart1: serial@52001000 { 434 compatible = "st,stm32-usart", "st,stm32-uart"; 435 reg = <0x52001000 0x400>; 436 clocks = <&rcc STM32_CLOCK(APB2, 4)>; 437 resets = <&rctl STM32_RESET(APB2, 4)>; 438 interrupts = <159 0>; 439 status = "disabled"; 440 }; 441 442 usart2: serial@50004400 { 443 compatible = "st,stm32-usart", "st,stm32-uart"; 444 reg = <0x50004400 0x400>; 445 clocks = <&rcc STM32_CLOCK(APB1, 17)>; 446 resets = <&rctl STM32_RESET(APB1L, 17)>; 447 interrupts = <160 0>; 448 status = "disabled"; 449 }; 450 451 usart3: serial@50004800 { 452 compatible = "st,stm32-usart", "st,stm32-uart"; 453 reg = <0x50004800 0x400>; 454 clocks = <&rcc STM32_CLOCK(APB1, 18)>; 455 resets = <&rctl STM32_RESET(APB1L, 18)>; 456 interrupts = <161 0>; 457 status = "disabled"; 458 }; 459 460 uart4: serial@50004c00 { 461 compatible = "st,stm32-usart", "st,stm32-uart"; 462 reg = <0x50004C00 0x400>; 463 clocks = <&rcc STM32_CLOCK(APB1, 19)>; 464 resets = <&rctl STM32_RESET(APB1L, 19)>; 465 interrupts = <162 0>; 466 status = "disabled"; 467 }; 468 469 uart5: serial@50005000 { 470 compatible = "st,stm32-usart", "st,stm32-uart"; 471 reg = <0x50005000 0x400>; 472 clocks = <&rcc STM32_CLOCK(APB1, 20)>; 473 resets = <&rctl STM32_RESET(APB1L, 20)>; 474 interrupts = <163 0>; 475 status = "disabled"; 476 }; 477 478 usart6: serial@52001400 { 479 compatible = "st,stm32-usart", "st,stm32-uart"; 480 reg = <0x52001400 0x400>; 481 clocks = <&rcc STM32_CLOCK(APB2, 5)>; 482 resets = <&rctl STM32_RESET(APB2, 5)>; 483 interrupts = <164 0>; 484 status = "disabled"; 485 }; 486 487 uart7: serial@50007800 { 488 compatible = "st,stm32-usart", "st,stm32-uart"; 489 reg = <0x50007800 0x400>; 490 clocks = <&rcc STM32_CLOCK(APB1, 30)>; 491 resets = <&rctl STM32_RESET(APB1L, 30)>; 492 interrupts = <165 0>; 493 status = "disabled"; 494 }; 495 496 uart8: serial@50007c00 { 497 compatible = "st,stm32-usart", "st,stm32-uart"; 498 reg = <0x50007C00 0x400>; 499 clocks = <&rcc STM32_CLOCK(APB1, 31)>; 500 resets = <&rctl STM32_RESET(APB1L, 31)>; 501 interrupts = <166 0>; 502 status = "disabled"; 503 }; 504 505 uart9: serial@52001800 { 506 compatible = "st,stm32-usart", "st,stm32-uart"; 507 reg = <0x52001800 0x400>; 508 clocks = <&rcc STM32_CLOCK(APB2, 6)>; 509 resets = <&rctl STM32_RESET(APB2, 6)>; 510 interrupts = <167 0>; 511 status = "disabled"; 512 }; 513 514 usart10: serial@52001c00 { 515 compatible = "st,stm32-usart", "st,stm32-uart"; 516 reg = <0x52001C00 0x400>; 517 clocks = <&rcc STM32_CLOCK(APB2, 7)>; 518 resets = <&rctl STM32_RESET(APB2, 7)>; 519 interrupts = <168 0>; 520 status = "disabled"; 521 }; 522 523 i2c1: i2c@50005400 { 524 compatible = "st,stm32-i2c-v2"; 525 clock-frequency = <I2C_BITRATE_STANDARD>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 reg = <0x50005400 0x400>; 529 clocks = <&rcc STM32_CLOCK(APB1, 21)>; 530 interrupts = <100 0>, <101 0>; 531 interrupt-names = "event", "error"; 532 status = "disabled"; 533 }; 534 535 i2c2: i2c@50005800 { 536 compatible = "st,stm32-i2c-v2"; 537 clock-frequency = <I2C_BITRATE_STANDARD>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 reg = <0x50005800 0x400>; 541 clocks = <&rcc STM32_CLOCK(APB1, 22)>; 542 interrupts = <102 0>, <103 0>; 543 interrupt-names = "event", "error"; 544 status = "disabled"; 545 }; 546 547 i2c3: i2c@50005c00 { 548 compatible = "st,stm32-i2c-v2"; 549 clock-frequency = <I2C_BITRATE_STANDARD>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 reg = <0x50005C00 0x400>; 553 clocks = <&rcc STM32_CLOCK(APB1, 23)>; 554 interrupts = <104 0>, <105 0>; 555 interrupt-names = "event", "error"; 556 status = "disabled"; 557 }; 558 559 i2c4: i2c@56001c00 { 560 compatible = "st,stm32-i2c-v2"; 561 clock-frequency = <I2C_BITRATE_STANDARD>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 reg = <0x56001C00 0x400>; 565 clocks = <&rcc STM32_CLOCK(APB4, 7)>; 566 interrupts = <106 0>, <107 0>; 567 interrupt-names = "event", "error"; 568 status = "disabled"; 569 }; 570 571 spi1: spi@52003000 { 572 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 reg = <0x52003000 0x400>; 576 interrupts = <153 0>; 577 clocks = <&rcc STM32_CLOCK(APB2, 12)>; 578 status = "disabled"; 579 }; 580 581 spi2: spi@50003800 { 582 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 reg = <0x50003800 0x400>; 586 interrupts = <154 0>; 587 clocks = <&rcc STM32_CLOCK(APB1, 14)>; 588 status = "disabled"; 589 }; 590 591 spi3: spi@50003c00 { 592 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <0x50003C00 0x400>; 596 interrupts = <155 0>; 597 clocks = <&rcc STM32_CLOCK(APB1, 15)>; 598 status = "disabled"; 599 }; 600 601 spi4: spi@52003400 { 602 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 reg = <0x52003400 0x400>; 606 interrupts = <156 0>; 607 clocks = <&rcc STM32_CLOCK(APB2, 13)>; 608 status = "disabled"; 609 }; 610 611 spi5: spi@52005000 { 612 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 reg = <0x52005000 0x400>; 616 interrupts = <157 0>; 617 clocks = <&rcc STM32_CLOCK(APB2, 20)>; 618 status = "disabled"; 619 }; 620 621 spi6: spi@56001400 { 622 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 reg = <0x56001400 0x400>; 626 interrupts = <158 0>; 627 clocks = <&rcc STM32_CLOCK(APB4, 5)>; 628 status = "disabled"; 629 }; 630 631 gpdma1: dma@50021000 { 632 compatible = "st,stm32u5-dma"; 633 #dma-cells = <3>; 634 reg = <0x50021000 0x1000>; 635 clocks = <&rcc STM32_CLOCK(AHB1, 4)>; 636 interrupts = <84 0 85 0 86 0 87 0 88 0 89 0 90 0 91 0 637 92 0 93 0 94 0 95 0 96 0 97 0 98 0 99 0>; 638 dma-channels = <16>; 639 dma-requests = <144>; 640 dma-offset = <0>; 641 status = "disabled"; 642 }; 643 644 mac: ethernet@58036000 { 645 compatible = "st,stm32n6-ethernet", "st,stm32h7-ethernet", 646 "st,stm32-ethernet"; 647 reg = <0x58036000 0x8000>; 648 interrupts = <179 0>; 649 clock-names = "stmmaceth", "mac-clk-tx", 650 "mac-clk-rx"; 651 clocks = <&rcc STM32_CLOCK(AHB5, 22)>, 652 <&rcc STM32_CLOCK(AHB5, 23)>, 653 <&rcc STM32_CLOCK(AHB5, 24)>; 654 status = "disabled"; 655 656 mdio: mdio { 657 compatible = "st,stm32-mdio"; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 }; 663 }; 664}; 665 666&nvic { 667 arm,num-irq-priority-bits = <4>; 668}; 669
