1 /*
2  * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef __NI_TOWER_DISCOVERY_REG_H__
9 #define __NI_TOWER_DISCOVERY_REG_H__
10 
11 #include "tfm_hal_device_header.h"
12 
13 #include <stdint.h>
14 
15 /**
16  * \brief Offset address to be tested for every config read to determine
17  * if a configuration is mapped to FMU register
18  */
19 #define FMU_CHECK_OFFSET_ADDRESS    (0xFFE0)
20 
21 /**
22  * \brief Interconnect Part Number for NI-Tower
23  */
24 #define NI_TOWER_PID0_PART_NUM      (0x3F)
25 #define NI_TOWER_PID1_PART_NUM      (0x4)
26 
27 /**
28  * \brief NI-Tower Domain top registers. These are common for all domains
29  */
30 struct ni_tower_domain_cfg_hdr {
31     __IM uint32_t node_type;
32     __IM uint32_t child_node_info;
33     __IM uint32_t x_pointers[];
34 };
35 
36 /*  Field definitions for node_type register */
37 #define NI_TOWER_DOMAIN_NODE_TYPE_POS     (0U)
38 #define NI_TOWER_DOMAIN_NODE_TYPE_MSK     (0xFFFFUL << NI_TOWER_DOMAIN_NODE_TYPE_POS)
39 #define NI_TOWER_DOMAIN_NODE_TYPE         NI_TOWER_DOMAIN_NODE_TYPE_MSK
40 #define NI_TOWER_DOMAIN_NODE_ID_POS       (16U)
41 #define NI_TOWER_DOMAIN_NODE_ID_MSK       (0xFFFFUL << NI_TOWER_DOMAIN_NODE_ID_POS)
42 #define NI_TOWER_DOMAIN_NODE_ID           NI_TOWER_DOMAIN_NODE_ID_MSK
43 
44 /**
45  * \brief NI-Tower Component top registers. These are common for all components
46  */
47 struct ni_tower_component_cfg_hdr {
48     __IM  uint32_t node_type;
49     const uint32_t reserved_0[4];
50     __IM  uint32_t interface_id_0_3;
51     const uint32_t reserved_1[58];
52     __IM  uint32_t num_subfeatures;
53     const uint32_t reserved_2;
54     struct {
55         __IM uint32_t type;
56         __IM uint32_t pointer;
57     } subfeature[];
58 };
59 
60 /**
61  * \brief NI-Tower Global register
62  */
63 struct ni_tower_global_reg_map {
64     __IM  uint32_t node_type;
65     __IM  uint32_t child_node_info;
66     __IM  uint32_t vd_pointers;
67     const uint32_t reserved[1009];
68     __IM  uint32_t peripheral_id4;
69     __IM  uint32_t peripheral_id5;
70     __IM  uint32_t peripheral_id6;
71     __IM  uint32_t peripheral_id7;
72     __IM  uint32_t peripheral_id0;
73     __IM  uint32_t peripheral_id1;
74     __IM  uint32_t peripheral_id2;
75     __IM  uint32_t peripheral_id3;
76     __IM  uint32_t component_id0;
77     __IM  uint32_t component_id1;
78     __IM  uint32_t component_id2;
79     __IM  uint32_t component_id3;
80 };
81 
82 /*  Field definitions for peripheral_id0 register */
83 #define NI_TOWER_GLOBAL_PERIPHERAL_ID0_POS         (0U)
84 #define NI_TOWER_GLOBAL_PERIPHERAL_ID0_MSK         (0xFFUL << NI_TOWER_GLOBAL_PERIPHERAL_ID0_POS)
85 #define NI_TOWER_GLOBAL_PERIPHERAL_ID0             NI_TOWER_GLOBAL_PERIPHERAL_ID0_MSK
86 
87 /*  Field definitions for peripheral_id1 register */
88 #define NI_TOWER_GLOBAL_PERIPHERAL_ID1_POS         (0U)
89 #define NI_TOWER_GLOBAL_PERIPHERAL_ID1_MSK         (0xFUL << NI_TOWER_GLOBAL_PERIPHERAL_ID1_POS)
90 #define NI_TOWER_GLOBAL_PERIPHERAL_ID1             NI_TOWER_GLOBAL_PERIPHERAL_ID1_MSK
91 
92 #endif /* __NI_TOWER_DISCOVERY_REG_H__ */
93