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/hal_infineon-latest/mtb-pdl-cat1/device-info/personalities_9.0/platform/
Dfll_solver-2.0.tcl276 proc verify_desired_frequency {sourceFreq targetFreq outputDiv} {
/hal_infineon-latest/mtb-pdl-cat1/device-info/personalities/platform/
Dfll_solver-2.0.tcl276 proc verify_desired_frequency {sourceFreq targetFreq outputDiv} {
/hal_infineon-latest/mtb-pdl-cat1/device-info/personalities_8.0/platform/
Dfll_solver-2.0.tcl276 proc verify_desired_frequency {sourceFreq targetFreq outputDiv} {
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_clock.c1602 uint32_t *referenceDiv, uint32_t *outputDiv) in _cyhal_clock_extract_pll_params()
1656 uint32_t outputDiv = 0; in _cyhal_clock_set_enabled_pll() local
1735 uint32_t outputDiv = 0; in _cyhal_clock_set_frequency_pll() local
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2516 uint8_t outputDiv; /**< CONFIG register, OUTPUT_DIV bits */ member
2638 uint8_t outputDiv; /**< CLK_PLL_CONFIG register, OUTPUT_DIV bits */ member