1 /*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #include <soc.h>
7 #include <zephyr/logging/log.h>
8 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
9 #include <zephyr/drivers/pinctrl.h>
10 #include <zephyr/drivers/can.h>
11 #include <zephyr/drivers/can/transceiver.h>
12 #include "r_can_api.h"
13 #include "r_canfd.h"
14
15 LOG_MODULE_REGISTER(can_renesas_ra, CONFIG_CAN_LOG_LEVEL);
16
17 #define DT_DRV_COMPAT renesas_ra_canfd
18
19 #define CAN_RENESAS_RA_TIMING_MAX \
20 { \
21 .sjw = 128, \
22 .prop_seg = 1, \
23 .phase_seg1 = 255, \
24 .phase_seg2 = 128, \
25 .prescaler = 1024, \
26 }
27
28 #define CAN_RENESAS_RA_TIMING_MIN \
29 { \
30 .sjw = 1, \
31 .prop_seg = 1, \
32 .phase_seg1 = 2, \
33 .phase_seg2 = 2, \
34 .prescaler = 1, \
35 }
36
37 #ifdef CONFIG_CAN_FD_MODE
38 #define CAN_RENESAS_RA_TIMING_DATA_MAX \
39 { \
40 .sjw = 16, \
41 .prop_seg = 1, \
42 .phase_seg1 = 31, \
43 .phase_seg2 = 16, \
44 .prescaler = 128, \
45 }
46 #define CAN_RENESAS_RA_TIMING_DATA_MIN \
47 { \
48 .sjw = 1, \
49 .prop_seg = 1, \
50 .phase_seg1 = 2, \
51 .phase_seg2 = 2, \
52 .prescaler = 1, \
53 }
54 #endif
55
56 /* This frame ID will be reserved. Any filter using this ID may cause undefined behavior. */
57 #define CAN_RENESAS_RA_RESERVED_ID (CAN_EXT_ID_MASK)
58
59 /*
60 * Common FIFO configuration: refer to '34.2.28 CFDCFCC : Common FIFO Configuration/Control
61 * Register' - RA8M1 MCU group HWM
62 */
63 #define CANFD_CFG_COMMONFIFO0 (0U << R_CANFD_CFDCFCC_CFE_Pos) /* Common FIFO Disable */
64
65 #define CANFD_CFG_COMMONFIFO {CANFD_CFG_COMMONFIFO0}
66
67 /*
68 * RX FIFO configuration: refer to '34.2.25 CFDRFCCa : RX FIFO Configuration/Control Registers' -
69 * RA8M1 MCU group HWM
70 */
71 #define CANFD_CFG_RX_FIFO0 \
72 ((1U << R_CANFD_CFDRFCC_RFE_Pos) | /* RX FIFO Enable */ \
73 (1U << R_CANFD_CFDRFCC_RFIE_Pos) | /* RX FIFO Interrupt Enable */ \
74 (7U << R_CANFD_CFDRFCC_RFPLS_Pos) | /* RX FIFO Payload Data Size: 64 */ \
75 (3U << R_CANFD_CFDRFCC_RFDC_Pos) | /* RX FIFO Depth: 16 messages */ \
76 (1U << R_CANFD_CFDRFCC_RFIM_Pos)) /* Interrupt generated at every received message \
77 * storage \
78 */
79
80 #define CANFD_CFG_RX_FIFO1 (0U << R_CANFD_CFDRFCC_RFE_Pos) /* RX FIFO Disable */
81
82 #define CANFD_CFG_RXFIFO {CANFD_CFG_RX_FIFO0, CANFD_CFG_RX_FIFO1}
83
84 /*
85 * Global Configuration: refer to '34.2.11 CFDGCFG : Global Configuration Register' - RA8M1 MCU
86 * group HWM
87 */
88 #define CANFD_CFG_GLOBAL \
89 ((0U << R_CANFD_CFDGCFG_TPRI_Pos) | /* Transmission Priority: ID priority */ \
90 (0U << R_CANFD_CFDGCFG_DCE_Pos) | /* DLC check disabled */ \
91 (1U << R_CANFD_CFDGCFG_DCS_Pos)) /* DLL Clock Select: CANFDCLK */
92
93 /*
94 * TX Message Buffer Interrupt Enable Configuration: refer to '34.2.43 CFDTMIEC : TX Message Buffer
95 * Interrupt Enable Configuration Register' - RA8M1 MCU group HWM
96 */
97 #define CANFD_CFG_TXMB_TXI_ENABLE (BIT(0)) /* Enable TXMB0 interrupt */
98
99 /*
100 * Number and size of RX Message Buffers: refer to '34.2.23 CFDRMNB : RX Message Buffer Number
101 * Register' - RA8M1 MCU group HWM
102 */
103 #define CANFD_CFG_RXMB (0U << R_CANFD_CFDRMNB_NRXMB_Pos) /* Number of RX Message Buffers: 0 */
104
105 /*
106 * Channel Error IRQ configurations: refer to '34.2.3 CFDC0CTR : Control Register' - RA8M1 MCU group
107 * HWM
108 */
109 #define CANFD_CFG_ERR_IRQ \
110 (BIT(R_CANFD_CFDC_CTR_EWIE_Pos) | /* Error Warning Interrupt Enable */ \
111 BIT(R_CANFD_CFDC_CTR_EPIE_Pos) | /* Error Passive Interrupt Enable */ \
112 BIT(R_CANFD_CFDC_CTR_BOEIE_Pos) | /* Bus-Off Entry Interrupt Enable */ \
113 BIT(R_CANFD_CFDC_CTR_BORIE_Pos) | /* Bus-Off Recovery Interrupt Enable */ \
114 BIT(R_CANFD_CFDC_CTR_OLIE_Pos)) /* Overload Interrupt Enable */
115
116 /*
117 * Global Error IRQ configurations: refer to '34.2.12 CFDGCTR : Global Control Register' - RA8M1 MCU
118 * group HWM
119 */
120 #define CANFD_CFG_GLERR_IRQ \
121 ((3UL << R_CANFD_CFDGCTR_GMDC_Pos) | /* Global Mode Control: Keep current value */ \
122 (0UL << R_CANFD_CFDGCTR_DEIE_Pos) | /* DLC check interrupt disabled */ \
123 (0UL << R_CANFD_CFDGCTR_MEIE_Pos) | /* Message lost error interrupt disabled */ \
124 (0UL << R_CANFD_CFDGCTR_THLEIE_Pos) | /* TX history list entry lost interrupt disabled */ \
125 (0UL << R_CANFD_CFDGCTR_CMPOFIE_Pos)) /* CANFD message payload overflow flag interrupt \
126 * disabled \
127 */
128
129 /* Keycode to enable/disable accessing to AFL entry */
130 #define CFDGAFLIGNCTR_KEY_CODE (0xC4UL)
131
132 /* Default Dataphase bitrate configuration in case classic mode is enabled */
133 static const can_bit_timing_cfg_t classic_can_data_timing_default = {
134 .baud_rate_prescaler = 1,
135 .time_segment_1 = 3,
136 .time_segment_2 = 2,
137 .synchronization_jump_width = 1,
138 };
139
140 struct can_renesas_ra_global_cfg {
141 const struct device *op_clk;
142 const struct device *ram_clk;
143 const struct clock_control_ra_subsys_cfg op_subsys;
144 const struct clock_control_ra_subsys_cfg ram_subsys;
145 };
146
147 struct can_renesas_ra_filter {
148 bool set;
149 struct can_filter filter;
150 can_rx_callback_t rx_cb;
151 void *rx_usr_data;
152 };
153
154 struct can_renesas_ra_cfg {
155 struct can_driver_config common;
156 const struct pinctrl_dev_config *pcfg;
157 const struct device *global_dev;
158 const struct device *dll_clk;
159 const struct clock_control_ra_subsys_cfg dll_subsys;
160 const uint32_t rx_filter_num;
161 };
162
163 struct can_renesas_ra_data {
164 struct can_driver_data common;
165 struct k_mutex inst_mutex;
166 const struct device *dev;
167 can_instance_t fsp_can;
168 can_tx_callback_t tx_cb;
169 struct k_sem tx_sem;
170 void *tx_usr_data;
171 struct can_renesas_ra_filter *rx_filter;
172 can_bit_timing_cfg_t data_timing;
173 };
174
175 extern void canfd_error_isr(void);
176 extern void canfd_rx_fifo_isr(void);
177 extern void canfd_common_fifo_rx_isr(void);
178 extern void canfd_channel_tx_isr(void);
179
180 static const can_api_t *can_api = &g_canfd_on_canfd;
181
set_hw_timing_configuration(const struct device * dev,can_bit_timing_cfg_t * f_timing,const struct can_timing * z_timing)182 static inline int set_hw_timing_configuration(const struct device *dev,
183 can_bit_timing_cfg_t *f_timing,
184 const struct can_timing *z_timing)
185 {
186 struct can_renesas_ra_data *data = dev->data;
187
188 if (f_timing == NULL || z_timing == NULL) {
189 return -EINVAL;
190 }
191
192 k_mutex_lock(&data->inst_mutex, K_FOREVER);
193
194 *f_timing = (can_bit_timing_cfg_t){
195 .baud_rate_prescaler = z_timing->prescaler,
196 .time_segment_1 = z_timing->prop_seg + z_timing->phase_seg1,
197 .time_segment_2 = z_timing->phase_seg2,
198 .synchronization_jump_width = z_timing->sjw,
199 };
200
201 k_mutex_unlock(&data->inst_mutex);
202
203 return 0;
204 }
205
get_free_filter_id(const struct device * dev)206 static inline int get_free_filter_id(const struct device *dev)
207 {
208 struct can_renesas_ra_data *data = dev->data;
209 const struct can_renesas_ra_cfg *cfg = dev->config;
210
211 for (uint32_t filter_id = 0; filter_id < cfg->rx_filter_num; filter_id++) {
212 if (!data->rx_filter[filter_id].set) {
213 return filter_id;
214 }
215 }
216
217 return -ENOSPC;
218 }
219
set_afl_rule(const struct device * dev,const struct can_filter * filter,uint32_t afl_offset)220 static void set_afl_rule(const struct device *dev, const struct can_filter *filter,
221 uint32_t afl_offset)
222 {
223 struct can_renesas_ra_data *data = dev->data;
224 canfd_extended_cfg_t const *p_extend = data->fsp_can.p_cfg->p_extend;
225 canfd_afl_entry_t *afl = (canfd_afl_entry_t *)&p_extend->p_afl[afl_offset];
226
227 *afl = (canfd_afl_entry_t){.id = {.id = filter->id,
228 #ifndef CONFIG_CAN_ACCEPT_RTR
229 .frame_type = CAN_FRAME_TYPE_DATA,
230 #endif
231 .id_mode = ((filter->flags & CAN_FILTER_IDE) != 0)
232 ? CAN_ID_MODE_EXTENDED
233 : CAN_ID_MODE_STANDARD},
234 .mask = {.mask_id = filter->mask,
235 #ifdef CONFIG_CAN_ACCEPT_RTR
236 /* Accept all types of frames */
237 .mask_frame_type = 0,
238 #else
239 /* Only accept frames with the configured frametype */
240 .mask_frame_type = 1,
241 #endif
242 .mask_id_mode = ((filter->flags & CAN_FILTER_IDE) != 0)
243 ? CAN_ID_MODE_EXTENDED
244 : CAN_ID_MODE_STANDARD},
245 .destination = {.fifo_select_flags = CANFD_RX_FIFO_0}};
246
247 if (data->common.started) {
248 /* These steps help update AFL rules while CAN module running */
249 canfd_instance_ctrl_t *p_ctrl = (canfd_instance_ctrl_t *)data->fsp_can.p_ctrl;
250 R_CANFD_Type *reg = p_ctrl->p_reg;
251
252 /* Ignore AFL entry which will be changed */
253 reg->CFDGAFLIGNENT_b.IRN = afl_offset;
254 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos) |
255 BIT(R_CANFD_CFDGAFLIGNCTR_IREN_Pos));
256 reg->CFDGAFLECTR_b.AFLDAE = 1;
257
258 /* Write AFL configuration */
259 reg->CFDGAFL[afl_offset] = *(R_CANFD_CFDGAFL_Type *)afl;
260
261 /* Lock AFL entry access */
262 reg->CFDGAFLECTR_b.AFLDAE = 0;
263 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos));
264 }
265 }
266
remove_afl_rule(const struct device * dev,uint32_t afl_offset)267 static void remove_afl_rule(const struct device *dev, uint32_t afl_offset)
268 {
269 struct can_renesas_ra_data *data = dev->data;
270 canfd_extended_cfg_t const *p_extend = data->fsp_can.p_cfg->p_extend;
271 canfd_afl_entry_t *afl = (canfd_afl_entry_t *)&p_extend->p_afl[afl_offset];
272
273 /* Set the AFL ID to reserved ID */
274 *afl = (canfd_afl_entry_t){
275 .id = {.id = CAN_RENESAS_RA_RESERVED_ID, .id_mode = CAN_ID_MODE_EXTENDED},
276 .mask = {.mask_id = CAN_RENESAS_RA_RESERVED_ID,
277 .mask_id_mode = CAN_ID_MODE_EXTENDED}};
278
279 if (data->common.started) {
280 /* These steps help update AFL rules while CAN module running */
281 canfd_instance_ctrl_t *p_ctrl = (canfd_instance_ctrl_t *)data->fsp_can.p_ctrl;
282 R_CANFD_Type *reg = p_ctrl->p_reg;
283
284 /* Ignore AFL entry which will be changed */
285 reg->CFDGAFLIGNENT_b.IRN = afl_offset;
286 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos) |
287 BIT(R_CANFD_CFDGAFLIGNCTR_IREN_Pos));
288 reg->CFDGAFLECTR_b.AFLDAE = 1;
289
290 /* Change configurations for AFL entry */
291 reg->CFDGAFL[afl_offset] = *(R_CANFD_CFDGAFL_Type *)(afl);
292
293 /* Lock AFL entry access */
294 reg->CFDGAFLECTR_b.AFLDAE = 0;
295 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos));
296 }
297 }
298
299 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
recover_bus(const struct device * dev,k_timeout_t timeout)300 static int recover_bus(const struct device *dev, k_timeout_t timeout)
301 {
302 struct can_renesas_ra_data *data = dev->data;
303 canfd_instance_ctrl_t *p_ctrl = data->fsp_can.p_ctrl;
304 R_CANFD_Type *reg = p_ctrl->p_reg;
305 uint32_t cfdcnctr = reg->CFDC->CTR;
306 int ret = 0;
307
308 if (reg->CFDC->ERFL_b.BOEF == 0) {
309 /* Channel bus-off entry not detected */
310 goto end;
311 }
312
313 reg->CFDC->CTR_b.BOM = 0x00; /* Switch to Normal Bus-Off mode (comply with ISO 11898-1) */
314 reg->CFDC->CTR_b.RTBO = 1; /* Force channel state to return from bus-off */
315
316 int64_t start_ticks = k_uptime_ticks();
317
318 while (reg->CFDC->ERFL_b.BORF == 0) {
319 if ((k_uptime_ticks() - start_ticks) > timeout.ticks) {
320 ret = -EAGAIN;
321 goto end;
322 }
323 }
324 end:
325 reg->CFDC->CTR = cfdcnctr; /* Restore channel configuration */
326 return ret;
327 }
328 #endif
329
can_renesas_ra_call_tx_cb(const struct device * dev,int err)330 static inline void can_renesas_ra_call_tx_cb(const struct device *dev, int err)
331 {
332 struct can_renesas_ra_data *data = dev->data;
333 can_tx_callback_t cb = data->tx_cb;
334
335 if (cb != NULL) {
336 data->tx_cb = NULL;
337 cb(dev, err, data->tx_usr_data);
338 k_sem_give(&data->tx_sem);
339 }
340 }
341
can_renesas_ra_call_rx_cb(const struct device * dev,can_callback_args_t * p_args)342 static inline void can_renesas_ra_call_rx_cb(const struct device *dev, can_callback_args_t *p_args)
343 {
344 struct can_renesas_ra_data *data = dev->data;
345 struct can_renesas_ra_filter *rx_filter = data->rx_filter;
346 const struct can_renesas_ra_cfg *cfg = dev->config;
347 struct can_frame frame = {
348 .dlc = can_bytes_to_dlc(p_args->frame.data_length_code),
349 .id = p_args->frame.id,
350 .flags = (((p_args->frame.id_mode == CAN_ID_MODE_EXTENDED) ? CAN_FRAME_IDE : 0UL) |
351 ((p_args->frame.type == CAN_FRAME_TYPE_REMOTE) ? CAN_FRAME_RTR : 0UL) |
352 ((p_args->frame.options & CANFD_FRAME_OPTION_FD) != 0 ? CAN_FRAME_FDF
353 : 0UL) |
354 ((p_args->frame.options & CANFD_FRAME_OPTION_ERROR) != 0 ? CAN_FRAME_ESI
355 : 0UL) |
356 ((p_args->frame.options & CANFD_FRAME_OPTION_BRS) != 0 ? CAN_FRAME_BRS
357 : 0UL)),
358 };
359
360 memcpy(frame.data, p_args->frame.data, p_args->frame.data_length_code);
361
362 for (uint32_t i = 0; i < cfg->rx_filter_num; i++) {
363 can_rx_callback_t cb = rx_filter->rx_cb;
364 void *usr_data = rx_filter->rx_usr_data;
365
366 if (cb == NULL) {
367 rx_filter++;
368 continue; /* this filter has not set yet */
369 }
370
371 if (!can_frame_matches_filter(&frame, &rx_filter->filter)) {
372 rx_filter++;
373 continue; /* filter did not match */
374 }
375
376 cb(dev, &frame, usr_data);
377 break;
378 }
379 }
380
can_renesas_ra_call_state_change_cb(const struct device * dev,enum can_state state)381 static inline void can_renesas_ra_call_state_change_cb(const struct device *dev,
382 enum can_state state)
383 {
384 struct can_renesas_ra_data *data = dev->data;
385 can_info_t can_info;
386
387 if (FSP_SUCCESS != can_api->infoGet(data->fsp_can.p_ctrl, &can_info)) {
388 LOG_DBG("get state info failed");
389 return;
390 }
391
392 struct can_bus_err_cnt err_cnt = {
393 .rx_err_cnt = can_info.error_count_receive,
394 .tx_err_cnt = can_info.error_count_transmit,
395 };
396
397 data->common.state_change_cb(dev, state, err_cnt, data->common.state_change_cb_user_data);
398 }
399
can_renesas_ra_get_capabilities(const struct device * dev,can_mode_t * cap)400 static int can_renesas_ra_get_capabilities(const struct device *dev, can_mode_t *cap)
401 {
402 ARG_UNUSED(dev);
403 *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK;
404
405 #ifdef CONFIG_CAN_FD_MODE
406 *cap |= CAN_MODE_FD;
407 #endif
408
409 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
410 *cap |= CAN_MODE_MANUAL_RECOVERY;
411 #endif
412
413 return 0;
414 }
415
can_renesas_ra_start(const struct device * dev)416 static int can_renesas_ra_start(const struct device *dev)
417 {
418 struct can_renesas_ra_data *data = dev->data;
419 const struct device *transceiver_dev = can_get_transceiver(dev);
420 int ret = 0;
421
422 if (!device_is_ready(dev)) {
423 return -EIO;
424 }
425
426 if (data->common.started) {
427 return -EALREADY;
428 }
429
430 if (((transceiver_dev != NULL) &&
431 can_transceiver_enable(transceiver_dev, data->common.mode))) {
432 LOG_DBG("CAN transceiver enable failed");
433 return -EIO;
434 }
435
436 k_mutex_lock(&data->inst_mutex, K_FOREVER);
437 canfd_extended_cfg_t *p_extend = (canfd_extended_cfg_t *)data->fsp_can.p_cfg->p_extend;
438
439 p_extend->p_data_timing =
440 (can_bit_timing_cfg_t *)((data->common.mode & CAN_MODE_FD) != 0
441 ? &data->data_timing
442 : &classic_can_data_timing_default);
443
444 if (FSP_SUCCESS != can_api->close(data->fsp_can.p_ctrl)) {
445 LOG_DBG("CAN close failed");
446 ret = -EIO;
447 goto end;
448 }
449
450 if (FSP_SUCCESS != can_api->open(data->fsp_can.p_ctrl, data->fsp_can.p_cfg)) {
451 LOG_DBG("CAN open failed");
452 ret = -EIO;
453 goto end;
454 }
455
456 if ((data->common.mode & CAN_MODE_LOOPBACK) != 0) {
457 if (FSP_SUCCESS != can_api->modeTransition(data->fsp_can.p_ctrl,
458 CAN_OPERATION_MODE_NORMAL,
459 CAN_TEST_MODE_LOOPBACK_INTERNAL)) {
460 LOG_DBG("CAN mode change failed");
461 ret = -EIO;
462 goto end;
463 }
464 }
465
466 data->common.started = true;
467 end:
468 k_mutex_unlock(&data->inst_mutex);
469 return ret;
470 }
471
can_renesas_ra_stop(const struct device * dev)472 static int can_renesas_ra_stop(const struct device *dev)
473 {
474 struct can_renesas_ra_data *data = dev->data;
475 const struct device *transceiver_dev = can_get_transceiver(dev);
476 int ret = 0;
477
478 if (!data->common.started) {
479 return -EALREADY;
480 }
481
482 k_mutex_lock(&data->inst_mutex, K_FOREVER);
483
484 if (FSP_SUCCESS != can_api->modeTransition(data->fsp_can.p_ctrl, CAN_OPERATION_MODE_HALT,
485 CAN_TEST_MODE_DISABLED)) {
486 LOG_DBG("CAN stop failed");
487 ret = -EIO;
488 goto end;
489 }
490
491 if (((transceiver_dev != NULL) && can_transceiver_disable(transceiver_dev))) {
492 LOG_DBG("CAN transceiver disable failed");
493 ret = -EIO;
494 goto end;
495 }
496
497 if (data->tx_cb != NULL) {
498 data->tx_cb = NULL;
499 k_sem_give(&data->tx_sem);
500 }
501
502 data->common.started = false;
503
504 end:
505 k_mutex_unlock(&data->inst_mutex);
506 return ret;
507 }
508
can_renesas_ra_set_mode(const struct device * dev,can_mode_t mode)509 static int can_renesas_ra_set_mode(const struct device *dev, can_mode_t mode)
510 {
511 struct can_renesas_ra_data *data = dev->data;
512 int ret = 0;
513
514 if (data->common.started) {
515 /* CAN controller should be in stopped state */
516 return -EBUSY;
517 }
518
519 k_mutex_lock(&data->inst_mutex, K_FOREVER);
520
521 can_mode_t caps = 0;
522
523 ret = can_renesas_ra_get_capabilities(dev, &caps);
524 if (ret != 0) {
525 goto end;
526 }
527
528 if ((mode & ~caps) != 0) {
529 ret = -ENOTSUP;
530 goto end;
531 }
532
533 data->common.mode = mode;
534
535 end:
536 k_mutex_unlock(&data->inst_mutex);
537 return ret;
538 }
539
can_renesas_ra_set_timing(const struct device * dev,const struct can_timing * timing)540 static int can_renesas_ra_set_timing(const struct device *dev, const struct can_timing *timing)
541 {
542 struct can_renesas_ra_data *data = dev->data;
543
544 if (data->common.started) {
545 /* Device is not in stopped state */
546 return -EBUSY;
547 }
548
549 return set_hw_timing_configuration(dev, data->fsp_can.p_cfg->p_bit_timing, timing);
550 }
551
can_renesas_ra_send(const struct device * dev,const struct can_frame * frame,k_timeout_t timeout,can_tx_callback_t callback,void * user_data)552 static int can_renesas_ra_send(const struct device *dev, const struct can_frame *frame,
553 k_timeout_t timeout, can_tx_callback_t callback, void *user_data)
554 {
555 struct can_renesas_ra_data *data = dev->data;
556
557 if (!data->common.started) {
558 return -ENETDOWN;
559 }
560
561 #ifdef CONFIG_CAN_FD_MODE
562 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR | CAN_FRAME_FDF | CAN_FRAME_BRS)) !=
563 0) {
564 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
565 return -ENOTSUP;
566 }
567
568 if ((data->common.mode & CAN_MODE_FD) == 0U &&
569 ((frame->flags & (CAN_FRAME_FDF | CAN_FRAME_BRS)) != 0U)) {
570 LOG_ERR("CAN FD format not supported in non-FD mode");
571 return -ENOTSUP;
572 }
573 #else /* CONFIG_CAN_FD_MODE */
574 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0U) {
575 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
576 return -ENOTSUP;
577 }
578 #endif /* !CONFIG_CAN_FD_MODE */
579
580 if ((frame->flags & CAN_FRAME_FDF) != 0U) {
581 if (frame->dlc > CANFD_MAX_DLC) {
582 LOG_ERR("DLC of %d for CAN FD format frame", frame->dlc);
583 return -EINVAL;
584 }
585 } else {
586 if (frame->dlc > CAN_MAX_DLC) {
587 LOG_ERR("DLC of %d for non-FD format frame", frame->dlc);
588 return -EINVAL;
589 }
590 }
591
592 if (k_sem_take(&data->tx_sem, timeout) != 0) {
593 return -EAGAIN;
594 }
595
596 k_mutex_lock(&data->inst_mutex, K_FOREVER);
597 int ret = 0;
598
599 data->tx_cb = callback;
600 data->tx_usr_data = user_data;
601
602 can_frame_t fsp_frame = {
603 .id = frame->id,
604 .id_mode = ((frame->flags & CAN_FRAME_IDE) != 0) ? CAN_ID_MODE_EXTENDED
605 : CAN_ID_MODE_STANDARD,
606 .type = ((frame->flags & CAN_FRAME_RTR) != 0) ? CAN_FRAME_TYPE_REMOTE
607 : CAN_FRAME_TYPE_DATA,
608 .data_length_code = can_dlc_to_bytes(frame->dlc),
609 .options =
610 ((((frame->flags & CAN_FRAME_FDF) != 0) ? CANFD_FRAME_OPTION_FD : 0UL) |
611 (((frame->flags & CAN_FRAME_BRS) != 0) ? CANFD_FRAME_OPTION_BRS : 0UL) |
612 (((frame->flags & CAN_FRAME_ESI) != 0) ? CANFD_FRAME_OPTION_ERROR : 0UL)),
613 };
614
615 memcpy(fsp_frame.data, frame->data, fsp_frame.data_length_code);
616
617 if (FSP_SUCCESS != can_api->write(data->fsp_can.p_ctrl, CANFD_TX_BUFFER_0, &fsp_frame)) {
618 LOG_DBG("CAN transmit failed");
619 data->tx_cb = NULL;
620 data->tx_usr_data = NULL;
621 k_sem_give(&data->tx_sem);
622 ret = -EIO;
623 goto end;
624 }
625
626 end:
627 k_mutex_unlock(&data->inst_mutex);
628 return ret;
629 }
630
can_renesas_ra_add_rx_filter(const struct device * dev,can_rx_callback_t callback,void * user_data,const struct can_filter * filter)631 static int can_renesas_ra_add_rx_filter(const struct device *dev, can_rx_callback_t callback,
632 void *user_data, const struct can_filter *filter)
633 {
634 struct can_renesas_ra_data *data = dev->data;
635 int filter_id = -ENOSPC;
636
637 k_mutex_lock(&data->inst_mutex, K_FOREVER);
638
639 filter_id = get_free_filter_id(dev);
640 if (filter_id == -ENOSPC) {
641 goto end;
642 }
643
644 set_afl_rule(dev, filter, filter_id);
645
646 memcpy(&data->rx_filter[filter_id].filter, filter, sizeof(struct can_filter));
647 data->rx_filter[filter_id].rx_cb = callback;
648 data->rx_filter[filter_id].rx_usr_data = user_data;
649 data->rx_filter[filter_id].set = true;
650
651 end:
652 k_mutex_unlock(&data->inst_mutex);
653 return filter_id;
654 }
655
can_renesas_ra_remove_rx_filter(const struct device * dev,int filter_id)656 static void can_renesas_ra_remove_rx_filter(const struct device *dev, int filter_id)
657 {
658 struct can_renesas_ra_data *data = dev->data;
659 const struct can_renesas_ra_cfg *cfg = dev->config;
660
661 if ((filter_id < 0) || (filter_id >= cfg->rx_filter_num)) {
662 return;
663 }
664
665 k_mutex_lock(&data->inst_mutex, K_FOREVER);
666
667 remove_afl_rule(dev, filter_id);
668
669 data->rx_filter[filter_id].rx_cb = NULL;
670 data->rx_filter[filter_id].rx_usr_data = NULL;
671 data->rx_filter[filter_id].set = false;
672
673 k_mutex_unlock(&data->inst_mutex);
674 }
675
676 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
can_renesas_ra_recover(const struct device * dev,k_timeout_t timeout)677 static int can_renesas_ra_recover(const struct device *dev, k_timeout_t timeout)
678 {
679 struct can_renesas_ra_data *data = dev->data;
680
681 if (!data->common.started) {
682 return -ENETDOWN;
683 }
684
685 if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0) {
686 return -ENOTSUP;
687 }
688
689 return recover_bus(dev, timeout);
690 }
691 #endif
692
can_renesas_ra_get_state(const struct device * dev,enum can_state * state,struct can_bus_err_cnt * err_cnt)693 static int can_renesas_ra_get_state(const struct device *dev, enum can_state *state,
694 struct can_bus_err_cnt *err_cnt)
695 {
696 struct can_renesas_ra_data *data = dev->data;
697 can_info_t fsp_info = {0};
698
699 if (state == NULL && err_cnt == NULL) {
700 return 0;
701 }
702
703 if (FSP_SUCCESS != can_api->infoGet(data->fsp_can.p_ctrl, &fsp_info)) {
704 LOG_DBG("CAN get state info failed");
705 return -EIO;
706 }
707
708 if (state != NULL) {
709 if (!data->common.started) {
710 *state = CAN_STATE_STOPPED;
711 } else {
712 if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_BOEF_Msk) != 0) {
713 *state = CAN_STATE_BUS_OFF;
714 } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_EPF_Msk) != 0) {
715 *state = CAN_STATE_ERROR_PASSIVE;
716 } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_EWF_Msk) != 0) {
717 *state = CAN_STATE_ERROR_WARNING;
718 } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_BEF_Msk) != 0) {
719 *state = CAN_STATE_ERROR_ACTIVE;
720 }
721 }
722 }
723
724 if (err_cnt != NULL) {
725 err_cnt->tx_err_cnt = fsp_info.error_count_transmit;
726 err_cnt->rx_err_cnt = fsp_info.error_count_receive;
727 }
728
729 return 0;
730 }
731
can_renesas_ra_set_state_change_callback(const struct device * dev,can_state_change_callback_t callback,void * user_data)732 static void can_renesas_ra_set_state_change_callback(const struct device *dev,
733 can_state_change_callback_t callback,
734 void *user_data)
735 {
736 struct can_renesas_ra_data *data = dev->data;
737 canfd_instance_ctrl_t *p_ctrl = data->fsp_can.p_ctrl;
738 int key = irq_lock();
739
740 k_mutex_lock(&data->inst_mutex, K_FOREVER);
741
742 if (callback != NULL) {
743 /* Enable state change interrupt */
744 p_ctrl->p_reg->CFDC->CTR |= (uint32_t)CANFD_CFG_ERR_IRQ;
745 } else {
746 /* Disable state change interrupt */
747 p_ctrl->p_reg->CFDC->CTR &= (uint32_t)~CANFD_CFG_ERR_IRQ;
748
749 /* Clear state change interrupt flags */
750 p_ctrl->p_reg->CFDC->ERFL &=
751 ~(BIT(R_CANFD_CFDC_ERFL_BOEF_Pos) | BIT(R_CANFD_CFDC_ERFL_EWF_Pos) |
752 BIT(R_CANFD_CFDC_ERFL_EPF_Pos) | BIT(R_CANFD_CFDC_ERFL_BOEF_Pos));
753 }
754
755 data->common.state_change_cb = callback;
756 data->common.state_change_cb_user_data = user_data;
757
758 k_mutex_unlock(&data->inst_mutex);
759
760 irq_unlock(key);
761 }
762
can_renesas_ra_get_core_clock(const struct device * dev,uint32_t * rate)763 static int can_renesas_ra_get_core_clock(const struct device *dev, uint32_t *rate)
764 {
765 const struct can_renesas_ra_cfg *cfg = dev->config;
766 clock_control_subsys_t dll_subsys = (clock_control_subsys_t)&cfg->dll_subsys;
767
768 return clock_control_get_rate(cfg->dll_clk, dll_subsys, rate);
769 }
770
can_renesas_ra_get_max_filters(const struct device * dev,bool ide)771 static int can_renesas_ra_get_max_filters(const struct device *dev, bool ide)
772 {
773 ARG_UNUSED(ide);
774 const struct can_renesas_ra_cfg *cfg = dev->config;
775
776 return cfg->rx_filter_num;
777 }
778
779 #ifdef CONFIG_CAN_FD_MODE
can_renesas_ra_set_timing_data(const struct device * dev,const struct can_timing * timing_data)780 static int can_renesas_ra_set_timing_data(const struct device *dev,
781 const struct can_timing *timing_data)
782 {
783 struct can_renesas_ra_data *data = dev->data;
784
785 if (data->common.started) {
786 return -EBUSY;
787 }
788
789 return set_hw_timing_configuration(dev, &data->data_timing, timing_data);
790 }
791 #endif /* CONFIG_CAN_FD_MODE */
792
can_renesas_ra_fsp_cb(can_callback_args_t * p_args)793 void can_renesas_ra_fsp_cb(can_callback_args_t *p_args)
794 {
795 const struct device *dev = p_args->p_context;
796
797 switch (p_args->event) {
798 case CAN_EVENT_RX_COMPLETE: {
799 can_renesas_ra_call_rx_cb(dev, p_args);
800 break;
801 }
802
803 case CAN_EVENT_TX_COMPLETE: {
804 can_renesas_ra_call_tx_cb(dev, 0);
805 break;
806 }
807
808 case CAN_EVENT_ERR_CHANNEL: {
809 if ((p_args->error & R_CANFD_CFDC_ERFL_BEF_Msk) != 0) {
810 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_ERROR_ACTIVE);
811 }
812 if ((p_args->error & R_CANFD_CFDC_ERFL_EWF_Msk) != 0) {
813 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_ERROR_WARNING);
814 }
815 if ((p_args->error & R_CANFD_CFDC_ERFL_EPF_Msk) != 0) {
816 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_ERROR_PASSIVE);
817 }
818 if ((p_args->error & R_CANFD_CFDC_ERFL_BOEF_Msk) != 0) {
819 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_BUS_OFF);
820 }
821
822 if ((p_args->error & R_CANFD_CFDC_ERFL_ALF_Msk) != 0) { /* Arbitration Lost Error */
823 can_renesas_ra_call_tx_cb(dev, -EBUSY);
824 }
825 if ((p_args->error & (R_CANFD_CFDC_ERFL_AERR_Msk | /* ACK Error */
826 R_CANFD_CFDC_ERFL_ADERR_Msk | /* ACK Delimiter Error */
827 R_CANFD_CFDC_ERFL_B1ERR_Msk | /* Bit 1 Error */
828 R_CANFD_CFDC_ERFL_B0ERR_Msk)) /* Bit 0 Error */
829 != 0) {
830 can_renesas_ra_call_tx_cb(dev, -EIO);
831 }
832 }
833
834 default:
835 break;
836 }
837 }
838
can_renesas_ra_apply_default_config(const struct device * dev)839 static inline int can_renesas_ra_apply_default_config(const struct device *dev)
840 {
841 struct can_renesas_ra_cfg *cfg = (struct can_renesas_ra_cfg *)dev->config;
842 int ret;
843
844 struct can_timing timing = {0};
845
846 /* Calculate bit_timing parameter */
847 ret = can_calc_timing(dev, &timing, cfg->common.bitrate, cfg->common.sample_point);
848 if (ret < 0) {
849 return ret;
850 }
851
852 ret = can_renesas_ra_set_timing(dev, &timing);
853 if (ret != 0) {
854 return ret;
855 }
856
857 #ifdef CONFIG_CAN_FD_MODE
858 can_calc_timing_data(dev, &timing, cfg->common.bitrate_data, cfg->common.sample_point_data);
859 ret = can_renesas_ra_set_timing_data(dev, &timing);
860 if (ret < 0) {
861 return ret;
862 }
863 #endif
864
865 for (uint32_t filter_id = 0; filter_id < cfg->rx_filter_num; filter_id++) {
866 remove_afl_rule(dev, filter_id);
867 }
868
869 return 0;
870 }
871
can_renesas_module_clock_init(const struct device * dev)872 static inline int can_renesas_module_clock_init(const struct device *dev)
873 {
874 const struct can_renesas_ra_cfg *cfg = dev->config;
875 const struct can_renesas_ra_global_cfg *global_cfg = cfg->global_dev->config;
876 int ret;
877
878 ret = clock_control_on(cfg->dll_clk, (clock_control_subsys_t)&cfg->dll_subsys);
879 if (ret < 0) {
880 return -EIO;
881 }
882
883 uint32_t op_rate;
884 uint32_t ram_rate;
885 uint32_t dll_rate;
886
887 ret = clock_control_get_rate(global_cfg->op_clk,
888 (clock_control_subsys_t)&global_cfg->op_subsys, &op_rate);
889 if (ret < 0) {
890 return ret;
891 }
892
893 ret = clock_control_get_rate(global_cfg->ram_clk,
894 (clock_control_subsys_t)&global_cfg->ram_subsys, &ram_rate);
895 if (ret < 0) {
896 return ret;
897 }
898
899 ret = clock_control_get_rate(cfg->dll_clk, (clock_control_subsys_t)&cfg->dll_subsys,
900 &dll_rate);
901 if (ret < 0) {
902 return ret;
903 }
904
905 /* Clock constraint: refer to '34.1.2 Clock restriction' - RA8M1 MCU group HWM */
906 /*
907 * Operation clock rate must be at least 40Mhz in case CANFD mode.
908 * Otherwise, it must be at least 32MHz.
909 */
910 if (IS_ENABLED(CONFIG_CAN_FD_MODE) ? op_rate < 40000000 : op_rate < 32000000) {
911 return -ENOTSUP;
912 }
913 /*
914 * (RAM clock rate / 2) >= DLL rate
915 * (CANFD operation clock rate) >= DLL rate
916 */
917 if ((ram_rate / 2) < dll_rate || op_rate < dll_rate) {
918 return -ENOTSUP;
919 }
920
921 return 0;
922 }
923
can_renesas_ra_init(const struct device * dev)924 static int can_renesas_ra_init(const struct device *dev)
925 {
926 const struct can_renesas_ra_cfg *cfg = dev->config;
927 struct can_renesas_ra_data *data = dev->data;
928 int ret = 0;
929
930 k_mutex_init(&data->inst_mutex);
931 k_sem_init(&data->tx_sem, 1, 1);
932 data->common.started = false;
933
934 ret = can_renesas_module_clock_init(dev);
935 if (ret < 0) {
936 LOG_DBG("clock initialize failed");
937 return ret;
938 }
939
940 /* Configure dt provided device signals when available */
941 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
942 if (ret < 0) {
943 LOG_DBG("pin function initial failed");
944 return ret;
945 }
946
947 /* Apply config and setting for CAN controller HW */
948 ret = can_renesas_ra_apply_default_config(dev);
949 if (ret < 0) {
950 LOG_DBG("invalid default configuration");
951 return ret;
952 }
953
954 ret = can_api->open(data->fsp_can.p_ctrl, data->fsp_can.p_cfg);
955 if (ret != FSP_SUCCESS) {
956 LOG_DBG("CAN bus initialize failed");
957 return -EIO;
958 }
959
960 /* Put CAN controller into stopped state */
961 ret = can_api->modeTransition(data->fsp_can.p_ctrl, CAN_OPERATION_MODE_HALT,
962 CAN_TEST_MODE_DISABLED);
963 if (ret != FSP_SUCCESS) {
964 can_api->close(data->fsp_can.p_ctrl);
965 LOG_DBG("CAN bus initialize failed");
966 return -EIO;
967 }
968
969 return 0;
970 }
971
972 static DEVICE_API(can, can_renesas_ra_driver_api) = {
973 .get_capabilities = can_renesas_ra_get_capabilities,
974 .start = can_renesas_ra_start,
975 .stop = can_renesas_ra_stop,
976 .set_mode = can_renesas_ra_set_mode,
977 .set_timing = can_renesas_ra_set_timing,
978 .send = can_renesas_ra_send,
979 .add_rx_filter = can_renesas_ra_add_rx_filter,
980 .remove_rx_filter = can_renesas_ra_remove_rx_filter,
981 #if defined(CONFIG_CAN_MANUAL_RECOVERY_MODE)
982 .recover = can_renesas_ra_recover,
983 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
984 .get_state = can_renesas_ra_get_state,
985 .set_state_change_callback = can_renesas_ra_set_state_change_callback,
986 .get_core_clock = can_renesas_ra_get_core_clock,
987 .get_max_filters = can_renesas_ra_get_max_filters,
988 .timing_min = CAN_RENESAS_RA_TIMING_MIN,
989 .timing_max = CAN_RENESAS_RA_TIMING_MAX,
990 #if defined(CONFIG_CAN_FD_MODE)
991 .set_timing_data = can_renesas_ra_set_timing_data,
992 .timing_data_min = CAN_RENESAS_RA_TIMING_DATA_MIN,
993 .timing_data_max = CAN_RENESAS_RA_TIMING_DATA_MAX,
994 #endif /* CONFIG_CAN_FD_MODE */
995 };
996
997 #define CAN_RENESAS_RA_GLOBAL_IRQ_INIT() \
998 R_ICU->IELSR_b[VECTOR_NUMBER_CAN_GLERR].IELS = ELC_EVENT_CAN_GLERR; \
999 R_ICU->IELSR_b[VECTOR_NUMBER_CAN_RXF].IELS = ELC_EVENT_CAN_RXF; \
1000 IRQ_CONNECT(VECTOR_NUMBER_CAN_GLERR, \
1001 DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), glerr, \
1002 priority), \
1003 canfd_error_isr, NULL, 0); \
1004 IRQ_CONNECT(VECTOR_NUMBER_CAN_RXF, \
1005 DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), rxf, \
1006 priority), \
1007 canfd_rx_fifo_isr, NULL, 0); \
1008 irq_enable(VECTOR_NUMBER_CAN_RXF); \
1009 irq_enable(VECTOR_NUMBER_CAN_GLERR);
1010
1011 static canfd_global_cfg_t g_canfd_global_cfg = {
1012 .global_interrupts = CANFD_CFG_GLERR_IRQ,
1013 .global_config = CANFD_CFG_GLOBAL,
1014 .rx_mb_config = CANFD_CFG_RXMB,
1015 .global_err_ipl = DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global),
1016 glerr, priority),
1017 .rx_fifo_ipl = DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), rxf,
1018 priority),
1019 .rx_fifo_config = CANFD_CFG_RXFIFO,
1020 .common_fifo_config = CANFD_CFG_COMMONFIFO,
1021 };
1022
1023 static const struct can_renesas_ra_global_cfg g_can_renesas_ra_global_cfg = {
1024 .op_clk = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(
1025 DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), opclk)),
1026 .ram_clk = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(
1027 DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), ramclk)),
1028 .op_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(
1029 DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), opclk, mstp),
1030 .stop_bit = DT_CLOCKS_CELL_BY_NAME(
1031 DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), opclk,
1032 stop_bit)},
1033 .ram_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(
1034 DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), ramclk,
1035 mstp),
1036 .stop_bit = DT_CLOCKS_CELL_BY_NAME(
1037 DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), ramclk,
1038 stop_bit)},
1039 };
1040
can_renesas_ra_global_init(const struct device * dev)1041 static int can_renesas_ra_global_init(const struct device *dev)
1042 {
1043 int ret;
1044 const struct can_renesas_ra_global_cfg *cfg = dev->config;
1045
1046 ret = clock_control_on(cfg->op_clk, (clock_control_subsys_t)&cfg->op_subsys);
1047 if (ret < 0) {
1048 LOG_DBG("clock initialize failed");
1049 return ret;
1050 }
1051
1052 ret = clock_control_on(cfg->ram_clk, (clock_control_subsys_t)&cfg->ram_subsys);
1053 if (ret < 0) {
1054 LOG_DBG("clock initialize failed");
1055 return ret;
1056 }
1057
1058 CAN_RENESAS_RA_GLOBAL_IRQ_INIT();
1059
1060 return 0;
1061 }
1062
1063 DEVICE_DT_DEFINE(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), can_renesas_ra_global_init,
1064 NULL, NULL, &g_can_renesas_ra_global_cfg, PRE_KERNEL_2, CONFIG_CAN_INIT_PRIORITY,
1065 NULL)
1066
1067 #define _ELC_EVENT_CAN_COMFRX(channel) ELC_EVENT_CAN##channel##_COMFRX
1068 #define _ELC_EVENT_CAN_TX(channel) ELC_EVENT_CAN##channel##_TX
1069 #define _ELC_EVENT_CAN_CHERR(channel) ELC_EVENT_CAN##channel##_CHERR
1070
1071 #define ELC_EVENT_CAN_COMFRX(channel) _ELC_EVENT_CAN_COMFRX(channel)
1072 #define ELC_EVENT_CAN_TX(channel) _ELC_EVENT_CAN_TX(channel)
1073 #define ELC_EVENT_CAN_CHERR(channel) _ELC_EVENT_CAN_CHERR(channel)
1074
1075 #define CAN_RENESAS_RA_CHANNEL_IRQ_INIT(index) \
1076 { \
1077 R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, rx, irq)].IELS = \
1078 ELC_EVENT_CAN_COMFRX(DT_INST_PROP(index, channel)); \
1079 R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, tx, irq)].IELS = \
1080 ELC_EVENT_CAN_TX(DT_INST_PROP(index, channel)); \
1081 R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, err, irq)].IELS = \
1082 ELC_EVENT_CAN_CHERR(DT_INST_PROP(index, channel)); \
1083 \
1084 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, rx, irq), \
1085 DT_INST_IRQ_BY_NAME(index, rx, priority), canfd_common_fifo_rx_isr, \
1086 NULL, 0); \
1087 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, tx, irq), \
1088 DT_INST_IRQ_BY_NAME(index, tx, priority), canfd_channel_tx_isr, NULL, \
1089 0); \
1090 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, err, irq), \
1091 DT_INST_IRQ_BY_NAME(index, err, priority), canfd_error_isr, NULL, 0); \
1092 \
1093 irq_enable(DT_INST_IRQ_BY_NAME(index, rx, irq)); \
1094 irq_enable(DT_INST_IRQ_BY_NAME(index, tx, irq)); \
1095 irq_enable(DT_INST_IRQ_BY_NAME(index, err, irq)); \
1096 }
1097
1098 #define CAN_RENESAS_RA_INIT(index) \
1099 PINCTRL_DT_INST_DEFINE(index); \
1100 static canfd_afl_entry_t canfd_afl##index[DT_INST_PROP(index, rx_max_filters)]; \
1101 struct can_renesas_ra_filter \
1102 can_renesas_ra_rx_filter##index[DT_INST_PROP(index, rx_max_filters)]; \
1103 static can_bit_timing_cfg_t g_canfd_bit_timing##index; \
1104 static const struct can_renesas_ra_cfg can_renesas_ra_cfg##index = { \
1105 .common = CAN_DT_DRIVER_CONFIG_INST_GET(index, 0, 5000000), \
1106 .global_dev = DEVICE_DT_GET(DT_INST_PARENT(index)), \
1107 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
1108 .dll_clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(index, dllclk)), \
1109 .dll_subsys = \
1110 { \
1111 .mstp = DT_INST_CLOCKS_CELL_BY_NAME(index, dllclk, mstp), \
1112 .stop_bit = DT_INST_CLOCKS_CELL_BY_NAME(index, dllclk, stop_bit), \
1113 }, \
1114 .rx_filter_num = DT_INST_PROP(index, rx_max_filters), \
1115 }; \
1116 static canfd_instance_ctrl_t fsp_canfd_ctrl##index; \
1117 static canfd_extended_cfg_t fsp_canfd_extend####index = { \
1118 .p_afl = canfd_afl##index, \
1119 .txmb_txi_enable = CANFD_CFG_TXMB_TXI_ENABLE, \
1120 .error_interrupts = 0U, \
1121 .p_global_cfg = &g_canfd_global_cfg, \
1122 }; \
1123 static can_cfg_t fsp_canfd_cfg####index = { \
1124 .channel = DT_INST_PROP(index, channel), \
1125 .ipl = DT_INST_IRQ_BY_NAME(index, err, priority), \
1126 .error_irq = DT_INST_IRQ_BY_NAME(index, err, irq), \
1127 .rx_irq = DT_INST_IRQ_BY_NAME(index, rx, irq), \
1128 .tx_irq = DT_INST_IRQ_BY_NAME(index, tx, irq), \
1129 .p_extend = &fsp_canfd_extend##index, \
1130 .p_bit_timing = &g_canfd_bit_timing##index, \
1131 .p_context = DEVICE_DT_INST_GET(index), \
1132 .p_callback = can_renesas_ra_fsp_cb, \
1133 }; \
1134 static struct can_renesas_ra_data can_renesas_ra_data##index = { \
1135 .fsp_can = \
1136 { \
1137 .p_ctrl = &fsp_canfd_ctrl##index, \
1138 .p_cfg = &fsp_canfd_cfg##index, \
1139 .p_api = &g_canfd_on_canfd, \
1140 }, \
1141 .rx_filter = can_renesas_ra_rx_filter##index, \
1142 .dev = DEVICE_DT_INST_GET(index), \
1143 }; \
1144 static int can_renesas_ra_init##index(const struct device *dev) \
1145 { \
1146 const struct device *global_canfd = DEVICE_DT_GET(DT_INST_PARENT(index)); \
1147 if (!device_is_ready(global_canfd)) { \
1148 return -EIO; \
1149 } \
1150 CAN_RENESAS_RA_CHANNEL_IRQ_INIT(index) \
1151 return can_renesas_ra_init(dev); \
1152 } \
1153 CAN_DEVICE_DT_INST_DEFINE(index, can_renesas_ra_init##index, NULL, \
1154 &can_renesas_ra_data##index, &can_renesas_ra_cfg##index, \
1155 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
1156 &can_renesas_ra_driver_api);
1157
1158 DT_INST_FOREACH_STATUS_OKAY(CAN_RENESAS_RA_INIT)
1159
