1 /*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief System/hardware module for Nordic Semiconductor nRF54L family processor
10 *
11 * This module provides routines to initialize and support board-level hardware
12 * for the Nordic Semiconductor nRF54L family processor.
13 */
14
15 #include <zephyr/kernel.h>
16 #include <zephyr/devicetree.h>
17 #include <zephyr/init.h>
18 #include <zephyr/logging/log.h>
19 #include <zephyr/cache.h>
20
21 #if defined(NRF_APPLICATION)
22 #include <cmsis_core.h>
23 #include <hal/nrf_glitchdet.h>
24 #include <hal/nrf_oscillators.h>
25 #include <hal/nrf_power.h>
26 #include <hal/nrf_regulators.h>
27 #endif
28 #include <soc/nrfx_coredep.h>
29
30 #include <system_nrf54l.h>
31
32 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
33
34 #if defined(NRF_APPLICATION)
35 #define LFXO_NODE DT_NODELABEL(lfxo)
36 #define HFXO_NODE DT_NODELABEL(hfxo)
37 #endif
38
nordicsemi_nrf54l_init(void)39 static int nordicsemi_nrf54l_init(void)
40 {
41 /* Update the SystemCoreClock global variable with current core clock
42 * retrieved from hardware state.
43 */
44 SystemCoreClockUpdate();
45
46 #if defined(NRF_APPLICATION)
47 /* Enable ICACHE */
48 sys_cache_instr_enable();
49
50 #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
51 uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM;
52
53 uint32_t offset_k =
54 (xosc32ktrim & FICR_XOSC32KTRIM_OFFSET_Msk) >> FICR_XOSC32KTRIM_OFFSET_Pos;
55
56 uint32_t slope_field_k =
57 (xosc32ktrim & FICR_XOSC32KTRIM_SLOPE_Msk) >> FICR_XOSC32KTRIM_SLOPE_Pos;
58 uint32_t slope_mask_k = FICR_XOSC32KTRIM_SLOPE_Msk >> FICR_XOSC32KTRIM_SLOPE_Pos;
59 uint32_t slope_sign_k = (slope_mask_k - (slope_mask_k >> 1));
60 int32_t slope_k = (int32_t)(slope_field_k ^ slope_sign_k) - (int32_t)slope_sign_k;
61
62 /* As specified in the nRF54L15 PS:
63 * CAPVALUE = round( (CAPACITANCE - 4) * (FICR->XOSC32KTRIM.SLOPE + 0.765625 * 2^9)/(2^9)
64 * + FICR->XOSC32KTRIM.OFFSET/(2^6) );
65 * where CAPACITANCE is the desired capacitor value in pF, holding any
66 * value between 4 pF and 18 pF in 0.5 pF steps.
67 */
68
69 /* Encoding of desired capacitance (single ended) to value required for INTCAP core
70 * calculation: (CAP_VAL - 4 pF)* 0.5
71 * That translate to ((CAP_VAL_FEMTO_F - 4000fF) * 2UL) / 1000UL
72 *
73 * NOTE: The desired capacitance value is used in encoded from in INTCAP calculation formula
74 * That is different than in case of HFXO.
75 */
76 uint32_t cap_val_encoded = (((DT_PROP(LFXO_NODE, load_capacitance_femtofarad) - 4000UL)
77 * 2UL) / 1000UL);
78
79 /* Calculation of INTCAP code before rounding. Min that calculations here are done on
80 * values multiplied by 2^9, e.g. 0.765625 * 2^9 = 392.
81 * offset_k should be divided by 2^6, but to add it to value shifted by 2^9 we have to
82 * multiply it be 2^3.
83 */
84 uint32_t mid_val = (cap_val_encoded - 4UL) * (uint32_t)(slope_k + 392UL)
85 + (offset_k << 3UL);
86
87 /* Get integer part of the INTCAP code */
88 uint32_t lfxo_intcap = mid_val >> 9UL;
89
90 /* Round based on fractional part */
91 if ((mid_val & BIT_MASK(9)) > (BIT_MASK(9) / 2)) {
92 lfxo_intcap++;
93 }
94
95 nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, lfxo_intcap);
96 #elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
97 nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, (nrf_oscillators_lfxo_cap_t)0);
98 #endif
99
100 #if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
101 uint32_t xosc32mtrim = NRF_FICR->XOSC32MTRIM;
102 /* The SLOPE field is in the two's complement form, hence this special
103 * handling. Ideally, it would result in just one SBFX instruction for
104 * extracting the slope value, at least gcc is capable of producing such
105 * output, but since the compiler apparently tries first to optimize
106 * additions and subtractions, it generates slightly less than optimal
107 * code.
108 */
109 uint32_t slope_field =
110 (xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk) >> FICR_XOSC32MTRIM_SLOPE_Pos;
111 uint32_t slope_mask = FICR_XOSC32MTRIM_SLOPE_Msk >> FICR_XOSC32MTRIM_SLOPE_Pos;
112 uint32_t slope_sign = (slope_mask - (slope_mask >> 1));
113 int32_t slope_m = (int32_t)(slope_field ^ slope_sign) - (int32_t)slope_sign;
114 uint32_t offset_m =
115 (xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk) >> FICR_XOSC32MTRIM_OFFSET_Pos;
116 /* As specified in the nRF54L15 PS:
117 * CAPVALUE = (((CAPACITANCE-5.5)*(FICR->XOSC32MTRIM.SLOPE+791)) +
118 * FICR->XOSC32MTRIM.OFFSET<<2)>>8;
119 * where CAPACITANCE is the desired total load capacitance value in pF,
120 * holding any value between 4.0 pF and 17.0 pF in 0.25 pF steps.
121 */
122
123 /* NOTE 1: Requested HFXO internal capacitance in femto Faradas is used directly in formula
124 * to calculate INTCAP code. That is different than in case of LFXO.
125 *
126 * NOTE 2: PS formula uses piko Farads, the implementation of the formula uses femto Farads
127 * to avoid use of floating point data type.
128 */
129 uint32_t cap_val_femto_f = DT_PROP(HFXO_NODE, load_capacitance_femtofarad);
130
131 uint32_t mid_val_intcap = (((cap_val_femto_f - 5500UL) * (uint32_t)(slope_m + 791UL))
132 + (offset_m << 2UL) * 1000UL) >> 8UL;
133
134 /* Convert the calculated value to piko Farads */
135 uint32_t hfxo_intcap = mid_val_intcap / 1000;
136
137 /* Round based on fractional part */
138 if (mid_val_intcap % 1000 >= 500) {
139 hfxo_intcap++;
140 }
141
142 nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, hfxo_intcap);
143
144 #elif DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, external)
145 nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
146 #endif
147
148 if (IS_ENABLED(CONFIG_SOC_NRF_FORCE_CONSTLAT)) {
149 nrf_power_task_trigger(NRF_POWER, NRF_POWER_TASK_CONSTLAT);
150 }
151
152 if (IS_ENABLED(CONFIG_SOC_NRF54L_VREG_MAIN_DCDC)) {
153 nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MAIN, true);
154 }
155
156 if (IS_ENABLED(CONFIG_SOC_NRF54L_NORMAL_VOLTAGE_MODE)) {
157 nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_MEDIUM, false);
158 }
159
160 #if defined(CONFIG_ELV_GRTC_LFXO_ALLOWED)
161 nrf_regulators_elv_mode_allow_set(NRF_REGULATORS, NRF_REGULATORS_ELV_ELVGRTCLFXO_MASK);
162 #endif /* CONFIG_ELV_GRTC_LFXO_ALLOWED */
163 #endif /* NRF_APPLICATION */
164
165 return 0;
166 }
167
arch_busy_wait(uint32_t time_us)168 void arch_busy_wait(uint32_t time_us)
169 {
170 nrfx_coredep_delay_us(time_us);
171 }
172
173 SYS_INIT(nordicsemi_nrf54l_init, PRE_KERNEL_1, 0);
174
