1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for nxp_mcxn94x platform 10 * 11 * This module provides routines to initialize and support board-level 12 * hardware for the nxp_mcxn94x platform. 13 */ 14 15 #include <zephyr/kernel.h> 16 #include <zephyr/device.h> 17 #include <zephyr/init.h> 18 #include <soc.h> 19 20 #ifdef CONFIG_SOC_RESET_HOOK 21 soc_reset_hook(void)22void soc_reset_hook(void) 23 { 24 SystemInit(); 25 } 26 27 #endif 28 29 #define FLEXCOMM_CHECK_2(n) \ 30 BUILD_ASSERT((DT_NODE_HAS_COMPAT(n, nxp_lpuart) == 0) && \ 31 (DT_NODE_HAS_COMPAT(n, nxp_lpi2c) == 0), \ 32 "Do not enable SPI and UART/I2C on the same Flexcomm node"); 33 34 /* For SPI node enabled, check if UART or I2C is also enabled on the same parent Flexcomm node */ 35 #define FLEXCOMM_CHECK(n) DT_FOREACH_CHILD_STATUS_OKAY(DT_PARENT(n), FLEXCOMM_CHECK_2) 36 37 /* SPI cannot be exist with UART or I2C on the same FlexComm Interface 38 * Throw a build error if user is enabling SPI and UART/I2C on a Flexcomm node. 39 */ DT_FOREACH_STATUS_OKAY(nxp_lpspi,FLEXCOMM_CHECK)40DT_FOREACH_STATUS_OKAY(nxp_lpspi, FLEXCOMM_CHECK) 41 42 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MCXN947_CPU0) 43 44 /* This function is also called at deep sleep resume. */ 45 static int second_core_boot(void) 46 { 47 /* Boot source for Core 1 from flash */ 48 SYSCON->CPBOOT = ((uint32_t)(char *)DT_REG_ADDR(DT_CHOSEN(zephyr_code_cpu1_partition)) & 49 SYSCON_CPBOOT_CPBOOT_MASK); 50 51 uint32_t temp = SYSCON->CPUCTRL; 52 53 temp |= 0xc0c40000U; 54 SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK | SYSCON_CPUCTRL_CPU1CLKEN_MASK; 55 SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) & (~SYSCON_CPUCTRL_CPU1RSTEN_MASK); 56 57 return 0; 58 } 59 60 SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); 61 #endif 62
