| /Zephyr-Core-3.6.0/soc/arm/nuvoton_npcx/npcx9/ |
| D | soc.h | 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) argument
14 #define NPCX_PUPD_EN_OFFSET(n) (0x028 + n) argument
15 #define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n)) argument
16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) argument
19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010)) argument
20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010)) argument
21 #define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010)) argument
22 #define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010)) argument
23 #define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010)) argument
24 #define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010)) argument
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| /Zephyr-Core-3.6.0/soc/arm/nuvoton_npcx/npcx7/ |
| D | soc.h | 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) argument
14 #define NPCX_PUPD_EN_OFFSET(n) (0x028 + n) argument
15 #define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n)) argument
16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) argument
19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 2) + ((n < 5) ? 0 : 0x01e)) argument
20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 2) + ((n < 5) ? 0 : 0x01e)) argument
21 #define NPCX_WKMOD_OFFSET(n) (0x070 + n) argument
22 #define NPCX_WKPND_OFFSET(n) (0x00a + (n * 4) + ((n < 5) ? 0 : 0x010)) argument
23 #define NPCX_WKPCL_OFFSET(n) (0x00c + (n * 4) + ((n < 5) ? 0 : 0x010)) argument
24 #define NPCX_WKEN_OFFSET(n) (0x01e + (n * 2) + ((n < 5) ? 0 : 0x012)) argument
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| /Zephyr-Core-3.6.0/soc/arm/nuvoton_npcx/npcx4/ |
| D | soc.h | 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) argument
14 #define NPCX_PUPD_EN_OFFSET(n) (0x02b + n) argument
15 #define NPCX_LV_GPIO_CTL_OFFSET(n) (0x150 + n) argument
16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) argument
19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010)) argument
20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010)) argument
21 #define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010)) argument
22 #define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010)) argument
23 #define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010)) argument
24 #define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010)) argument
[all …]
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| /Zephyr-Core-3.6.0/drivers/gpio/ |
| D | gpio_nct38xx.h | 19 #define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n) * 8)) argument
20 #define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n) * 8)) argument
21 #define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n) * 8)) argument
22 #define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n) * 8)) argument
23 #define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n) * 8)) argument
24 #define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n) * 8)) argument
25 #define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n) * 8)) argument
26 #define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n) * 8)) argument
28 #define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n)) argument
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| D | gpio_bcm2711.c | 14 #define GPIO_REG_GROUP(n, cnt) (n / cnt) argument
15 #define GPIO_REG_SHIFT(n, cnt, bits) ((n % cnt) * bits) argument
17 #define GPFSEL(base, n) (base + 0x00 + 0x04 * n) argument
18 #define GPSET(base, n) (base + 0x1C + 0x04 * n) argument
19 #define GPCLR(base, n) (base + 0x28 + 0x04 * n) argument
20 #define GPLEV(base, n) (base + 0x34 + 0x04 * n) argument
21 #define GPEDS(base, n) (base + 0x40 + 0x04 * n) argument
22 #define GPREN(base, n) (base + 0x4C + 0x04 * n) argument
23 #define GPFEN(base, n) (base + 0x58 + 0x04 * n) argument
24 #define GPHEN(base, n) (base + 0x64 + 0x04 * n) argument
[all …]
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| D | gpio_nxp_s32.c | 504 #define GPIO_NXP_S32_RESERVED_PIN_MASK(n) \ argument
510 #define GPIO_NXP_S32_PORT_PIN_MASK(n) \ argument
516 #define GPIO_NXP_S32_REG_ADDR(n) \ argument
519 #define GPIO_NXP_S32_PORT_REG_ADDR(n) \ argument
523 #define GPIO_NXP_S32_EIRQ_NODE(n) \ argument
526 #define GPIO_NXP_S32_EIRQ_PIN_LINE(idx, n) \ argument
530 #define GPIO_NXP_S32_SET_EIRQ_INFO(n) \ argument
548 #define GPIO_NXP_S32_GET_EIRQ_INFO(n) \ argument
552 #define GPIO_NXP_S32_SET_EIRQ_INFO(n) argument
553 #define GPIO_NXP_S32_GET_EIRQ_INFO(n) argument
[all …]
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| /Zephyr-Core-3.6.0/soc/arm/atmel_sam0/common/ |
| D | atmel_sam0_dt.h | 18 #define MCLK_MASK_DT_INT_REG_ADDR(n) \ argument
25 #define ATMEL_SAM0_DT_INST_DMA_CELL(n, name, cell) \ argument
29 #define ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, name) \ argument
31 #define ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, name) \ argument
33 #define ATMEL_SAM0_DT_INST_DMA_CTLR(n, name) \ argument
40 #define ATMEL_SAM0_DT_SERCOM_CHECK(n, compat) \ argument
44 #define ATMEL_SAM0_DT_TCC_CHECK(n, compat) \ argument
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| D | adc_fixup_sam0.h | 85 # define ADC_FUSES_PREFIX(n) ADC_ argument
87 # define ADC_FUSES_PREFIX(n) UTIL_CAT(AD, UTIL_CAT(C, UTIL_CAT(n, _))) argument
91 # define ADC_SAM0_BIASCOMP(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASCOMP) argument
93 # define ADC_SAM0_BIASCOMP(n) 0 argument
97 # define ADC_SAM0_BIASR2R(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASR2R) argument
99 # define ADC_SAM0_BIASR2R(n) 0 argument
103 # define ADC_SAM0_BIASREFBUF(n) ADC_SAM0_CALIB(ADC_FUSES_PREFIX(n), BIASREFBUF) argument
105 # define ADC_SAM0_BIASREFBUF(n) 0 argument
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| /Zephyr-Core-3.6.0/drivers/memc/ |
| D | memc_nxp_s32_qspi.c | 79 #define QSPI_DATA_CFG(n) \ argument
88 #define QSPI_ADDR_CFG(n) \ argument
94 #define QSPI_BYTES_SWAP_ADDR(n) \ argument
98 #define QSPI_SAMPLE_DELAY(n) \ argument
103 #define QSPI_SAMPLE_PHASE(n) \ argument
108 #define QSPI_AHB_BUFFERS(n) \ argument
115 #define QSPI_DLL_CFG(n, side, side_upper) \ argument
131 #define QSPI_READ_MODE(n, side, side_upper) \ argument
134 #define QSPI_IDLE_SIGNAL_DRIVE(n, side, side_upper) \ argument
147 #define QSPI_PORT_SIZE(n, side_upper) \ argument
[all …]
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| /Zephyr-Core-3.6.0/drivers/interrupt_controller/ |
| D | intc_gic_common_priv.h | 25 #define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) argument
26 #define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) argument
27 #define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) argument
28 #define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) argument
29 #define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) argument
30 #define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) argument
31 #define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) argument
32 #define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) argument
33 #define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) argument
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| D | intc_eirq_nxp_s32.c | 130 #define EIRQ_NXP_S32_CALLBACK(line, n) \ argument
136 #define EIRQ_NXP_S32_CHANNEL_CONFIG(idx, n) \ argument
148 #define EIRQ_NXP_S32_CHANNELS_CONFIG(n) \ argument
153 #define EIRQ_NXP_S32_INSTANCE_CONFIG(n) \ argument
159 #define EIRQ_NXP_S32_COMBINE_CONFIG(n) \ argument
166 #define EIRQ_NXP_S32_CONFIG(n) \ argument
174 #define EIRQ_NXP_S32_IRQ_NAME(idx, n) \ argument
179 #define _EIRQ_NXP_S32_IRQ_CONFIG(idx, n) \ argument
189 #define EIRQ_NXP_S32_IRQ_CONFIG(n) \ argument
192 #define EIRQ_NXP_S32_HW_INSTANCE_CHECK(i, n) \ argument
[all …]
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| /Zephyr-Core-3.6.0/soc/arm/cypress/common/ |
| D | cypress_psoc6_dt.h | 65 #define CY_PSOC6_DT_INST_NVIC_INSTALL(n, isr) \ argument
68 #define CY_PSOC6_NVIC_MUX_IRQN(n) DT_IRQN(DT_INST_PHANDLE_BY_IDX(n,\ argument
71 #define CY_PSOC6_NVIC_MUX_IRQ_PRIO(n) DT_IRQ(DT_INST_PHANDLE_BY_IDX(n,\ argument
81 #define CY_PSOC6_NVIC_MUX_MAP(n) Cy_SysInt_SetInterruptSource( \ argument
91 #define CY_PSOC6_DT_INST_NVIC_INSTALL(n, isr) CY_PSOC6_IRQ_CONFIG(n, isr) argument
92 #define CY_PSOC6_NVIC_MUX_IRQN(n) DT_INST_IRQN(n) argument
93 #define CY_PSOC6_NVIC_MUX_IRQ_PRIO(n) DT_INST_IRQ(n, priority) argument
94 #define CY_PSOC6_NVIC_MUX_MAP(n) argument
97 #define CY_PSOC6_IRQ_CONFIG(n, isr) \ argument
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| /Zephyr-Core-3.6.0/drivers/misc/nxp_s32_emios/ |
| D | nxp_s32_emios.c | 46 #define NXP_S32_EMIOS_INSTANCE_CHECK(idx, n) \ argument
49 #define NXP_S32_EMIOS_GET_INSTANCE(n) \ argument
52 #define NXP_S32_EMIOS_GENERATE_GLOBAL_CONFIG(n) \ argument
77 #define NXP_S32_EMIOS_GENERATE_MASTER_BUS_CONFIG(n) \ argument
85 #define NXP_S32_EMIOS_GENERATE_CONFIG(n) \ argument
103 #define NXP_S32_EMIOS_INTERRUPT_DEFINE(n) \ argument
116 #define NXP_S32_EMIOS_INTERRUPT_CONFIG(n) \ argument
122 #define NXP_S32_EMIOS_INIT_DEVICE(n) \ argument
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| /Zephyr-Core-3.6.0/drivers/ethernet/ |
| D | eth_nxp_s32_gmac.c | 673 #define ETH_NXP_S32_FIXED_LINK_NODE(n) \ argument
676 #define ETH_NXP_S32_IS_FIXED_LINK(n) \ argument
679 #define ETH_NXP_S32_FIXED_LINK_SPEED(n) \ argument
682 #define ETH_NXP_S32_FIXED_LINK_FULL_DUPLEX(n) \ argument
685 #define ETH_NXP_S32_MAC_SPEED(n) \ argument
690 #define ETH_NXP_S32_MAC_DUPLEX(n) \ argument
696 #define ETH_NXP_S32_MAC_MII(n) \ argument
699 #define ETH_NXP_S32_IRQ_INIT(n, name) \ argument
707 #define ETH_NXP_S32_INIT_CONFIG(n) \ argument
726 #define ETH_NXP_S32_RX_CALLBACK(n) \ argument
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| D | eth_mcux.c | 1406 #define ETH_MCUX_IRQ_INIT(n, name) \ argument
1416 #define ETH_MCUX_IRQ(n, name) \ argument
1422 #define PTP_INST_NODEID(n) DT_INST_CHILD(n, ptp) argument
1424 #define ETH_MCUX_IRQ_PTP_INIT(n) \ argument
1434 #define ETH_MCUX_IRQ_PTP(n) \ argument
1439 #define ETH_MCUX_PTP_FRAMEINFO_ARRAY(n) \ argument
1443 #define ETH_MCUX_PTP_FRAMEINFO(n) \ argument
1446 #define ETH_MCUX_IRQ_PTP(n) argument
1448 #define ETH_MCUX_PTP_FRAMEINFO_ARRAY(n) argument
1450 #define ETH_MCUX_PTP_FRAMEINFO(n) \ argument
[all …]
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| D | eth_nxp_s32_netc_psi.c | 231 #define NETC_VSI_RX_MSG_BUF(node, prop, idx, n) \ argument
239 #define NETC_VSI_RX_MSG_BUF_ARRAY(node, prop, idx, n) \ argument
243 #define NETC_SWITCH_PORT_CFG(_, n) \ argument
254 #define PHY_NODE(n) DT_INST_PHANDLE(n, phy_handle) argument
255 #define INIT_VSIS(n) DT_INST_NODE_HAS_PROP(n, vsis) argument
257 #define NETC_PSI_INSTANCE_DEFINE(n) \ argument
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| /Zephyr-Core-3.6.0/drivers/spi/ |
| D | spi_nxp_s32.c | 614 #define SPI_NXP_S32_HW_INSTANCE_CHECK(i, n) \ argument
617 #define SPI_NXP_S32_HW_INSTANCE(n) \ argument
620 #define SPI_NXP_S32_NUM_CS(n) DT_INST_PROP(n, num_cs) argument
621 #define SPI_NXP_S32_IS_MASTER(n) !DT_INST_PROP(n, slave) argument
624 #define SPI_NXP_S32_SET_SLAVE(n) .SlaveMode = DT_INST_PROP(n, slave), argument
626 #define SPI_NXP_S32_SET_SLAVE(n) argument
631 #define SPI_NXP_S32_CONFIG_INTERRUPT_FUNC(n) \ argument
634 #define SPI_NXP_S32_INTERRUPT_DEFINE(n) \ argument
643 #define SPI_NXP_S32_CONFIG_CALLBACK_FUNC(n) \ argument
646 #define SPI_NXP_S32_CALLBACK_DEFINE(n) \ argument
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| /Zephyr-Core-3.6.0/drivers/mbox/ |
| D | mbox_nxp_s32_mru.c | 188 #define MRU_BASE(n) ((RTU_MRU_Type *)DT_INST_REG_ADDR(n)) argument
189 #define MRU_RX_CHANNELS(n) DT_INST_PROP_OR(n, rx_channels, 0) argument
190 #define MRU_MBOX_ADDR(n, ch, mb) \ argument
193 #define MRU_HW_INSTANCE_CHECK(i, n) \ argument
196 #define MRU_HW_INSTANCE(n) \ argument
199 #define MRU_INIT_IRQ_FUNC(n) \ argument
210 #define MRU_CH_RX_CFG(i, n) \ argument
225 #define MRU_CH_RX_LINK_CFG_MBOX(i, n, chan, intgroup) \ argument
230 #define MRU_CH_RX_LINK_CFG(i, n) \ argument
236 #define MRU_CH_CFG(i, n) \ argument
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| /Zephyr-Core-3.6.0/soc/arm/arm/mps3/ |
| D | soc.c | 13 #define FPGAIO_NODE(n) DT_INST(n, arm_mps3_fpgaio_gpio) argument
14 #define FPGAIO_INIT(n) \ argument
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| /Zephyr-Core-3.6.0/drivers/i2c/ |
| D | i2c_dw.c | 1121 #define PINCTRL_DW_DEFINE(n) PINCTRL_DT_INST_DEFINE(n) argument
1122 #define PINCTRL_DW_CONFIG(n) .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), argument
1124 #define PINCTRL_DW_DEFINE(n) argument
1125 #define PINCTRL_DW_CONFIG(n) argument
1129 #define RESET_DW_CONFIG(n) \ argument
1133 #define RESET_DW_CONFIG(n) argument
1136 #define I2C_DW_INIT_PCIE0(n) argument
1137 #define I2C_DW_INIT_PCIE1(n) DEVICE_PCIE_INST_INIT(n, pcie), argument
1138 #define I2C_DW_INIT_PCIE(n) \ argument
1141 #define I2C_DEFINE_PCIE0(n) argument
[all …]
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| /Zephyr-Core-3.6.0/include/zephyr/math/ |
| D | ilog2.h | 39 #define ilog2_compile_time_const_u32(n) \ argument
93 #define ilog2(n) \ argument
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| /Zephyr-Core-3.6.0/lib/utils/ |
| D | rb.c | 12 #define CHECK(n) /**/ argument
21 static struct rbnode *get_child(struct rbnode *n, uint8_t side) in get_child()
34 static void set_child(struct rbnode *n, uint8_t side, void *val) in set_child()
47 static enum rb_color get_color(struct rbnode *n) in get_color()
53 static bool is_black(struct rbnode *n) in is_black()
58 static bool is_red(struct rbnode *n) in is_red()
63 static void set_color(struct rbnode *n, enum rb_color color) in set_color()
102 struct rbnode *n; in z_rb_get_minmax() local
272 struct rbnode *n = stack[stacksz - 1]; in fix_missing_black() local
519 struct rbnode *n = tree->root; in rb_contains() local
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| /Zephyr-Core-3.6.0/lib/libc/minimal/source/string/ |
| D | string.c | 42 char *strncpy(char *ZRESTRICT d, const char *ZRESTRICT s, size_t n) in strncpy()
109 size_t n = 0; in strlen() local
143 int strncmp(const char *s1, const char *s2, size_t n) in strncmp()
200 size_t n) in strncat()
220 int memcmp(const void *m1, const void *m2, size_t n) in memcmp()
244 void *memmove(void *d, const void *s, size_t n) in memmove()
279 void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n) in memcpy()
333 void *memset(void *buf, int c, size_t n) in memset()
385 void *memchr(const void *s, int c, size_t n) in memchr()
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| /Zephyr-Core-3.6.0/drivers/serial/ |
| D | uart_pl011.c | 370 #define PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n); argument
371 #define PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), argument
373 #define PINCTRL_DEFINE(n) argument
374 #define PINCTRL_INIT(n) argument
377 #define PL011_GET_COMPAT_QUIRK_NONE(n) NULL argument
379 #define PL011_GET_COMPAT_CLK_QUIRK_0(n) \ argument
384 #define PL011_GET_COMPAT_PWR_QUIRK_0(n) \ argument
402 #define PL011_IRQ_CONFIG_FUNC_BODY(n, prop, i) \ argument
412 #define PL011_CONFIG_PORT(n) \ argument
428 #define PL011_CONFIG_PORT(n) \ argument
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| /Zephyr-Core-3.6.0/include/zephyr/sys/ |
| D | hash_function.h | 58 static inline uint32_t sys_hash32_identity(const void *str, size_t n) in sys_hash32_identity()
119 static inline uint32_t sys_hash32(const void *str, size_t n) in sys_hash32()
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