1 /*
2 * Copyright (c) 2017, I-SENSE group of ICCS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * I2C Driver for: STM32F1, STM32F2, STM32F4 and STM32L1
8 *
9 */
10
11 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
12 #include <zephyr/drivers/clock_control.h>
13 #include <zephyr/sys/util.h>
14 #include <zephyr/kernel.h>
15 #include <soc.h>
16 #include <stm32_ll_i2c.h>
17 #include <errno.h>
18 #include <zephyr/drivers/i2c.h>
19 #include "i2c_ll_stm32.h"
20
21 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(i2c_ll_stm32_v1);
24
25 #include "i2c-priv.h"
26
27 #define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500
28
29 #define STM32_I2C_TIMEOUT_USEC 1000
30 #define I2C_REQUEST_WRITE 0x00
31 #define I2C_REQUEST_READ 0x01
32 #define HEADER 0xF0
33
stm32_i2c_generate_start_condition(I2C_TypeDef * i2c)34 static void stm32_i2c_generate_start_condition(I2C_TypeDef *i2c)
35 {
36 uint16_t cr1 = LL_I2C_ReadReg(i2c, CR1);
37
38 if (cr1 & I2C_CR1_STOP) {
39 LOG_DBG("%s: START while STOP active!", __func__);
40 LL_I2C_WriteReg(i2c, CR1, cr1 & ~I2C_CR1_STOP);
41 }
42
43 LL_I2C_GenerateStartCondition(i2c);
44 }
45
46 #ifdef CONFIG_I2C_STM32_INTERRUPT
47
stm32_i2c_disable_transfer_interrupts(const struct device * dev)48 static void stm32_i2c_disable_transfer_interrupts(const struct device *dev)
49 {
50 const struct i2c_stm32_config *cfg = dev->config;
51 struct i2c_stm32_data *data = dev->data;
52 I2C_TypeDef *i2c = cfg->i2c;
53
54 LL_I2C_DisableIT_TX(i2c);
55 LL_I2C_DisableIT_RX(i2c);
56 LL_I2C_DisableIT_EVT(i2c);
57 LL_I2C_DisableIT_BUF(i2c);
58
59 if (!data->smbalert_active) {
60 LL_I2C_DisableIT_ERR(i2c);
61 }
62 }
63
stm32_i2c_enable_transfer_interrupts(const struct device * dev)64 static void stm32_i2c_enable_transfer_interrupts(const struct device *dev)
65 {
66 const struct i2c_stm32_config *cfg = dev->config;
67 I2C_TypeDef *i2c = cfg->i2c;
68
69 LL_I2C_EnableIT_ERR(i2c);
70 LL_I2C_EnableIT_EVT(i2c);
71 LL_I2C_EnableIT_BUF(i2c);
72 }
73
74 #endif /* CONFIG_I2C_STM32_INTERRUPT */
75
stm32_i2c_reset(const struct device * dev)76 static void stm32_i2c_reset(const struct device *dev)
77 {
78 const struct i2c_stm32_config *cfg = dev->config;
79 I2C_TypeDef *i2c = cfg->i2c;
80 uint16_t cr1, cr2, oar1, oar2, trise, ccr;
81 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
82 uint16_t fltr;
83 #endif
84
85 /* disable i2c and disable IRQ's */
86 LL_I2C_Disable(i2c);
87 #ifdef CONFIG_I2C_STM32_INTERRUPT
88 stm32_i2c_disable_transfer_interrupts(dev);
89 #endif
90
91 /* save all important registers before reset */
92 cr1 = LL_I2C_ReadReg(i2c, CR1);
93 cr2 = LL_I2C_ReadReg(i2c, CR2);
94 oar1 = LL_I2C_ReadReg(i2c, OAR1);
95 oar2 = LL_I2C_ReadReg(i2c, OAR2);
96 ccr = LL_I2C_ReadReg(i2c, CCR);
97 trise = LL_I2C_ReadReg(i2c, TRISE);
98 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
99 fltr = LL_I2C_ReadReg(i2c, FLTR);
100 #endif
101
102 /* reset i2c hardware */
103 LL_I2C_EnableReset(i2c);
104 LL_I2C_DisableReset(i2c);
105
106 /* restore all important registers after reset */
107 LL_I2C_WriteReg(i2c, CR1, cr1);
108 LL_I2C_WriteReg(i2c, CR2, cr2);
109
110 /* bit 14 of OAR1 must always be 1 */
111 oar1 |= (1 << 14);
112 LL_I2C_WriteReg(i2c, OAR1, oar1);
113 LL_I2C_WriteReg(i2c, OAR2, oar2);
114 LL_I2C_WriteReg(i2c, CCR, ccr);
115 LL_I2C_WriteReg(i2c, TRISE, trise);
116 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
117 LL_I2C_WriteReg(i2c, FLTR, fltr);
118 #endif
119 }
120
121
stm32_i2c_master_finish(const struct device * dev)122 static void stm32_i2c_master_finish(const struct device *dev)
123 {
124 const struct i2c_stm32_config *cfg = dev->config;
125 struct i2c_stm32_data *data = dev->data;
126 I2C_TypeDef *i2c = cfg->i2c;
127
128 #ifdef CONFIG_I2C_STM32_INTERRUPT
129 stm32_i2c_disable_transfer_interrupts(dev);
130 #endif
131
132 #if defined(CONFIG_I2C_TARGET)
133 data->master_active = false;
134 if (!data->slave_attached && !data->smbalert_active) {
135 LL_I2C_Disable(i2c);
136 } else {
137 stm32_i2c_enable_transfer_interrupts(dev);
138 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
139 }
140 #else
141 if (!data->smbalert_active) {
142 LL_I2C_Disable(i2c);
143 }
144 #endif
145 }
146
msg_init(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave,uint32_t transfer)147 static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
148 uint8_t *next_msg_flags, uint16_t slave,
149 uint32_t transfer)
150 {
151 const struct i2c_stm32_config *cfg = dev->config;
152 struct i2c_stm32_data *data = dev->data;
153 I2C_TypeDef *i2c = cfg->i2c;
154
155 ARG_UNUSED(next_msg_flags);
156
157 #ifdef CONFIG_I2C_STM32_INTERRUPT
158 k_sem_reset(&data->device_sync_sem);
159 #endif
160
161 data->current.len = msg->len;
162 data->current.buf = msg->buf;
163 data->current.flags = msg->flags;
164 data->current.is_restart = 0U;
165 data->current.is_write = (transfer == I2C_REQUEST_WRITE);
166 data->current.is_arlo = 0U;
167 data->current.is_err = 0U;
168 data->current.is_nack = 0U;
169 data->current.msg = msg;
170 #if defined(CONFIG_I2C_TARGET)
171 data->master_active = true;
172 #endif
173 data->slave_address = slave;
174
175 LL_I2C_Enable(i2c);
176
177 LL_I2C_DisableBitPOS(i2c);
178 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
179 if (msg->flags & I2C_MSG_RESTART) {
180 stm32_i2c_generate_start_condition(i2c);
181 }
182 }
183
msg_end(const struct device * dev,uint8_t * next_msg_flags,const char * funcname)184 static int32_t msg_end(const struct device *dev, uint8_t *next_msg_flags,
185 const char *funcname)
186 {
187 struct i2c_stm32_data *data = dev->data;
188
189 if (data->current.is_nack || data->current.is_err ||
190 data->current.is_arlo) {
191 goto error;
192 }
193
194 if (!next_msg_flags) {
195 stm32_i2c_master_finish(dev);
196 }
197
198 return 0;
199
200 error:
201 if (data->current.is_arlo) {
202 LOG_DBG("%s: ARLO %d", funcname,
203 data->current.is_arlo);
204 data->current.is_arlo = 0U;
205 }
206
207 if (data->current.is_nack) {
208 LOG_DBG("%s: NACK", funcname);
209 data->current.is_nack = 0U;
210 }
211
212 if (data->current.is_err) {
213 LOG_DBG("%s: ERR %d", funcname,
214 data->current.is_err);
215 data->current.is_err = 0U;
216 }
217 stm32_i2c_master_finish(dev);
218
219 return -EIO;
220 }
221
222 #ifdef CONFIG_I2C_STM32_INTERRUPT
223
stm32_i2c_master_mode_end(const struct device * dev)224 static void stm32_i2c_master_mode_end(const struct device *dev)
225 {
226 struct i2c_stm32_data *data = dev->data;
227
228 k_sem_give(&data->device_sync_sem);
229 }
230
handle_sb(const struct device * dev)231 static inline void handle_sb(const struct device *dev)
232 {
233 const struct i2c_stm32_config *cfg = dev->config;
234 struct i2c_stm32_data *data = dev->data;
235 I2C_TypeDef *i2c = cfg->i2c;
236
237 uint16_t saddr = data->slave_address;
238 uint8_t slave;
239
240 if (I2C_ADDR_10_BITS & data->dev_config) {
241 slave = (((saddr & 0x0300) >> 7) & 0xFF);
242 uint8_t header = slave | HEADER;
243
244 if (data->current.is_restart == 0U) {
245 data->current.is_restart = 1U;
246 } else {
247 header |= I2C_REQUEST_READ;
248 data->current.is_restart = 0U;
249 }
250 LL_I2C_TransmitData8(i2c, header);
251
252 return;
253 }
254 slave = (saddr << 1) & 0xFF;
255 if (data->current.is_write) {
256 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
257 } else {
258 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
259 if (data->current.len == 2) {
260 LL_I2C_EnableBitPOS(i2c);
261 }
262 }
263 }
264
handle_addr(const struct device * dev)265 static inline void handle_addr(const struct device *dev)
266 {
267 const struct i2c_stm32_config *cfg = dev->config;
268 struct i2c_stm32_data *data = dev->data;
269 I2C_TypeDef *i2c = cfg->i2c;
270
271 if (I2C_ADDR_10_BITS & data->dev_config) {
272 if (!data->current.is_write && data->current.is_restart) {
273 data->current.is_restart = 0U;
274 LL_I2C_ClearFlag_ADDR(i2c);
275 stm32_i2c_generate_start_condition(i2c);
276
277 return;
278 }
279 }
280
281 if (data->current.is_write) {
282 LL_I2C_ClearFlag_ADDR(i2c);
283 return;
284 }
285 /* according to STM32F1 errata we need to handle these corner cases in
286 * specific way.
287 * Please ref to STM32F10xxC/D/E I2C peripheral Errata sheet 2.14.1
288 */
289 if (data->current.len == 0U && IS_ENABLED(CONFIG_SOC_SERIES_STM32F1X)) {
290 LL_I2C_GenerateStopCondition(i2c);
291 } else if (data->current.len == 1U) {
292 /* Single byte reception: enable NACK and clear POS */
293 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
294 #ifdef CONFIG_SOC_SERIES_STM32F1X
295 LL_I2C_ClearFlag_ADDR(i2c);
296 LL_I2C_GenerateStopCondition(i2c);
297 #endif
298 } else if (data->current.len == 2U) {
299 #ifdef CONFIG_SOC_SERIES_STM32F1X
300 LL_I2C_ClearFlag_ADDR(i2c);
301 #endif
302 /* 2-byte reception: enable NACK and set POS */
303 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
304 LL_I2C_EnableBitPOS(i2c);
305 }
306 LL_I2C_ClearFlag_ADDR(i2c);
307 }
308
handle_txe(const struct device * dev)309 static inline void handle_txe(const struct device *dev)
310 {
311 const struct i2c_stm32_config *cfg = dev->config;
312 struct i2c_stm32_data *data = dev->data;
313 I2C_TypeDef *i2c = cfg->i2c;
314
315 if (data->current.len) {
316 data->current.len--;
317 if (data->current.len == 0U) {
318 /*
319 * This is the last byte to transmit disable Buffer
320 * interrupt and wait for a BTF interrupt
321 */
322 LL_I2C_DisableIT_BUF(i2c);
323 }
324 LL_I2C_TransmitData8(i2c, *data->current.buf);
325 data->current.buf++;
326 } else {
327 if (data->current.flags & I2C_MSG_STOP) {
328 LL_I2C_GenerateStopCondition(i2c);
329 }
330 if (LL_I2C_IsActiveFlag_BTF(i2c)) {
331 /* Read DR to clear BTF flag */
332 LL_I2C_ReceiveData8(i2c);
333 }
334
335 k_sem_give(&data->device_sync_sem);
336 }
337 }
338
handle_rxne(const struct device * dev)339 static inline void handle_rxne(const struct device *dev)
340 {
341 const struct i2c_stm32_config *cfg = dev->config;
342 struct i2c_stm32_data *data = dev->data;
343 I2C_TypeDef *i2c = cfg->i2c;
344
345 if (data->current.len > 0) {
346 switch (data->current.len) {
347 case 1:
348 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
349 LL_I2C_DisableBitPOS(i2c);
350 /* Single byte reception */
351 if (data->current.flags & I2C_MSG_STOP) {
352 LL_I2C_GenerateStopCondition(i2c);
353 }
354 LL_I2C_DisableIT_BUF(i2c);
355 data->current.len--;
356 *data->current.buf = LL_I2C_ReceiveData8(i2c);
357 data->current.buf++;
358
359 k_sem_give(&data->device_sync_sem);
360 break;
361 case 2:
362 /*
363 * 2-byte reception for N > 3 has already set the NACK
364 * bit, and must not set the POS bit. See pg. 854 in
365 * the F4 reference manual (RM0090).
366 */
367 if (data->current.msg->len > 2) {
368 break;
369 }
370 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
371 LL_I2C_EnableBitPOS(i2c);
372 __fallthrough;
373 case 3:
374 /*
375 * 2-byte, 3-byte reception and for N-2, N-1,
376 * N when N > 3
377 */
378 LL_I2C_DisableIT_BUF(i2c);
379 break;
380 default:
381 /* N byte reception when N > 3 */
382 data->current.len--;
383 *data->current.buf = LL_I2C_ReceiveData8(i2c);
384 data->current.buf++;
385 }
386 } else {
387
388 if (data->current.flags & I2C_MSG_STOP) {
389 LL_I2C_GenerateStopCondition(i2c);
390 }
391 k_sem_give(&data->device_sync_sem);
392 }
393 }
394
handle_btf(const struct device * dev)395 static inline void handle_btf(const struct device *dev)
396 {
397 const struct i2c_stm32_config *cfg = dev->config;
398 struct i2c_stm32_data *data = dev->data;
399 I2C_TypeDef *i2c = cfg->i2c;
400
401 if (data->current.is_write) {
402 handle_txe(dev);
403 } else {
404 uint32_t counter = 0U;
405
406 switch (data->current.len) {
407 case 2:
408 /*
409 * Stop condition must be generated before reading the
410 * last two bytes.
411 */
412 if (data->current.flags & I2C_MSG_STOP) {
413 LL_I2C_GenerateStopCondition(i2c);
414 }
415
416 for (counter = 2U; counter > 0; counter--) {
417 data->current.len--;
418 *data->current.buf = LL_I2C_ReceiveData8(i2c);
419 data->current.buf++;
420 }
421 k_sem_give(&data->device_sync_sem);
422 break;
423 case 3:
424 /* Set NACK before reading N-2 byte*/
425 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
426 data->current.len--;
427 *data->current.buf = LL_I2C_ReceiveData8(i2c);
428 data->current.buf++;
429 break;
430 default:
431 handle_rxne(dev);
432 }
433 }
434 }
435
436
437 #if defined(CONFIG_I2C_TARGET)
stm32_i2c_slave_event(const struct device * dev)438 static void stm32_i2c_slave_event(const struct device *dev)
439 {
440 const struct i2c_stm32_config *cfg = dev->config;
441 struct i2c_stm32_data *data = dev->data;
442 I2C_TypeDef *i2c = cfg->i2c;
443 const struct i2c_target_callbacks *slave_cb =
444 data->slave_cfg->callbacks;
445
446 if (LL_I2C_IsActiveFlag_TXE(i2c) && LL_I2C_IsActiveFlag_BTF(i2c)) {
447 uint8_t val;
448 slave_cb->read_processed(data->slave_cfg, &val);
449 LL_I2C_TransmitData8(i2c, val);
450 return;
451 }
452
453 if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
454 uint8_t val = LL_I2C_ReceiveData8(i2c);
455 if (slave_cb->write_received(data->slave_cfg, val)) {
456 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
457 }
458 return;
459 }
460
461 if (LL_I2C_IsActiveFlag_AF(i2c)) {
462 LL_I2C_ClearFlag_AF(i2c);
463 }
464
465 if (LL_I2C_IsActiveFlag_STOP(i2c)) {
466 LL_I2C_ClearFlag_STOP(i2c);
467 slave_cb->stop(data->slave_cfg);
468 /* Prepare to ACK next transmissions address byte */
469 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
470 }
471
472 if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
473 uint32_t dir = LL_I2C_GetTransferDirection(i2c);
474 if (dir == LL_I2C_DIRECTION_READ) {
475 slave_cb->write_requested(data->slave_cfg);
476 LL_I2C_EnableIT_RX(i2c);
477 } else {
478 uint8_t val;
479 slave_cb->read_requested(data->slave_cfg, &val);
480 LL_I2C_TransmitData8(i2c, val);
481 LL_I2C_EnableIT_TX(i2c);
482 }
483
484 stm32_i2c_enable_transfer_interrupts(dev);
485 }
486 }
487
488 /* Attach and start I2C as slave */
i2c_stm32_target_register(const struct device * dev,struct i2c_target_config * config)489 int i2c_stm32_target_register(const struct device *dev, struct i2c_target_config *config)
490 {
491 const struct i2c_stm32_config *cfg = dev->config;
492 struct i2c_stm32_data *data = dev->data;
493 I2C_TypeDef *i2c = cfg->i2c;
494 uint32_t bitrate_cfg;
495 int ret;
496
497 if (!config) {
498 return -EINVAL;
499 }
500
501 if (data->slave_attached) {
502 return -EBUSY;
503 }
504
505 if (data->master_active) {
506 return -EBUSY;
507 }
508
509 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
510
511 ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
512 if (ret < 0) {
513 LOG_ERR("i2c: failure initializing");
514 return ret;
515 }
516
517 data->slave_cfg = config;
518
519 LL_I2C_Enable(i2c);
520
521 if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
522 return -ENOTSUP;
523 }
524 LL_I2C_SetOwnAddress1(i2c, config->address << 1U, LL_I2C_OWNADDRESS1_7BIT);
525 data->slave_attached = true;
526
527 LOG_DBG("i2c: target registered");
528
529 stm32_i2c_enable_transfer_interrupts(dev);
530 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
531
532 return 0;
533 }
534
i2c_stm32_target_unregister(const struct device * dev,struct i2c_target_config * config)535 int i2c_stm32_target_unregister(const struct device *dev, struct i2c_target_config *config)
536 {
537 const struct i2c_stm32_config *cfg = dev->config;
538 struct i2c_stm32_data *data = dev->data;
539 I2C_TypeDef *i2c = cfg->i2c;
540
541 if (!data->slave_attached) {
542 return -EINVAL;
543 }
544
545 if (data->master_active) {
546 return -EBUSY;
547 }
548
549 stm32_i2c_disable_transfer_interrupts(dev);
550
551 LL_I2C_ClearFlag_AF(i2c);
552 LL_I2C_ClearFlag_STOP(i2c);
553 LL_I2C_ClearFlag_ADDR(i2c);
554
555 if (!data->smbalert_active) {
556 LL_I2C_Disable(i2c);
557 }
558
559 data->slave_attached = false;
560
561 LOG_DBG("i2c: slave unregistered");
562
563 return 0;
564 }
565 #endif /* defined(CONFIG_I2C_TARGET) */
566
stm32_i2c_event_isr(void * arg)567 void stm32_i2c_event_isr(void *arg)
568 {
569 const struct device *dev = (const struct device *)arg;
570 const struct i2c_stm32_config *cfg = dev->config;
571 struct i2c_stm32_data *data = dev->data;
572 I2C_TypeDef *i2c = cfg->i2c;
573
574 #if defined(CONFIG_I2C_TARGET)
575 if (data->slave_attached && !data->master_active) {
576 stm32_i2c_slave_event(dev);
577 return;
578 }
579 #endif
580
581 if (LL_I2C_IsActiveFlag_SB(i2c)) {
582 handle_sb(dev);
583 } else if (LL_I2C_IsActiveFlag_ADD10(i2c)) {
584 LL_I2C_TransmitData8(i2c, data->slave_address);
585 } else if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
586 handle_addr(dev);
587 } else if (LL_I2C_IsActiveFlag_BTF(i2c)) {
588 handle_btf(dev);
589 } else if (LL_I2C_IsActiveFlag_TXE(i2c) && data->current.is_write) {
590 handle_txe(dev);
591 } else if (LL_I2C_IsActiveFlag_RXNE(i2c) && !data->current.is_write) {
592 handle_rxne(dev);
593 }
594 }
595
stm32_i2c_error_isr(void * arg)596 void stm32_i2c_error_isr(void *arg)
597 {
598 const struct device *dev = (const struct device *)arg;
599 const struct i2c_stm32_config *cfg = dev->config;
600 struct i2c_stm32_data *data = dev->data;
601 I2C_TypeDef *i2c = cfg->i2c;
602
603 #if defined(CONFIG_I2C_TARGET)
604 if (data->slave_attached && !data->master_active) {
605 /* No need for a slave error function right now. */
606 return;
607 }
608 #endif
609
610 if (LL_I2C_IsActiveFlag_AF(i2c)) {
611 LL_I2C_ClearFlag_AF(i2c);
612 LL_I2C_GenerateStopCondition(i2c);
613 data->current.is_nack = 1U;
614 goto end;
615 }
616 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
617 LL_I2C_ClearFlag_ARLO(i2c);
618 data->current.is_arlo = 1U;
619 goto end;
620 }
621
622 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
623 LL_I2C_ClearFlag_BERR(i2c);
624 data->current.is_err = 1U;
625 goto end;
626 }
627
628 #if defined(CONFIG_SMBUS_STM32_SMBALERT)
629 if (LL_I2C_IsActiveSMBusFlag_ALERT(i2c)) {
630 LL_I2C_ClearSMBusFlag_ALERT(i2c);
631 if (data->smbalert_cb_func != NULL) {
632 data->smbalert_cb_func(data->smbalert_cb_dev);
633 }
634 goto end;
635 }
636 #endif
637 return;
638 end:
639 stm32_i2c_master_mode_end(dev);
640 }
641
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)642 static int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
643 uint8_t *next_msg_flags, uint16_t saddr)
644 {
645 struct i2c_stm32_data *data = dev->data;
646
647 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
648
649 stm32_i2c_enable_transfer_interrupts(dev);
650
651 if (k_sem_take(&data->device_sync_sem,
652 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
653 LOG_DBG("%s: WRITE timeout", __func__);
654 stm32_i2c_reset(dev);
655 return -EIO;
656 }
657
658 return msg_end(dev, next_msg_flags, __func__);
659 }
660
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)661 static int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
662 uint8_t *next_msg_flags, uint16_t saddr)
663 {
664 const struct i2c_stm32_config *cfg = dev->config;
665 struct i2c_stm32_data *data = dev->data;
666 I2C_TypeDef *i2c = cfg->i2c;
667
668 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
669
670 stm32_i2c_enable_transfer_interrupts(dev);
671 LL_I2C_EnableIT_RX(i2c);
672
673 if (k_sem_take(&data->device_sync_sem,
674 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
675 LOG_DBG("%s: READ timeout", __func__);
676 stm32_i2c_reset(dev);
677 return -EIO;
678 }
679
680 return msg_end(dev, next_msg_flags, __func__);
681 }
682
683 #else /* CONFIG_I2C_STM32_INTERRUPT */
684
check_errors(const struct device * dev,const char * funcname)685 static inline int check_errors(const struct device *dev, const char *funcname)
686 {
687 const struct i2c_stm32_config *cfg = dev->config;
688 struct i2c_stm32_data *data = dev->data;
689 I2C_TypeDef *i2c = cfg->i2c;
690
691 if (LL_I2C_IsActiveFlag_AF(i2c)) {
692 LL_I2C_ClearFlag_AF(i2c);
693 LOG_DBG("%s: NACK", funcname);
694 data->current.is_nack = 1U;
695 goto error;
696 }
697
698 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
699 LL_I2C_ClearFlag_ARLO(i2c);
700 LOG_DBG("%s: ARLO", funcname);
701 data->current.is_arlo = 1U;
702 goto error;
703 }
704
705 if (LL_I2C_IsActiveFlag_OVR(i2c)) {
706 LL_I2C_ClearFlag_OVR(i2c);
707 LOG_DBG("%s: OVR", funcname);
708 data->current.is_err = 1U;
709 goto error;
710 }
711
712 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
713 LL_I2C_ClearFlag_BERR(i2c);
714 LOG_DBG("%s: BERR", funcname);
715 data->current.is_err = 1U;
716 goto error;
717 }
718
719 return 0;
720 error:
721 return -EIO;
722 }
723
stm32_i2c_wait_timeout(uint16_t * timeout)724 static int stm32_i2c_wait_timeout(uint16_t *timeout)
725 {
726 if (*timeout == 0) {
727 return 1;
728 } else {
729 k_busy_wait(1);
730 (*timeout)--;
731 return 0;
732 }
733 }
734
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)735 static int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
736 uint8_t *next_msg_flags, uint16_t saddr)
737 {
738 const struct i2c_stm32_config *cfg = dev->config;
739 struct i2c_stm32_data *data = dev->data;
740 I2C_TypeDef *i2c = cfg->i2c;
741 uint32_t len = msg->len;
742 uint16_t timeout;
743 uint8_t *buf = msg->buf;
744 int32_t res;
745
746 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
747
748 if (msg->flags & I2C_MSG_RESTART) {
749 timeout = STM32_I2C_TIMEOUT_USEC;
750 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
751 if (stm32_i2c_wait_timeout(&timeout)) {
752 LL_I2C_GenerateStopCondition(i2c);
753 data->current.is_err = 1U;
754 goto end;
755 }
756 }
757
758 if (I2C_ADDR_10_BITS & data->dev_config) {
759 uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
760 uint8_t header = slave | HEADER;
761
762 LL_I2C_TransmitData8(i2c, header);
763 timeout = STM32_I2C_TIMEOUT_USEC;
764 while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
765 if (stm32_i2c_wait_timeout(&timeout)) {
766 LL_I2C_GenerateStopCondition(i2c);
767 data->current.is_err = 1U;
768 goto end;
769 }
770 }
771
772 slave = data->slave_address & 0xFF;
773 LL_I2C_TransmitData8(i2c, slave);
774 } else {
775 uint8_t slave = (saddr << 1) & 0xFF;
776
777 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
778 }
779
780 timeout = STM32_I2C_TIMEOUT_USEC;
781 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
782 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
783 LL_I2C_ClearFlag_AF(i2c);
784 LL_I2C_GenerateStopCondition(i2c);
785 data->current.is_nack = 1U;
786 goto end;
787 }
788 }
789 LL_I2C_ClearFlag_ADDR(i2c);
790 }
791
792 while (len) {
793 timeout = STM32_I2C_TIMEOUT_USEC;
794 while (1) {
795 if (LL_I2C_IsActiveFlag_TXE(i2c)) {
796 break;
797 }
798 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
799 LL_I2C_ClearFlag_AF(i2c);
800 LL_I2C_GenerateStopCondition(i2c);
801 data->current.is_nack = 1U;
802 goto end;
803 }
804 }
805 LL_I2C_TransmitData8(i2c, *buf);
806 buf++;
807 len--;
808 }
809
810 timeout = STM32_I2C_TIMEOUT_USEC;
811 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
812 if (stm32_i2c_wait_timeout(&timeout)) {
813 LL_I2C_GenerateStopCondition(i2c);
814 data->current.is_err = 1U;
815 goto end;
816 }
817 }
818
819 if (msg->flags & I2C_MSG_STOP) {
820 LL_I2C_GenerateStopCondition(i2c);
821 }
822
823 end:
824 check_errors(dev, __func__);
825 res = msg_end(dev, next_msg_flags, __func__);
826 if (res < 0) {
827 stm32_i2c_reset(dev);
828 }
829
830 return res;
831 }
832
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)833 static int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
834 uint8_t *next_msg_flags, uint16_t saddr)
835 {
836 const struct i2c_stm32_config *cfg = dev->config;
837 struct i2c_stm32_data *data = dev->data;
838 I2C_TypeDef *i2c = cfg->i2c;
839 uint32_t len = msg->len;
840 uint16_t timeout;
841 uint8_t *buf = msg->buf;
842 int32_t res;
843
844 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
845
846 if (msg->flags & I2C_MSG_RESTART) {
847 timeout = STM32_I2C_TIMEOUT_USEC;
848 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
849 if (stm32_i2c_wait_timeout(&timeout)) {
850 LL_I2C_GenerateStopCondition(i2c);
851 data->current.is_err = 1U;
852 goto end;
853 }
854 }
855
856 if (I2C_ADDR_10_BITS & data->dev_config) {
857 uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
858 uint8_t header = slave | HEADER;
859
860 LL_I2C_TransmitData8(i2c, header);
861 timeout = STM32_I2C_TIMEOUT_USEC;
862 while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
863 if (stm32_i2c_wait_timeout(&timeout)) {
864 LL_I2C_GenerateStopCondition(i2c);
865 data->current.is_err = 1U;
866 goto end;
867 }
868 }
869
870 slave = saddr & 0xFF;
871 LL_I2C_TransmitData8(i2c, slave);
872 timeout = STM32_I2C_TIMEOUT_USEC;
873 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
874 if (stm32_i2c_wait_timeout(&timeout)) {
875 LL_I2C_GenerateStopCondition(i2c);
876 data->current.is_err = 1U;
877 goto end;
878 }
879 }
880
881 LL_I2C_ClearFlag_ADDR(i2c);
882 stm32_i2c_generate_start_condition(i2c);
883 timeout = STM32_I2C_TIMEOUT_USEC;
884 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
885 if (stm32_i2c_wait_timeout(&timeout)) {
886 LL_I2C_GenerateStopCondition(i2c);
887 data->current.is_err = 1U;
888 goto end;
889 }
890 }
891
892 header |= I2C_REQUEST_READ;
893 LL_I2C_TransmitData8(i2c, header);
894 } else {
895 uint8_t slave = ((saddr) << 1) & 0xFF;
896
897 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
898 }
899
900 timeout = STM32_I2C_TIMEOUT_USEC;
901 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
902 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
903 LL_I2C_ClearFlag_AF(i2c);
904 LL_I2C_GenerateStopCondition(i2c);
905 data->current.is_nack = 1U;
906 goto end;
907 }
908 }
909 /* ADDR must be cleared before NACK generation. Either in 2 byte reception
910 * byte 1 will be NACK'ed and slave won't sent the last byte
911 */
912 LL_I2C_ClearFlag_ADDR(i2c);
913 if (len == 1U) {
914 /* Single byte reception: enable NACK and set STOP */
915 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
916 } else if (len == 2U) {
917 /* 2-byte reception: enable NACK and set POS */
918 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
919 LL_I2C_EnableBitPOS(i2c);
920 }
921 }
922
923 while (len) {
924 timeout = STM32_I2C_TIMEOUT_USEC;
925 while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
926 if (stm32_i2c_wait_timeout(&timeout)) {
927 LL_I2C_GenerateStopCondition(i2c);
928 data->current.is_err = 1U;
929 goto end;
930 }
931 }
932
933 timeout = STM32_I2C_TIMEOUT_USEC;
934 switch (len) {
935 case 1:
936 if (msg->flags & I2C_MSG_STOP) {
937 LL_I2C_GenerateStopCondition(i2c);
938 }
939 len--;
940 *buf = LL_I2C_ReceiveData8(i2c);
941 buf++;
942 break;
943 case 2:
944 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
945 if (stm32_i2c_wait_timeout(&timeout)) {
946 LL_I2C_GenerateStopCondition(i2c);
947 data->current.is_err = 1U;
948 goto end;
949 }
950 }
951
952 /*
953 * Stop condition must be generated before reading the
954 * last two bytes.
955 */
956 if (msg->flags & I2C_MSG_STOP) {
957 LL_I2C_GenerateStopCondition(i2c);
958 }
959
960 for (uint32_t counter = 2; counter > 0; counter--) {
961 len--;
962 *buf = LL_I2C_ReceiveData8(i2c);
963 buf++;
964 }
965
966 break;
967 case 3:
968 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
969 if (stm32_i2c_wait_timeout(&timeout)) {
970 LL_I2C_GenerateStopCondition(i2c);
971 data->current.is_err = 1U;
972 goto end;
973 }
974 }
975
976 /* Set NACK before reading N-2 byte*/
977 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
978 __fallthrough;
979 default:
980 len--;
981 *buf = LL_I2C_ReceiveData8(i2c);
982 buf++;
983 }
984 }
985 end:
986 check_errors(dev, __func__);
987 res = msg_end(dev, next_msg_flags, __func__);
988 if (res < 0) {
989 stm32_i2c_reset(dev);
990 }
991
992 return res;
993 }
994 #endif /* CONFIG_I2C_STM32_INTERRUPT */
995
stm32_i2c_configure_timing(const struct device * dev,uint32_t clock)996 int32_t stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
997 {
998 const struct i2c_stm32_config *cfg = dev->config;
999 struct i2c_stm32_data *data = dev->data;
1000 I2C_TypeDef *i2c = cfg->i2c;
1001
1002 switch (I2C_SPEED_GET(data->dev_config)) {
1003 case I2C_SPEED_STANDARD:
1004 LL_I2C_ConfigSpeed(i2c, clock, 100000, LL_I2C_DUTYCYCLE_2);
1005 break;
1006 case I2C_SPEED_FAST:
1007 LL_I2C_ConfigSpeed(i2c, clock, 400000, LL_I2C_DUTYCYCLE_2);
1008 break;
1009 default:
1010 return -EINVAL;
1011 }
1012
1013 return 0;
1014 }
1015
stm32_i2c_transaction(const struct device * dev,struct i2c_msg msg,uint8_t * next_msg_flags,uint16_t periph)1016 int stm32_i2c_transaction(const struct device *dev,
1017 struct i2c_msg msg, uint8_t *next_msg_flags,
1018 uint16_t periph)
1019 {
1020 int ret;
1021
1022 if ((msg.flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
1023 ret = stm32_i2c_msg_write(dev, &msg, next_msg_flags, periph);
1024 } else {
1025 ret = stm32_i2c_msg_read(dev, &msg, next_msg_flags, periph);
1026 }
1027 return ret;
1028 }
1029
