1/* 2 * Copyright 2022-2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-r.dtsi> 9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 10#include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-r52"; 21 reg = <0>; 22 }; 23 24 cpu@1 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-r52"; 27 reg = <1>; 28 }; 29 30 cpu@2 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-r52"; 33 reg = <2>; 34 }; 35 36 cpu@3 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-r52"; 39 reg = <3>; 40 }; 41 42 cpu@4 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-r52"; 45 reg = <4>; 46 }; 47 48 cpu@5 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-r52"; 51 reg = <5>; 52 }; 53 54 cpu@6 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-r52"; 57 reg = <6>; 58 }; 59 60 cpu@7 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-r52"; 63 reg = <7>; 64 }; 65 }; 66 67 arch_timer: timer { 68 compatible = "arm,armv8_timer"; 69 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 70 <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 71 <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 72 <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 73 interrupt-parent = <&gic>; 74 }; 75 76 /* Dummy pinctrl node, filled with pin mux options at board level */ 77 pinctrl: pinctrl { 78 compatible = "nxp,s32ze-pinctrl"; 79 status = "okay"; 80 }; 81 82 soc { 83 interrupt-parent = <&gic>; 84 85 clock: clock-controller@40030000 { 86 compatible = "nxp,s32-clock"; 87 reg = <0x40030000 0x10000>, 88 <0x40200000 0x10000>, 89 <0x40210000 0x10000>, 90 <0x40220000 0x10000>, 91 <0x40260000 0x10000>, 92 <0x40270000 0x10000>, 93 <0x40830000 0x10000>, 94 <0x41030000 0x10000>, 95 <0x41830000 0x10000>, 96 <0x42030000 0x10000>, 97 <0x42830000 0x10000>, 98 <0x44030000 0x10000>, 99 <0x440a0000 0x10000>; 100 #clock-cells = <1>; 101 status = "okay"; 102 }; 103 104 gic: interrupt-controller@47800000 { 105 compatible = "arm,gic-v3", "arm,gic"; 106 reg = <0x47800000 0x10000>, 107 <0x47900000 0x80000>; 108 interrupt-controller; 109 #interrupt-cells = <4>; 110 status = "okay"; 111 }; 112 113 dram0: memory@31780000 { 114 compatible = "mmio-sram"; 115 reg = <0x31780000 DT_SIZE_M(1)>; 116 }; 117 118 dram1: memory@35780000 { 119 compatible = "mmio-sram"; 120 reg = <0x35780000 DT_SIZE_M(1)>; 121 }; 122 123 uart0: uart@40170000 { 124 compatible = "nxp,s32-linflexd"; 125 reg = <0x40170000 0x1000>; 126 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 127 status = "disabled"; 128 }; 129 130 uart1: uart@40180000 { 131 compatible = "nxp,s32-linflexd"; 132 reg = <0x40180000 0x1000>; 133 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 134 status = "disabled"; 135 }; 136 137 uart2: uart@40190000 { 138 compatible = "nxp,s32-linflexd"; 139 reg = <0x40190000 0x1000>; 140 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 141 status = "disabled"; 142 }; 143 144 uart3: uart@40970000 { 145 compatible = "nxp,s32-linflexd"; 146 reg = <0x40970000 0x1000>; 147 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 148 status = "disabled"; 149 }; 150 151 uart4: uart@40980000 { 152 compatible = "nxp,s32-linflexd"; 153 reg = <0x40980000 0x1000>; 154 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 155 status = "disabled"; 156 }; 157 158 uart5: uart@40990000 { 159 compatible = "nxp,s32-linflexd"; 160 reg = <0x40990000 0x1000>; 161 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 162 status = "disabled"; 163 }; 164 165 uart6: uart@42170000 { 166 compatible = "nxp,s32-linflexd"; 167 reg = <0x42170000 0x1000>; 168 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 169 status = "disabled"; 170 }; 171 172 uart7: uart@42180000 { 173 compatible = "nxp,s32-linflexd"; 174 reg = <0x42180000 0x1000>; 175 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 176 status = "disabled"; 177 }; 178 179 uart8: uart@42190000 { 180 compatible = "nxp,s32-linflexd"; 181 reg = <0x42190000 0x1000>; 182 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 183 status = "disabled"; 184 }; 185 186 uart9: uart@42980000 { 187 compatible = "nxp,s32-linflexd"; 188 reg = <0x42980000 0x1000>; 189 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 190 status = "disabled"; 191 }; 192 193 uart10: uart@42990000 { 194 compatible = "nxp,s32-linflexd"; 195 reg = <0x42990000 0x1000>; 196 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 197 status = "disabled"; 198 }; 199 200 uart11: uart@429a0000 { 201 compatible = "nxp,s32-linflexd"; 202 reg = <0x429a0000 0x1000>; 203 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 204 status = "disabled"; 205 }; 206 207 uart12: uart@40330000 { 208 compatible = "nxp,s32-linflexd"; 209 reg = <0x40330000 0x1000>; 210 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 211 status = "disabled"; 212 }; 213 214 siul2_0: siul2@40520000 { 215 reg = <0x40520000 0x10000>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 219 eirq0: eirq0@40520010 { 220 compatible = "nxp,s32-siul2-eirq"; 221 reg = <0x40520010 0xb4>; 222 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 status = "disabled"; 226 }; 227 228 gpioa: gpio@40521702 { 229 compatible = "nxp,s32-gpio"; 230 reg = <0x40521702 0x02>, <0x40520240 0x40>; 231 reg-names = "pgpdo", "mscr"; 232 interrupt-parent = <&eirq0>; 233 interrupts = <1 1>, <3 0>, <5 2>, <12 3>, 234 <13 4>, <14 5>, <15 6>; 235 gpio-controller; 236 #gpio-cells = <2>; 237 ngpios = <16>; 238 status = "disabled"; 239 }; 240 241 gpiob: gpio@40521700 { 242 compatible = "nxp,s32-gpio"; 243 reg = <0x40521700 0x02>, <0x40520280 0x40>; 244 reg-names = "pgpdo", "mscr"; 245 interrupt-parent = <&eirq0>; 246 interrupts = <0 7>; 247 gpio-controller; 248 #gpio-cells = <2>; 249 ngpios = <15>; 250 status = "disabled"; 251 }; 252 253 gpioo: gpio@40521716 { 254 compatible = "nxp,s32-gpio"; 255 reg = <0x40521716 0x02>, <0x405204c0 0x40>; 256 reg-names = "pgpdo", "mscr"; 257 gpio-controller; 258 #gpio-cells = <2>; 259 ngpios = <14>; 260 gpio-reserved-ranges = <0 10>; 261 status = "disabled"; 262 }; 263 }; 264 265 siul2_1: siul2@40d20000 { 266 reg = <0x40d20000 0x10000>; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 270 eirq1: eirq1@40d20010 { 271 compatible = "nxp,s32-siul2-eirq"; 272 reg = <0x40d20010 0xb4>; 273 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 status = "disabled"; 277 }; 278 279 gpioc: gpio@40d21700 { 280 compatible = "nxp,s32-gpio"; 281 reg = <0x40d21700 0x02>, <0x40d20280 0x40>; 282 reg-names = "pgpdo", "mscr"; 283 interrupt-parent = <&eirq1>; 284 interrupts = <3 0>, <5 1>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 ngpios = <16>; 288 gpio-reserved-ranges = <0 15>; 289 status = "disabled"; 290 }; 291 292 gpiod: gpio@40d21706 { 293 compatible = "nxp,s32-gpio"; 294 reg = <0x40d21706 0x02>, <0x40d202c0 0x40>; 295 reg-names = "pgpdo", "mscr"; 296 gpio-controller; 297 #gpio-cells = <2>; 298 ngpios = <16>; 299 status = "disabled"; 300 }; 301 302 gpioe: gpio@40d21704 { 303 compatible = "nxp,s32-gpio"; 304 reg = <0x40d21704 0x02>, <0x40d20300 0x40>; 305 reg-names = "pgpdo", "mscr"; 306 gpio-controller; 307 #gpio-cells = <2>; 308 ngpios = <16>; 309 status = "disabled"; 310 }; 311 312 gpiof: gpio@40d2170a { 313 compatible = "nxp,s32-gpio"; 314 reg = <0x40d2170a 0x02>, <0x40d20340 0x40>; 315 reg-names = "pgpdo", "mscr"; 316 gpio-controller; 317 #gpio-cells = <2>; 318 ngpios = <16>; 319 status = "disabled"; 320 }; 321 322 gpiog: gpio@40d21708 { 323 compatible = "nxp,s32-gpio"; 324 reg = <0x40d21708 0x02>, <0x40d20380 0x40>; 325 reg-names = "pgpdo", "mscr"; 326 interrupt-parent = <&eirq1>; 327 interrupts = <0 2>, <1 3>, <4 4>, 328 <5 5>, <10 6>, <11 7>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 ngpios = <12>; 332 status = "disabled"; 333 }; 334 }; 335 336 siul2_3: siul2@41d20000 { 337 reg = <0x41d20000 0x10000>; 338 }; 339 340 siul2_4: siul2@42520000 { 341 reg = <0x42520000 0x10000>; 342 #address-cells = <1>; 343 #size-cells = <1>; 344 345 eirq4: eirq4@42520010 { 346 compatible = "nxp,s32-siul2-eirq"; 347 reg = <0x42520010 0xb4>; 348 interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 status = "disabled"; 352 }; 353 354 gpioh: gpio@42521708 { 355 compatible = "nxp,s32-gpio"; 356 reg = <0x42521708 0x02>, <0x42520380 0x40>; 357 reg-names = "pgpdo", "mscr"; 358 gpio-controller; 359 #gpio-cells = <2>; 360 ngpios = <16>; 361 gpio-reserved-ranges = <0 12>; 362 status = "disabled"; 363 }; 364 365 gpioi: gpio@4252170e { 366 compatible = "nxp,s32-gpio"; 367 reg = <0x4252170e 0x02>, <0x425203c0 0x40>; 368 reg-names = "pgpdo", "mscr"; 369 interrupt-parent = <&eirq4>; 370 interrupts = <11 0>, <13 1>; 371 gpio-controller; 372 #gpio-cells = <2>; 373 ngpios = <16>; 374 status = "disabled"; 375 }; 376 377 gpioj: gpio@4252170c { 378 compatible = "nxp,s32-gpio"; 379 reg = <0x4252170c 0x02>, <0x42520400 0x40>; 380 reg-names = "pgpdo", "mscr"; 381 interrupt-parent = <&eirq4>; 382 interrupts = <12 2>; 383 gpio-controller; 384 #gpio-cells = <2>; 385 ngpios = <16>; 386 status = "disabled"; 387 }; 388 389 gpiok: gpio@42521712 { 390 compatible = "nxp,s32-gpio"; 391 reg = <0x42521712 0x02>, <0x42520440 0x40>; 392 reg-names = "pgpdo", "mscr"; 393 interrupt-parent = <&eirq4>; 394 interrupts = <4 3>, <6 4>, <9 5>, 395 <11 6>, <13 7>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 ngpios = <16>; 399 status = "disabled"; 400 }; 401 402 gpiol: gpio@42521710 { 403 compatible = "nxp,s32-gpio"; 404 reg = <0x42521710 0x02>, <0x42520480 0x40>; 405 reg-names = "pgpdo", "mscr"; 406 gpio-controller; 407 #gpio-cells = <2>; 408 ngpios = <2>; 409 status = "disabled"; 410 }; 411 }; 412 413 siul2_5: siul2@42d20000 { 414 reg = <0x42d20000 0x10000>; 415 #address-cells = <1>; 416 #size-cells = <1>; 417 418 eirq5: eirq5@42d20010 { 419 compatible = "nxp,s32-siul2-eirq"; 420 reg = <0x42d20010 0xb4>; 421 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 status = "disabled"; 425 }; 426 427 gpiom: gpio@42d21710 { 428 compatible = "nxp,s32-gpio"; 429 reg = <0x42d21710 0x02>, <0x42d20480 0x40>; 430 reg-names = "pgpdo", "mscr"; 431 interrupt-parent = <&eirq5>; 432 interrupts = <1 0>, <3 1>, <5 2>, <7 3>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 ngpios = <16>; 436 gpio-reserved-ranges = <0 2>; 437 status = "disabled"; 438 }; 439 440 gpion: gpio@42d21716 { 441 compatible = "nxp,s32-gpio"; 442 reg = <0x42d21716 0x02>, <0x42d204c0 0x40>; 443 reg-names = "pgpdo", "mscr"; 444 interrupt-parent = <&eirq5>; 445 interrupts = <0 4>, <2 5>, <5 6>, <6 7>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 ngpios = <10>; 449 status = "disabled"; 450 }; 451 }; 452 453 spi0: spi@40130000 { 454 compatible = "nxp,s32-spi"; 455 reg = <0x40130000 0x10000>; 456 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 457 clocks = <&clock NXP_S32_SPI0_CLK>; 458 num-cs = <5>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 spi1: spi@40140000 { 465 compatible = "nxp,s32-spi"; 466 reg = <0x40140000 0x10000>; 467 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 468 clocks = <&clock NXP_S32_SPI1_CLK>; 469 num-cs = <5>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 spi2: spi@40930000 { 476 compatible = "nxp,s32-spi"; 477 reg = <0x40930000 0x10000>; 478 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 479 clocks = <&clock NXP_S32_SPI2_CLK>; 480 num-cs = <5>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 status = "disabled"; 484 }; 485 486 spi3: spi@40940000 { 487 compatible = "nxp,s32-spi"; 488 reg = <0x40940000 0x10000>; 489 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 490 clocks = <&clock NXP_S32_SPI3_CLK>; 491 num-cs = <5>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 status = "disabled"; 495 }; 496 497 spi4: spi@40950000 { 498 compatible = "nxp,s32-spi"; 499 reg = <0x40950000 0x10000>; 500 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 501 clocks = <&clock NXP_S32_SPI4_CLK>; 502 num-cs = <5>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 508 spi5: spi@42130000 { 509 compatible = "nxp,s32-spi"; 510 reg = <0x42130000 0x10000>; 511 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 512 clocks = <&clock NXP_S32_SPI5_CLK>; 513 num-cs = <5>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 spi6: spi@42140000 { 520 compatible = "nxp,s32-spi"; 521 reg = <0x42140000 0x10000>; 522 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 523 clocks = <&clock NXP_S32_SPI6_CLK>; 524 num-cs = <5>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 status = "disabled"; 528 }; 529 530 spi7: spi@42150000 { 531 compatible = "nxp,s32-spi"; 532 reg = <0x42150000 0x10000>; 533 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 534 clocks = <&clock NXP_S32_SPI7_CLK>; 535 num-cs = <5>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 spi8: spi@42930000 { 542 compatible = "nxp,s32-spi"; 543 reg = <0x42930000 0x10000>; 544 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 545 clocks = <&clock NXP_S32_SPI8_CLK>; 546 num-cs = <5>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 spi9: spi@42940000 { 553 compatible = "nxp,s32-spi"; 554 reg = <0x42940000 0x10000>; 555 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 556 clocks = <&clock NXP_S32_SPI9_CLK>; 557 num-cs = <5>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 563 dspi0: spi@40340000 { 564 compatible = "nxp,dspi"; 565 reg = <0x40340000 0x10000>; 566 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 567 clocks = <&clock NXP_S32_MSCDSPI_CLK>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 mru0: mbox@76070000 { 574 compatible = "nxp,s32-mru"; 575 reg = <0x76070000 0x10000>; 576 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 577 #mbox-cells = <1>; 578 status = "disabled"; 579 }; 580 581 mru1: mbox@76090000 { 582 compatible = "nxp,s32-mru"; 583 reg = <0x76090000 0x10000>; 584 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 585 #mbox-cells = <1>; 586 status = "disabled"; 587 }; 588 589 mru2: mbox@76270000 { 590 compatible = "nxp,s32-mru"; 591 reg = <0x76270000 0x10000>; 592 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 593 #mbox-cells = <1>; 594 status = "disabled"; 595 }; 596 597 mru3: mbox@76290000 { 598 compatible = "nxp,s32-mru"; 599 reg = <0x76290000 0x10000>; 600 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 601 #mbox-cells = <1>; 602 status = "disabled"; 603 }; 604 605 mru4: mbox@76870000 { 606 compatible = "nxp,s32-mru"; 607 reg = <0x76870000 0x10000>; 608 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 609 #mbox-cells = <1>; 610 status = "disabled"; 611 }; 612 613 mru5: mbox@76890000 { 614 compatible = "nxp,s32-mru"; 615 reg = <0x76890000 0x10000>; 616 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 617 #mbox-cells = <1>; 618 status = "disabled"; 619 }; 620 621 mru6: mbox@76a70000 { 622 compatible = "nxp,s32-mru"; 623 reg = <0x76a70000 0x10000>; 624 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 625 #mbox-cells = <1>; 626 status = "disabled"; 627 }; 628 629 mru7: mbox@76a90000 { 630 compatible = "nxp,s32-mru"; 631 reg = <0x76a90000 0x10000>; 632 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 633 #mbox-cells = <1>; 634 status = "disabled"; 635 }; 636 637 netc: ethernet@74000000 { 638 reg = <0x74000000 0x1000000>; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 ranges; 642 643 emdio: mdio@74b60000 { 644 compatible = "nxp,s32-netc-emdio"; 645 reg = <0x74b60000 0x1c44>; 646 status = "disabled"; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 }; 650 651 enetc_psi0: ethernet@74b00000 { 652 compatible = "nxp,s32-netc-psi"; 653 reg = <0x74b00000 0x10000>; 654 status = "disabled"; 655 }; 656 657 enetc_vsi1: ethernet@74bc0000 { 658 compatible = "nxp,s32-netc-vsi"; 659 reg = <0x74bc0000 0x10000>; 660 status = "disabled"; 661 }; 662 663 enetc_vsi2: ethernet@74bd0000 { 664 compatible = "nxp,s32-netc-vsi"; 665 reg = <0x74bd0000 0x10000>; 666 status = "disabled"; 667 }; 668 669 enetc_vsi3: ethernet@74be0000 { 670 compatible = "nxp,s32-netc-vsi"; 671 reg = <0x74be0000 0x10000>; 672 status = "disabled"; 673 }; 674 675 enetc_vsi4: ethernet@74bf0000 { 676 compatible = "nxp,s32-netc-vsi"; 677 reg = <0x74bf0000 0x10000>; 678 status = "disabled"; 679 }; 680 681 enetc_vsi5: ethernet@74c00000 { 682 compatible = "nxp,s32-netc-vsi"; 683 reg = <0x74c00000 0x10000>; 684 status = "disabled"; 685 }; 686 687 enetc_vsi6: ethernet@74c10000 { 688 compatible = "nxp,s32-netc-vsi"; 689 reg = <0x74c10000 0x10000>; 690 status = "disabled"; 691 }; 692 693 enetc_vsi7: ethernet@74c20000 { 694 compatible = "nxp,s32-netc-vsi"; 695 reg = <0x74c20000 0x10000>; 696 status = "disabled"; 697 }; 698 }; 699 700 canxl0: can@4741b000 { 701 compatible = "nxp,s32-canxl"; 702 reg = <0x4741b000 0x1000>, 703 <0x47423000 0x1000>, 704 <0x47425000 0x1000>, 705 <0x47427000 0x1000>; 706 reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; 707 status = "disabled"; 708 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 709 <GIC_SPI 225 IRQ_TYPE_LEVEL 0xb0>; 710 interrupt-names = "rx_tx_mru", "error"; 711 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 712 }; 713 714 canxl1: can@4751b000 { 715 compatible = "nxp,s32-canxl"; 716 reg = <0x4751b000 0x1000>, 717 <0x47523000 0x1000>, 718 <0x47525000 0x1000>, 719 <0x47527000 0x1000>; 720 reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; 721 status = "disabled"; 722 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 723 <GIC_SPI 227 IRQ_TYPE_LEVEL 0xb0>; 724 interrupt-names = "rx_tx_mru", "error"; 725 clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; 726 }; 727 728 flexcan0: can@449a0000 { 729 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 730 reg = <0x449a0000 0x4000>; 731 clk-source = <0>; 732 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 733 <GIC_SPI 583 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 734 <GIC_SPI 584 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 735 <GIC_SPI 585 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 736 <GIC_SPI 586 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 737 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 738 "ored_64_95_mb", "ored_96_127_mb"; 739 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 740 status = "disabled"; 741 }; 742 743 flexcan1: can@449b0000 { 744 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 745 reg = <0x449b0000 0x4000>; 746 clk-source = <0>; 747 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 748 <GIC_SPI 589 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 749 <GIC_SPI 590 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 750 <GIC_SPI 591 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 751 <GIC_SPI 592 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 752 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 753 "ored_64_95_mb", "ored_96_127_mb"; 754 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 755 status = "disabled"; 756 }; 757 758 flexcan2: can@449c0000 { 759 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 760 clk-source = <0>; 761 reg = <0x449c0000 0x4000>; 762 interrupts = <GIC_SPI 593 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 763 <GIC_SPI 595 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 764 <GIC_SPI 596 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 765 <GIC_SPI 597 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 766 <GIC_SPI 598 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 767 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 768 "ored_64_95_mb", "ored_96_127_mb"; 769 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 770 status = "disabled"; 771 }; 772 773 flexcan3: can@449d0000 { 774 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 775 clk-source = <0>; 776 reg = <0x449d0000 0x4000>; 777 interrupts = <GIC_SPI 599 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 778 <GIC_SPI 601 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 779 <GIC_SPI 602 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 780 <GIC_SPI 603 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 781 <GIC_SPI 604 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 782 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 783 "ored_64_95_mb", "ored_96_127_mb"; 784 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 785 status = "disabled"; 786 }; 787 788 flexcan4: can@449e0000 { 789 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 790 clk-source = <0>; 791 reg = <0x449e0000 0x4000>; 792 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 793 <GIC_SPI 607 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 794 <GIC_SPI 608 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 795 <GIC_SPI 609 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 796 <GIC_SPI 610 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 797 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 798 "ored_64_95_mb", "ored_96_127_mb"; 799 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 800 status = "disabled"; 801 }; 802 803 flexcan5: can@449f0000 { 804 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 805 clk-source = <0>; 806 reg = <0x449f0000 0x4000>; 807 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 808 <GIC_SPI 613 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 809 <GIC_SPI 614 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 810 <GIC_SPI 615 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 811 <GIC_SPI 616 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 812 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 813 "ored_64_95_mb", "ored_96_127_mb"; 814 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 815 status = "disabled"; 816 }; 817 818 flexcan6: can@44ba0000 { 819 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 820 clk-source = <0>; 821 reg = <0x44ba0000 0x4000>; 822 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 823 <GIC_SPI 619 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 824 <GIC_SPI 620 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 825 <GIC_SPI 621 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 826 <GIC_SPI 622 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 827 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 828 "ored_64_95_mb", "ored_96_127_mb"; 829 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 830 status = "disabled"; 831 }; 832 833 flexcan7: can@44bb0000 { 834 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 835 clk-source = <0>; 836 reg = <0x44bb0000 0x4000>; 837 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 838 <GIC_SPI 625 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 839 <GIC_SPI 626 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 840 <GIC_SPI 627 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 841 <GIC_SPI 628 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 842 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 843 "ored_64_95_mb", "ored_96_127_mb"; 844 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 845 status = "disabled"; 846 }; 847 848 flexcan8: can@44bc0000 { 849 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 850 clk-source = <0>; 851 reg = <0x44bc0000 0x4000>; 852 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 853 <GIC_SPI 631 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 854 <GIC_SPI 632 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 855 <GIC_SPI 633 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 856 <GIC_SPI 634 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 857 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 858 "ored_64_95_mb", "ored_96_127_mb"; 859 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 860 status = "disabled"; 861 }; 862 863 flexcan9: can@44bd0000 { 864 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 865 clk-source = <0>; 866 reg = <0x44bd0000 0x4000>; 867 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 868 <GIC_SPI 637 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 869 <GIC_SPI 638 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 870 <GIC_SPI 639 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 871 <GIC_SPI 640 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 872 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 873 "ored_64_95_mb", "ored_96_127_mb"; 874 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 875 status = "disabled"; 876 }; 877 878 flexcan10: can@44be0000 { 879 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 880 clk-source = <0>; 881 reg = <0x44be0000 0x4000>; 882 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 883 <GIC_SPI 643 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 884 <GIC_SPI 644 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 885 <GIC_SPI 645 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 886 <GIC_SPI 646 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 887 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 888 "ored_64_95_mb", "ored_96_127_mb"; 889 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 890 status = "disabled"; 891 }; 892 893 flexcan11: can@44bf0000 { 894 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 895 clk-source = <0>; 896 reg = <0x44bf0000 0x4000>; 897 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 898 <GIC_SPI 649 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 899 <GIC_SPI 650 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 900 <GIC_SPI 651 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 901 <GIC_SPI 652 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 902 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 903 "ored_64_95_mb", "ored_96_127_mb"; 904 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 905 status = "disabled"; 906 }; 907 908 flexcan12: can@44da0000 { 909 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 910 clk-source = <0>; 911 reg = <0x44da0000 0x4000>; 912 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 913 <GIC_SPI 655 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 914 <GIC_SPI 656 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 915 <GIC_SPI 657 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 916 <GIC_SPI 658 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 917 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 918 "ored_64_95_mb", "ored_96_127_mb"; 919 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 920 status = "disabled"; 921 }; 922 923 flexcan13: can@44db0000 { 924 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 925 clk-source = <0>; 926 reg = <0x44db0000 0x4000>; 927 interrupts = <GIC_SPI 659 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 928 <GIC_SPI 661 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 929 <GIC_SPI 662 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 930 <GIC_SPI 663 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 931 <GIC_SPI 664 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 932 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 933 "ored_64_95_mb", "ored_96_127_mb"; 934 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 935 status = "disabled"; 936 }; 937 938 flexcan14: can@44dc0000 { 939 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 940 clk-source = <0>; 941 reg = <0x44dc0000 0x4000>; 942 interrupts = <GIC_SPI 665 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 943 <GIC_SPI 667 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 944 <GIC_SPI 668 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 945 <GIC_SPI 669 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 946 <GIC_SPI 670 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 947 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 948 "ored_64_95_mb", "ored_96_127_mb"; 949 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 950 status = "disabled"; 951 }; 952 953 flexcan15: can@44dd0000 { 954 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 955 clk-source = <0>; 956 reg = <0x44dd0000 0x4000>; 957 interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 958 <GIC_SPI 673 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 959 <GIC_SPI 674 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 960 <GIC_SPI 675 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 961 <GIC_SPI 676 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 962 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 963 "ored_64_95_mb", "ored_96_127_mb"; 964 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 965 status = "disabled"; 966 }; 967 968 flexcan16: can@44de0000 { 969 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 970 clk-source = <0>; 971 reg = <0x44de0000 0x4000>; 972 interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 973 <GIC_SPI 679 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 974 <GIC_SPI 680 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 975 <GIC_SPI 681 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 976 <GIC_SPI 682 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 977 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 978 "ored_64_95_mb", "ored_96_127_mb"; 979 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 980 status = "disabled"; 981 }; 982 983 flexcan17: can@44df0000 { 984 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 985 clk-source = <0>; 986 reg = <0x44df0000 0x4000>; 987 interrupts = <GIC_SPI 683 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 988 <GIC_SPI 685 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 989 <GIC_SPI 686 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 990 <GIC_SPI 687 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 991 <GIC_SPI 688 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 992 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 993 "ored_64_95_mb", "ored_96_127_mb"; 994 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 995 status = "disabled"; 996 }; 997 998 flexcan18: can@44fa0000 { 999 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1000 clk-source = <0>; 1001 reg = <0x44fa0000 0x4000>; 1002 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1003 <GIC_SPI 691 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1004 <GIC_SPI 692 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1005 <GIC_SPI 693 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1006 <GIC_SPI 694 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1007 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1008 "ored_64_95_mb", "ored_96_127_mb"; 1009 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1010 status = "disabled"; 1011 }; 1012 1013 flexcan19: can@44fb0000 { 1014 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1015 clk-source = <0>; 1016 reg = <0x44fb0000 0x4000>; 1017 interrupts = <GIC_SPI 695 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1018 <GIC_SPI 697 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1019 <GIC_SPI 698 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1020 <GIC_SPI 699 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1021 <GIC_SPI 700 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1022 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1023 "ored_64_95_mb", "ored_96_127_mb"; 1024 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1025 status = "disabled"; 1026 }; 1027 1028 flexcan20: can@44fc0000 { 1029 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1030 clk-source = <0>; 1031 reg = <0x44fc0000 0x4000>; 1032 interrupts = <GIC_SPI 701 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1033 <GIC_SPI 703 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1034 <GIC_SPI 704 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1035 <GIC_SPI 705 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1036 <GIC_SPI 706 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1037 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1038 "ored_64_95_mb", "ored_96_127_mb"; 1039 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1040 status = "disabled"; 1041 }; 1042 1043 flexcan21: can@44fd0000 { 1044 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1045 clk-source = <0>; 1046 reg = <0x44fd0000 0x4000>; 1047 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1048 <GIC_SPI 709 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1049 <GIC_SPI 710 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1050 <GIC_SPI 711 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1051 <GIC_SPI 712 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1052 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1053 "ored_64_95_mb", "ored_96_127_mb"; 1054 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1055 status = "disabled"; 1056 }; 1057 1058 flexcan22: can@44fe0000 { 1059 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1060 clk-source = <0>; 1061 reg = <0x44fe0000 0x4000>; 1062 interrupts = <GIC_SPI 713 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1063 <GIC_SPI 715 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1064 <GIC_SPI 716 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1065 <GIC_SPI 717 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1066 <GIC_SPI 718 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1067 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1068 "ored_64_95_mb", "ored_96_127_mb"; 1069 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1070 status = "disabled"; 1071 }; 1072 1073 flexcan23: can@44ff0000 { 1074 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 1075 clk-source = <0>; 1076 reg = <0x44ff0000 0x4000>; 1077 interrupts = <GIC_SPI 719 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1078 <GIC_SPI 721 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1079 <GIC_SPI 722 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1080 <GIC_SPI 723 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1081 <GIC_SPI 724 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1082 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", 1083 "ored_64_95_mb", "ored_96_127_mb"; 1084 clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; 1085 status = "disabled"; 1086 }; 1087 1088 sar_adc0: adc@402c0000 { 1089 compatible = "nxp,s32-adc-sar"; 1090 reg = <0x402C0000 0x1000>; 1091 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1092 <GIC_SPI 169 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1093 <GIC_SPI 170 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1094 #io-channel-cells = <1>; 1095 status = "disabled"; 1096 }; 1097 1098 sar_adc1: adc@402e0000 { 1099 compatible = "nxp,s32-adc-sar"; 1100 reg = <0x402e0000 0x1000>; 1101 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1102 <GIC_SPI 202 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1103 <GIC_SPI 203 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1104 #io-channel-cells = <1>; 1105 status = "disabled"; 1106 }; 1107 1108 lpi2c1: i2c@409d0000 { 1109 compatible = "nxp,lpi2c"; 1110 reg = <0x409d0000 0x10000>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1114 clocks = <&clock NXP_S32_P1_REG_INTF_CLK>; 1115 clock-frequency = <I2C_BITRATE_STANDARD>; 1116 status = "disabled"; 1117 }; 1118 1119 lpi2c2: i2c@421d0000 { 1120 compatible = "nxp,lpi2c"; 1121 reg = <0x421d0000 0x10000>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1125 clocks = <&clock NXP_S32_P4_REG_INTF_CLK>; 1126 clock-frequency = <I2C_BITRATE_STANDARD>; 1127 status = "disabled"; 1128 }; 1129 1130 edma0: dma-controller@405d0000 { 1131 compatible = "nxp,mcux-edma"; 1132 nxp,version = <3>; 1133 reg = <0x405d0000 0x10000>, <0x405a0000 0x10000>, <0x405b0000 0x100000>; 1134 dma-channels = <32>; 1135 dma-requests = <64>; 1136 dmamux-reg-offset = <3>; 1137 #dma-cells = <2>; 1138 nxp,mem2mem; 1139 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1140 <GIC_SPI 32 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1141 <GIC_SPI 33 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1142 <GIC_SPI 34 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1143 <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1144 <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1145 <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1146 <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1147 <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1148 <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1149 <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1150 <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1151 <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1152 <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1153 <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1154 <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1155 <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1156 <GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1157 <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1158 <GIC_SPI 50 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1159 <GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1160 <GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1161 <GIC_SPI 53 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1162 <GIC_SPI 54 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1163 <GIC_SPI 55 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1164 <GIC_SPI 56 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1165 <GIC_SPI 57 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1166 <GIC_SPI 58 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1167 <GIC_SPI 59 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1168 <GIC_SPI 60 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1169 <GIC_SPI 61 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1170 <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1171 <GIC_SPI 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1172 status = "disabled"; 1173 }; 1174 1175 edma1: dma-controller@40dd0000 { 1176 compatible = "nxp,mcux-edma"; 1177 nxp,version = <3>; 1178 reg = <0x40dd0000 0x10000>, <0x40da0000 0x10000>; 1179 dma-channels = <16>; 1180 dma-requests = <64>; 1181 dmamux-reg-offset = <3>; 1182 #dma-cells = <2>; 1183 nxp,mem2mem; 1184 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1185 <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1186 <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1187 <GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1188 <GIC_SPI 69 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1189 <GIC_SPI 70 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1190 <GIC_SPI 71 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1191 <GIC_SPI 72 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1192 <GIC_SPI 73 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1193 <GIC_SPI 74 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1194 <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1195 <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1196 <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1197 <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1198 <GIC_SPI 79 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1199 <GIC_SPI 80 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1200 <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1201 status = "disabled"; 1202 }; 1203 1204 edma4: dma-controller@425d0000 { 1205 compatible = "nxp,mcux-edma"; 1206 nxp,version = <3>; 1207 reg = <0x425d0000 0x10000>, <0x425a0000 0x10000>; 1208 dma-channels = <32>; 1209 dma-requests = <64>; 1210 dmamux-reg-offset = <3>; 1211 #dma-cells = <2>; 1212 nxp,mem2mem; 1213 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1214 <GIC_SPI 84 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1215 <GIC_SPI 85 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1216 <GIC_SPI 86 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1217 <GIC_SPI 87 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1218 <GIC_SPI 88 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1219 <GIC_SPI 89 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1220 <GIC_SPI 90 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1221 <GIC_SPI 91 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1222 <GIC_SPI 92 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1223 <GIC_SPI 93 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1224 <GIC_SPI 94 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1225 <GIC_SPI 95 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1226 <GIC_SPI 96 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1227 <GIC_SPI 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1228 <GIC_SPI 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1229 <GIC_SPI 81 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1230 status = "disabled"; 1231 }; 1232 1233 edma5: dma-controller@42dd0000 { 1234 compatible = "nxp,mcux-edma"; 1235 nxp,version = <3>; 1236 reg = <0x42dd0000 0x10000>, <0x42da0000 0x10000>; 1237 dma-channels = <32>; 1238 dma-requests = <64>; 1239 dmamux-reg-offset = <3>; 1240 #dma-cells = <2>; 1241 nxp,mem2mem; 1242 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1243 <GIC_SPI 102 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1244 <GIC_SPI 103 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1245 <GIC_SPI 104 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1246 <GIC_SPI 105 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1247 <GIC_SPI 106 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1248 <GIC_SPI 107 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1249 <GIC_SPI 108 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1250 <GIC_SPI 109 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1251 <GIC_SPI 110 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1252 <GIC_SPI 111 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1253 <GIC_SPI 112 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1254 <GIC_SPI 113 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1255 <GIC_SPI 114 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1256 <GIC_SPI 115 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1257 <GIC_SPI 116 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, 1258 <GIC_SPI 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 1259 status = "disabled"; 1260 }; 1261 1262 }; 1263}; 1264
