1/* 2 * Copyright (c) 2021 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8 9/* Macros for device tree declarations of npcx soc family */ 10#include <zephyr/dt-bindings/adc/adc.h> 11#include <zephyr/dt-bindings/clock/npcx_clock.h> 12#include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/i2c/i2c.h> 15#include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h> 16#include <zephyr/dt-bindings/pwm/pwm.h> 17#include <zephyr/dt-bindings/sensor/npcx_tach.h> 18#include <freq.h> 19 20/ { 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4f"; 28 reg = <0>; 29 cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>; 30 }; 31 32 power-states { 33 suspend_to_idle0: suspend-to-idle0 { 34 compatible = "zephyr,power-state"; 35 power-state-name = "suspend-to-idle"; 36 substate-id = <0>; 37 min-residency-us = <1000>; 38 }; 39 40 suspend_to_idle1: suspend-to-idle1 { 41 compatible = "zephyr,power-state"; 42 power-state-name = "suspend-to-idle"; 43 substate-id = <1>; 44 min-residency-us = <201000>; 45 }; 46 }; 47 }; 48 49 def-io-conf-list { 50 compatible = "nuvoton,npcx-pinctrl-def"; 51 /* Change default functional pads to GPIOs 52 * no_spip - PIN95.97.A1.A3 53 * no_fpip - PIN96.A0.A2.A4 - Internal flash only 54 * no_pwrgd - PIN72 55 * no_lpc_espi - PIN46.47.51.52.53.54.55.57 56 * no_peci_en - PIN81 57 * npsl_in1_sl - PIND2 58 * npsl_in2_sl - PIN00 59 * no_ksi0-7 - PIN31.30.27.26.25.24.23.22 60 * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04. 61 * 82.83.03.B1 62 */ 63 pinmux = <>; 64 }; 65 66 /** Dummy pinctrl node. It will be initialized with defaults based on the SoC series. 67 * Then, the user can override the pin control options at the board level. 68 */ 69 pinctrl: pinctrl { 70 compatible = "nuvoton,npcx-pinctrl"; 71 status = "okay"; 72 }; 73 74 /* Dummy node of IOs that have leakage current. The user can override 75 * 'leak-gpios' prop. at board DT file to save more power consumption. 76 */ 77 power_leakage_io: power-leakage-io { 78 compatible = "nuvoton,npcx-leakage-io"; 79 status = "okay"; 80 }; 81 82 soc { 83 pcc: clock-controller@4000d000 { 84 compatible = "nuvoton,npcx-pcc"; 85 /* Cells for bus type, clock control reg and bit */ 86 #clock-cells = <3>; 87 /* First reg region is Power Management Controller */ 88 /* Second reg region is Core Domain Clock Generator */ 89 reg = <0x4000d000 0x2000 90 0x400b5000 0x2000>; 91 reg-names = "pmc", "cdcg"; 92 }; 93 94 scfg: scfg@400c3000 { 95 compatible = "nuvoton,npcx-scfg"; 96 /* First reg region is System Configuration Device */ 97 /* Second reg region is Debugger Interface Device */ 98 /* Third reg region is System Glue Device */ 99 reg = <0x400c3000 0x70 100 0x400c3070 0x30 101 0x400a5000 0x2000>; 102 reg-names = "scfg", "dbg", "glue"; 103 #alt-cells = <3>; 104 #lvol-cells = <2>; 105 }; 106 107 mdc: mdc@4000c000 { 108 compatible = "syscon"; 109 reg = <0x4000c000 0xa>; 110 reg-io-width = <1>; 111 }; 112 113 mdc_header: mdc@4000c00a { 114 compatible = "syscon"; 115 reg = <0x4000c00a 0x4>; 116 reg-io-width = <2>; 117 }; 118 119 miwu0: miwu@400bb000 { 120 compatible = "nuvoton,npcx-miwu"; 121 reg = <0x400bb000 0x2000>; 122 index = <0>; 123 #miwu-cells = <2>; 124 }; 125 126 miwu1: miwu@400bd000 { 127 compatible = "nuvoton,npcx-miwu"; 128 reg = <0x400bd000 0x2000>; 129 index = <1>; 130 #miwu-cells = <2>; 131 }; 132 133 miwu2: miwu@400bf000 { 134 compatible = "nuvoton,npcx-miwu"; 135 reg = <0x400bf000 0x2000>; 136 index = <2>; 137 #miwu-cells = <2>; 138 }; 139 140 gpio0: gpio@40081000 { 141 compatible = "nuvoton,npcx-gpio"; 142 reg = <0x40081000 0x2000>; 143 gpio-controller; 144 index = <0x0>; 145 #gpio-cells=<2>; 146 }; 147 148 gpio1: gpio@40083000 { 149 compatible = "nuvoton,npcx-gpio"; 150 reg = <0x40083000 0x2000>; 151 gpio-controller; 152 index = <0x1>; 153 #gpio-cells=<2>; 154 }; 155 156 gpio2: gpio@40085000 { 157 compatible = "nuvoton,npcx-gpio"; 158 reg = <0x40085000 0x2000>; 159 gpio-controller; 160 index = <0x2>; 161 #gpio-cells=<2>; 162 }; 163 164 gpio3: gpio@40087000 { 165 compatible = "nuvoton,npcx-gpio"; 166 reg = <0x40087000 0x2000>; 167 gpio-controller; 168 index = <0x3>; 169 #gpio-cells=<2>; 170 }; 171 172 gpio4: gpio@40089000 { 173 compatible = "nuvoton,npcx-gpio"; 174 reg = <0x40089000 0x2000>; 175 gpio-controller; 176 index = <0x4>; 177 #gpio-cells=<2>; 178 }; 179 180 gpio5: gpio@4008b000 { 181 compatible = "nuvoton,npcx-gpio"; 182 reg = <0x4008b000 0x2000>; 183 gpio-controller; 184 index = <0x5>; 185 #gpio-cells=<2>; 186 }; 187 188 gpio6: gpio@4008d000 { 189 compatible = "nuvoton,npcx-gpio"; 190 reg = <0x4008d000 0x2000>; 191 gpio-controller; 192 index = <0x6>; 193 #gpio-cells=<2>; 194 }; 195 196 gpio7: gpio@4008f000 { 197 compatible = "nuvoton,npcx-gpio"; 198 reg = <0x4008f000 0x2000>; 199 gpio-controller; 200 index = <0x7>; 201 #gpio-cells=<2>; 202 }; 203 204 gpio8: gpio@40091000 { 205 compatible = "nuvoton,npcx-gpio"; 206 reg = <0x40091000 0x2000>; 207 gpio-controller; 208 index = <0x8>; 209 #gpio-cells=<2>; 210 }; 211 212 gpio9: gpio@40093000 { 213 compatible = "nuvoton,npcx-gpio"; 214 reg = <0x40093000 0x2000>; 215 gpio-controller; 216 index = <0x9>; 217 #gpio-cells=<2>; 218 }; 219 220 gpioa: gpio@40095000 { 221 compatible = "nuvoton,npcx-gpio"; 222 reg = <0x40095000 0x2000>; 223 gpio-controller; 224 index = <0xA>; 225 #gpio-cells=<2>; 226 }; 227 228 gpiob: gpio@40097000 { 229 compatible = "nuvoton,npcx-gpio"; 230 reg = <0x40097000 0x2000>; 231 gpio-controller; 232 index = <0xB>; 233 #gpio-cells=<2>; 234 }; 235 236 gpioc: gpio@40099000 { 237 compatible = "nuvoton,npcx-gpio"; 238 reg = <0x40099000 0x2000>; 239 gpio-controller; 240 index = <0xC>; 241 #gpio-cells=<2>; 242 }; 243 244 gpiod: gpio@4009b000 { 245 compatible = "nuvoton,npcx-gpio"; 246 reg = <0x4009b000 0x2000>; 247 gpio-controller; 248 index = <0xD>; 249 #gpio-cells=<2>; 250 }; 251 252 gpioe: gpio@4009d000 { 253 compatible = "nuvoton,npcx-gpio"; 254 reg = <0x4009d000 0x2000>; 255 gpio-controller; 256 index = <0xE>; 257 #gpio-cells=<2>; 258 }; 259 260 gpiof: gpio@4009f000 { 261 compatible = "nuvoton,npcx-gpio"; 262 reg = <0x4009f000 0x2000>; 263 gpio-controller; 264 index = <0xF>; 265 #gpio-cells=<2>; 266 }; 267 268 pwm0: pwm@40080000 { 269 compatible = "nuvoton,npcx-pwm"; 270 reg = <0x40080000 0x2000>; 271 pwm-channel = <0>; 272 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>; 273 #pwm-cells = <3>; 274 status = "disabled"; 275 }; 276 277 pwm1: pwm@40082000 { 278 compatible = "nuvoton,npcx-pwm"; 279 reg = <0x40082000 0x2000>; 280 pwm-channel = <1>; 281 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>; 282 #pwm-cells = <3>; 283 status = "disabled"; 284 }; 285 286 pwm2: pwm@40084000 { 287 compatible = "nuvoton,npcx-pwm"; 288 reg = <0x40084000 0x2000>; 289 pwm-channel = <2>; 290 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>; 291 #pwm-cells = <3>; 292 status = "disabled"; 293 }; 294 295 pwm3: pwm@40086000 { 296 compatible = "nuvoton,npcx-pwm"; 297 reg = <0x40086000 0x2000>; 298 pwm-channel = <3>; 299 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>; 300 #pwm-cells = <3>; 301 status = "disabled"; 302 }; 303 304 pwm4: pwm@40088000 { 305 compatible = "nuvoton,npcx-pwm"; 306 reg = <0x40088000 0x2000>; 307 pwm-channel = <4>; 308 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>; 309 #pwm-cells = <3>; 310 status = "disabled"; 311 }; 312 313 pwm5: pwm@4008a000 { 314 compatible = "nuvoton,npcx-pwm"; 315 reg = <0x4008a000 0x2000>; 316 pwm-channel = <5>; 317 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>; 318 #pwm-cells = <3>; 319 status = "disabled"; 320 }; 321 322 pwm6: pwm@4008c000 { 323 compatible = "nuvoton,npcx-pwm"; 324 reg = <0x4008c000 0x2000>; 325 pwm-channel = <6>; 326 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; 327 #pwm-cells = <3>; 328 status = "disabled"; 329 }; 330 331 pwm7: pwm@4008e000 { 332 compatible = "nuvoton,npcx-pwm"; 333 reg = <0x4008e000 0x2000>; 334 pwm-channel = <7>; 335 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>; 336 #pwm-cells = <3>; 337 status = "disabled"; 338 }; 339 340 adc0: adc@400d1000 { 341 compatible = "nuvoton,npcx-adc"; 342 #io-channel-cells = <1>; 343 reg = <0x400d1000 0x2000>; 344 interrupts = <10 3>; 345 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; 346 vref-mv = <2816>; 347 status = "disabled"; 348 }; 349 350 twd0: watchdog@400d8000 { 351 compatible = "nuvoton,npcx-watchdog"; 352 reg = <0x400d8000 0x2000>; 353 t0-out = <&wui_t0out>; 354 }; 355 356 espi0: espi@4000a000 { 357 compatible = "nuvoton,npcx-espi"; 358 reg = <0x4000a000 0x2000>; 359 interrupts = <18 3>; /* Interrupt for eSPI Bus */ 360 361 /* clocks for eSPI modules */ 362 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; 363 /* WUI maps for eSPI signals */ 364 espi-rst-wui = <&wui_espi_rst>; 365 366 #address-cells = <1>; 367 #size-cells = <0>; 368 #vw-cells = <3>; 369 status = "disabled"; 370 }; 371 372 host_sub: lpc@400c1000 { 373 compatible = "nuvoton,npcx-host-sub"; 374 /* host sub-module register address & size */ 375 reg = <0x400c1000 0x2000 376 0x40010000 0x2000 377 0x4000e000 0x2000 378 0x400c7000 0x2000 379 0x400c9000 0x2000 380 0x400cb000 0x2000>; 381 reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi", 382 "pm_hcmd"; 383 384 /* host sub-module IRQ and priority */ 385 interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ 386 <56 3>, /* KBC Output-Buf-Empty (OBE) */ 387 <26 3>, /* PMCH Input-Buf-Full (IBF) */ 388 <3 3>, /* PMCH Output-Buf-Empty (OBE) */ 389 <6 3>; /* Port80 FIFO Not Empty */ 390 interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", 391 "pmch_obe", "p80_fifo"; 392 393 /* WUI map for accessing host sub-modules */ 394 host-acc-wui = <&wui_host_acc>; 395 396 /* clocks for host sub-modules */ 397 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, 398 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, 399 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, 400 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, 401 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; 402 }; 403 404 /* I2c Controllers - Do not use them as i2c node directly */ 405 i2c_ctrl0: i2c@40009000 { 406 compatible = "nuvoton,npcx-i2c-ctrl"; 407 reg = <0x40009000 0x1000>; 408 interrupts = <13 3>; 409 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; 410 status = "disabled"; 411 }; 412 413 i2c_ctrl1: i2c@4000b000 { 414 compatible = "nuvoton,npcx-i2c-ctrl"; 415 reg = <0x4000b000 0x1000>; 416 interrupts = <14 3>; 417 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; 418 status = "disabled"; 419 }; 420 421 i2c_ctrl2: i2c@400c0000 { 422 compatible = "nuvoton,npcx-i2c-ctrl"; 423 reg = <0x400c0000 0x1000>; 424 interrupts = <36 3>; 425 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; 426 status = "disabled"; 427 }; 428 429 i2c_ctrl3: i2c@400c2000 { 430 compatible = "nuvoton,npcx-i2c-ctrl"; 431 reg = <0x400c2000 0x1000>; 432 interrupts = <37 3>; 433 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; 434 status = "disabled"; 435 }; 436 437 i2c_ctrl4: i2c@40008000 { 438 compatible = "nuvoton,npcx-i2c-ctrl"; 439 reg = <0x40008000 0x1000>; 440 interrupts = <19 3>; 441 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; 442 status = "disabled"; 443 }; 444 445 i2c_ctrl5: i2c@40017000 { 446 compatible = "nuvoton,npcx-i2c-ctrl"; 447 reg = <0x40017000 0x1000>; 448 interrupts = <20 3>; 449 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; 450 status = "disabled"; 451 }; 452 453 i2c_ctrl6: i2c@40018000 { 454 compatible = "nuvoton,npcx-i2c-ctrl"; 455 reg = <0x40018000 0x1000>; 456 interrupts = <16 3>; 457 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; 458 status = "disabled"; 459 }; 460 461 i2c_ctrl7: i2c@40019000 { 462 compatible = "nuvoton,npcx-i2c-ctrl"; 463 reg = <0x40019000 0x1000>; 464 interrupts = <8 3>; 465 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; 466 status = "disabled"; 467 }; 468 469 tach1: tach@400e1000 { 470 compatible = "nuvoton,npcx-tach"; 471 reg = <0x400e1000 0x2000>; 472 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>; 473 status = "disabled"; 474 }; 475 476 tach2: tach@400e3000 { 477 compatible = "nuvoton,npcx-tach"; 478 reg = <0x400e3000 0x2000>; 479 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>; 480 status = "disabled"; 481 }; 482 483 ps2_ctrl0: ps2@400b1000 { 484 compatible = "nuvoton,npcx-ps2-ctrl"; 485 reg = <0x400b1000 0x1000>; 486 interrupts = <21 4>; 487 clocks = <&pcc NPCX_CLOCK_BUS_FREERUN NPCX_PWDWN_CTL1 3>; 488 489 /* PS2 Channels - Please use them as PS2 node */ 490 ps2_channel0: io_ps2_channel0 { 491 compatible = "nuvoton,npcx-ps2-channel"; 492 channel = <0x00>; 493 status = "disabled"; 494 }; 495 496 ps2_channel1: io_ps2_channel1 { 497 compatible = "nuvoton,npcx-ps2-channel"; 498 channel = <0x01>; 499 status = "disabled"; 500 }; 501 502 ps2_channel2: io_ps2_channel2 { 503 compatible = "nuvoton,npcx-ps2-channel"; 504 channel = <0x02>; 505 status = "disabled"; 506 }; 507 508 ps2_channel3: io_ps2_channel3 { 509 compatible = "nuvoton,npcx-ps2-channel"; 510 channel = <0x03>; 511 status = "disabled"; 512 }; 513 }; 514 515 /* Dedicated Quad-SPI interface to access SPI flashes */ 516 qspi_fiu0: quadspi@40020000 { 517 compatible = "nuvoton,npcx-fiu-qspi"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <0x40020000 0x2000>; 521 }; 522 523 peci0: peci@400d4000 { 524 compatible = "nuvoton,npcx-peci"; 525 reg = <0x400d4000 0x1000>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 interrupts = <4 4>; 529 clocks = <&pcc NPCX_CLOCK_BUS_FMCLK NPCX_PWDWN_CTL4 5>; 530 status = "disabled"; 531 }; 532 533 kbd: kbd@400a3000 { 534 compatible = "nuvoton,npcx-kbd"; 535 reg = <0x400a3000 0x2000>; 536 interrupts = <49 4>; 537 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>; 538 wui-maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26 539 &wui_io25 &wui_io24 &wui_io23 &wui_io22>; 540 status = "disabled"; 541 }; 542 543 spip0: spi@400d2000 { 544 compatible = "nuvoton,npcx-spip"; 545 reg = <0x400d2000 0x1000>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 interrupts = <57 3>; 549 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL4 7>; 550 status = "disabled"; 551 552 }; 553 }; 554 555 soc-if { 556 /* Soc specific peripheral interface phandles which don't contain 557 * 'reg' prop. Please overwrite 'status' prop. to 'okay' if you 558 * want to switch the interface from io to specific peripheral. 559 */ 560 host_uart: io_host_uart { 561 compatible = "nuvoton,npcx-host-uart"; 562 status = "disabled"; 563 }; 564 565 i2c0_0: io_i2c_ctrl0_port0 { 566 compatible = "nuvoton,npcx-i2c-port"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 port = <0x00>; 570 controller = <&i2c_ctrl0>; 571 status = "disabled"; 572 }; 573 574 i2c1_0: io_i2c_ctrl1_port0 { 575 compatible = "nuvoton,npcx-i2c-port"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 port = <0x10>; 579 controller = <&i2c_ctrl1>; 580 status = "disabled"; 581 }; 582 583 i2c2_0: io_i2c_ctrl2_port0 { 584 compatible = "nuvoton,npcx-i2c-port"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 port = <0x20>; 588 controller = <&i2c_ctrl2>; 589 status = "disabled"; 590 }; 591 592 i2c3_0: io_i2c_ctrl3_port0 { 593 compatible = "nuvoton,npcx-i2c-port"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 port = <0x30>; 597 controller = <&i2c_ctrl3>; 598 status = "disabled"; 599 }; 600 601 i2c4_1: io_i2c_ctrl4_port1 { 602 compatible = "nuvoton,npcx-i2c-port"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 port = <0x41>; 606 controller = <&i2c_ctrl4>; 607 status = "disabled"; 608 }; 609 610 i2c5_0: io_i2c_ctrl5_port0 { 611 compatible = "nuvoton,npcx-i2c-port"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 port = <0x50>; 615 controller = <&i2c_ctrl5>; 616 status = "disabled"; 617 }; 618 619 i2c5_1: io_i2c_ctrl5_port1 { 620 compatible = "nuvoton,npcx-i2c-port"; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 port = <0x51>; 624 controller = <&i2c_ctrl5>; 625 status = "disabled"; 626 }; 627 628 i2c6_0: io_i2c_ctrl6_port0 { 629 compatible = "nuvoton,npcx-i2c-port"; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 port = <0x60>; 633 controller = <&i2c_ctrl6>; 634 status = "disabled"; 635 }; 636 637 i2c6_1: io_i2c_ctrl6_port1 { 638 compatible = "nuvoton,npcx-i2c-port"; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 port = <0x61>; 642 controller = <&i2c_ctrl6>; 643 status = "disabled"; 644 }; 645 646 i2c7_0: io_i2c_ctrl7_port0 { 647 compatible = "nuvoton,npcx-i2c-port"; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 port = <0x70>; 651 controller = <&i2c_ctrl7>; 652 status = "disabled"; 653 }; 654 655 power_ctrl_psl: power-ctrl-psl { 656 compatible = "nuvoton,npcx-power-psl"; 657 status = "disabled"; 658 }; 659 }; 660 661 soc-id { 662 compatible = "nuvoton,npcx-soc-id"; 663 family-id = <0x20>; 664 }; 665 666 booter-variant { 667 compatible = "nuvoton,npcx-booter-variant"; 668 }; 669}; 670 671&nvic { 672 arm,num-irq-priority-bits = <3>; 673}; 674
