1/*
2 * Copyright 2021, 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/imx_ccm.h>
8#include <xtensa/xtensa.dtsi>
9#include <mem.h>
10
11/ {
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			device_type = "cpu";
18			compatible = "cdns,tensilica-xtensa-lx6";
19			reg = <0>;
20
21			#address-cells = <1>;
22			#size-cells = <0>;
23
24			clic: interrupt-controller@0 {
25				compatible = "cdns,xtensa-core-intc";
26				reg = <0>;
27				interrupt-controller;
28				#interrupt-cells = <3>;
29			};
30		};
31	};
32
33	sram0: memory@92400000 {
34		device_type = "memory";
35		compatible = "mmio-sram";
36		reg = <0x92400000 DT_SIZE_K(512)>;
37	};
38
39	sram1: memory@92c00000 {
40		device_type = "memory";
41		compatible = "mmio-sram";
42		reg = <0x92c00000 DT_SIZE_K(512)>;
43	};
44
45	mclk1: mclk {
46		compatible = "fixed-clock";
47		#clock-cells = <0>;
48		clock-frequency = <12288000>;
49	};
50
51	soc {
52		irqsteer: interrupt-controller@30a80000 {
53			compatible = "nxp,irqsteer-intc";
54			reg = <0x30a80000 DT_SIZE_K(64)>;
55
56			#size-cells = <0>;
57			#address-cells = <1>;
58
59			master0: interrupt-controller@0 {
60				compatible = "nxp,irqsteer-master";
61				reg = <0>;
62				interrupt-controller;
63				#interrupt-cells = <1>;
64				interrupts-extended = <&clic 19 0 0>;
65			};
66
67			master1: interrupt-controller@1 {
68				compatible = "nxp,irqsteer-master";
69				reg = <1>;
70				interrupt-controller;
71				#interrupt-cells = <1>;
72				interrupts-extended = <&clic 20 0 0>;
73			};
74
75			master2: interrupt-controller@2 {
76				compatible = "nxp,irqsteer-master";
77				reg = <2>;
78				interrupt-controller;
79				#interrupt-cells = <1>;
80				interrupts-extended = <&clic 21 0 0>;
81			};
82		};
83
84		ccm: ccm@30380000 {
85			compatible = "nxp,imx-ccm";
86			reg = <0x30380000 DT_SIZE_K(64)>;
87			#clock-cells = <3>;
88		};
89
90		sdma3: dma@30e00000 {
91			compatible = "nxp,sdma";
92			reg = <0x30e00000 DT_SIZE_K(64)>;
93			interrupt-parent = <&master1>;
94			interrupts = <2 0 0>;
95			#dma-cells = <2>;
96			status = "disabled";
97		};
98
99		sai3: dai@30c30000 {
100			compatible = "nxp,dai-sai";
101			reg = <0x30c30000 DT_SIZE_K(64)>;
102
103			mclk-is-output;
104			clocks = <&mclk1>;
105			clock-names = "mclk1";
106
107			interrupt-parent = <&master1>;
108			interrupts = <18>;
109			dai-index = <3>;
110			/* DMA event source, peripheral type */
111			dmas = <&sdma3 5 5>, <&sdma3 4 5>;
112			dma-names = "tx", "rx";
113			status = "disabled";
114		};
115
116		micfil: micfil@30ca0000 {
117			compatible = "nxp,dai-micfil";
118			reg = <0x30ca0000 DT_SIZE_K(64)>;
119			dai-index = <2>;
120			dmas = <&sdma3 24 6>;
121			fifo-depth = <32>;
122			status = "disabled";
123		};
124
125		iomuxc: iomuxc@30330000 {
126			compatible = "nxp,imx-iomuxc";
127			reg = <0x30330000 DT_SIZE_K(64)>;
128			status = "okay";
129			pinctrl: pinctrl {
130				status = "okay";
131				compatible = "nxp,imx8mp-pinctrl";
132			};
133		};
134
135		/*
136		 * For now only UART4 is supported and
137		 * tested with the serial driver
138		 */
139		uart4: uart@30a60000 {
140			compatible = "nxp,imx-iuart";
141			reg = <0x30a60000 0x10000>;
142			/* TODO: This INTID is just a dummy
143			 * until we can support UART interrupts
144			 */
145			interrupt-parent = <&master0>;
146			interrupts = <29 0 0>;
147			clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
148			status = "disabled";
149		};
150
151		mailbox0: mailbox@30e70000 {
152			compatible = "nxp,imx-mu";
153			reg = <0x30e70000 0x10000>;
154			interrupt-parent = <&clic>;
155			interrupts = <7 0 0>;
156			rdc = <0>;
157			status = "disabled";
158		};
159	};
160};
161