| /hal_microchip-latest/mec5/drivers/ |
| D | mec_gpio.c | 34 uint8_t mask; member
396 int mec_hal_gpio_set_config_mask(uint32_t pin, uint32_t cfg, uint32_t mask) in mec_hal_gpio_set_config_mask()
521 uint32_t mask = mec_cfg_tbl[prop].mask; in mec_hal_gpio_set_props() local
721 int mec_hal_gpio_set_ctrl_mask(uint32_t pin, uint32_t val, uint32_t mask) in mec_hal_gpio_set_ctrl_mask()
763 int mec_hal_gpio_ctrl2_mask(const uint32_t pin, uint32_t val, uint32_t mask) in mec_hal_gpio_ctrl2_mask()
1029 int mec_hal_gpio_parout_port_set_bits(const uint8_t port, const uint32_t mask) in mec_hal_gpio_parout_port_set_bits()
1040 int mec_hal_gpio_parout_port_mask(const uint8_t port, const uint32_t newval, const uint32_t mask) in mec_hal_gpio_parout_port_mask()
1125 int mec_hal_gpio_port_ia_status_clr_mask(uint8_t port, uint32_t mask) in mec_hal_gpio_port_ia_status_clr_mask()
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| D | mec_espi.c | 21 uint32_t mask = (MEC_ESPI_IO_CAP0_PC_SUPP_Msk | MEC_ESPI_IO_CAP0_VW_SUPP_Msk in set_supported_channels() local
46 uint32_t mask = MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Msk; in set_supported_max_freq() local
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| D | mec_i3c_pvt.c | 33 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_clear()
43 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_enable()
125 void _i3c_intr_sgnl_enable(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sgnl_enable()
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| D | mec_mailbox.c | 129 int mec_hal_mbox_sirq_en_mask(struct mec_mbox_regs *base, uint8_t val, uint8_t mask) in mec_hal_mbox_sirq_en_mask()
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| D | mec_emi.c | 250 int mec_hal_emi_swi_host_clear_enable(struct mec_emi_regs *regs, uint16_t mask, uint16_t enable) in mec_hal_emi_swi_host_clear_enable()
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| D | mec_i3c.c | 219 uint32_t mask = 0xFFFFFFFFU; in MEC_HAL_I3C_Target_Interrupts_Init() local
252 uint32_t mask = 0xFFFFFFFFU; in MEC_HAL_I3C_Controller_Interrupts_Init() local
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| D | mec_espi_taf.c | 326 int mec_hal_espi_taf_pr_dirty_clr_mask(struct mec_espi_taf_regs *regs, uint32_t mask) in mec_hal_espi_taf_pr_dirty_clr_mask()
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| D | mec_espi_host_dev.c | 208 int mec_hal_espi_iobar_mask_set(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t mask) in mec_hal_espi_iobar_mask_set()
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| D | mec_pcr.c | 253 int mec_hal_pcr_slp_en_mask(uint8_t regid, uint32_t val, uint32_t mask) in mec_hal_pcr_slp_en_mask()
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| D | mec_i2c.c | 537 int mec_hal_i2c_smb_intr_ctrl(struct mec_i2c_smb_ctx *ctx, uint32_t mask, uint8_t enable) in mec_hal_i2c_smb_intr_ctrl()
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| /hal_microchip-latest/mpfs/mpfs_hal/common/nwc/ |
| D | mss_ddr.c | 2178 uint8_t mask; in ddr_setup() local
3508 uint8_t mask = (uint8_t)(1U<<laneToTest); in write_calibration_using_mtc() local
3651 uint64_t mask; in FPGA_VREFDQ_calibration_using_mtc() local
3776 uint64_t mask; in VREFDQ_calibration_using_mtc() local
3896 static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC_PATTERN data_patte… in MTC_test()
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| /hal_microchip-latest/mpfs/mpfs_hal/common/ |
| D | mss_mpu.c | 306 uint64_t mask = 0U; in pmp_get_napot_base_and_range() local
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| /hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/ |
| D | mss_ethernet_mac.c | 4725 uint32_t mask; in MSS_MAC_set_tx_cutthru() local
4751 uint32_t mask; in MSS_MAC_set_rx_cutthru() local
4778 uint32_t mask; in MSS_MAC_get_tx_cutthru() local
4808 uint32_t mask; in MSS_MAC_get_rx_cutthru() local
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| D | mss_ethernet_mac_types.h | 1145 uint16_t mask; /*!< 16 bit mask if data is 16 bit */ member
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