1/*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <mem.h>
9#include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-m7";
20			reg = <0>;
21		};
22
23		cpu@1 {
24			device_type = "cpu";
25			compatible = "arm,cortex-m7";
26			reg = <1>;
27		};
28
29		mpu: mpu@e000ed90 {
30			compatible = "arm,armv7m-mpu";
31			reg = <0xe000ed90 0x40>;
32		};
33	};
34
35	/* Dummy pinctrl node, filled with pin mux options at board level */
36	pinctrl: pinctrl {
37		compatible = "nxp,s32k3-pinctrl";
38		status = "okay";
39	};
40
41	soc {
42		interrupt-parent = <&nvic>;
43
44		itcm: memory@0 {
45			compatible = "zephyr,memory-region", "arm,itcm";
46			reg = <0x00000000 DT_SIZE_K(64)>;
47			zephyr,memory-region = "ITCM";
48		};
49
50		dtcm: memory@20000000 {
51			compatible = "zephyr,memory-region", "arm,dtcm";
52			reg = <0x20000000 DT_SIZE_K(128)>;
53			zephyr,memory-region = "DTCM";
54		};
55
56		sram0_1: sram0_1@20400000 {
57			compatible = "mmio-sram";
58			reg = <0x20400000 DT_SIZE_K(320)>;
59		};
60
61		/*
62		 * Last 48Kb is reserved by Secure BAF, application core cannot access it.
63		 *
64		 * Do not assign the compatible for this now, when Flash API is implemented,
65		 * need to check if "soc-nv-flash" can be used or a new binding need to be
66		 * created, based on it.
67		 */
68		flash0: flash@400000 {
69			reg = <0x00400000 DT_SIZE_K(4048)>;
70			status = "disabled";
71		};
72
73		clock: clock-controller@402c8000 {
74			compatible = "nxp,s32-clock";
75			reg = <0x402c8000 0x4000>,
76				<0x402cc000 0x4000>,
77				<0x402d0000 0x4000>,
78				<0x402d4000 0x4000>,
79				<0x402d8000 0x4000>,
80				<0x402e0000 0x4000>;
81			#clock-cells = <1>;
82			status = "okay";
83		};
84
85		siul2_0: siul2@40290000 {
86			reg = <0x40290000 0x10000>;
87			#address-cells = <1>;
88			#size-cells = <1>;
89
90			eirq0: eirq@40290010 {
91				compatible = "nxp,s32-siul2-eirq";
92				reg = <0x40290010 0xb4>;
93				interrupts = <53 0>, <54 0>, <55 0>, <56 0>;
94				interrupt-controller;
95				#interrupt-cells = <2>;
96				status = "disabled";
97			};
98
99			gpioa_l: gpio@40291702 {
100				compatible = "nxp,s32-gpio";
101				reg = <0x40291702 0x02>, <0x40290240 0x40>;
102				reg-names = "pgpdo", "mscr";
103				interrupt-parent = <&eirq0>;
104				interrupts = <0 0>, <1 1>, <2 2>, <3 3>, <4 4>,
105					<5 5>, <6 6>, <7 7>, <8 16>, <9 17>,
106					<10 18>, <11 19>, <12 20>, <13 21>,
107					<14 22>, <15 23>;
108				nxp,wkpu = <&wkpu>;
109				nxp,wkpu-interrupts = <1 9>, <2 4>, <6 19>,
110					<8 27>, <9 25>, <13 8>, <15 24>;
111				gpio-controller;
112				#gpio-cells = <2>;
113				ngpios = <16>;
114				status = "disabled";
115			};
116
117			gpioa_h: gpio@40291700 {
118				compatible = "nxp,s32-gpio";
119				reg = <0x40291700 0x02>, <0x40290280 0x40>;
120				reg-names = "pgpdo", "mscr";
121				interrupt-parent = <&eirq0>;
122				interrupts = <0 4>, <2 0>, <3 1>, <4 2>,
123					<5 3>, <9 5>, <12 6>, <14 7>;
124				nxp,wkpu = <&wkpu>;
125				nxp,wkpu-interrupts = <0 35>, <4 63>, <9 38>,
126					<10 39>, <14 41>;
127				gpio-controller;
128				#gpio-cells = <2>;
129				ngpios = <16>;
130				status = "disabled";
131			};
132
133			gpiob_l: gpio@40291706 {
134				compatible = "nxp,s32-gpio";
135				reg = <0x40291706 0x02>, <0x402902c0 0x40>;
136				reg-names = "pgpdo", "mscr";
137				interrupt-parent = <&eirq0>;
138				interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>,
139					<5 13>, <8 14>, <9 15>, <10 24>, <11 25>,
140					<12 26>, <13 27>, <14 28>, <15 29>;
141				nxp,wkpu = <&wkpu>;
142				nxp,wkpu-interrupts = <0 11>, <2 12>, <8 29>,
143					<9 21>, <11 20>, <12 16>, <13 15>, <15 37>;
144				gpio-controller;
145				#gpio-cells = <2>;
146				ngpios = <16>;
147				gpio-reserved-ranges = <6 2>;
148				status = "disabled";
149			};
150
151			gpiob_h: gpio@40291704 {
152				compatible = "nxp,s32-gpio";
153				reg = <0x40291704 0x02>, <0x40290300 0x40>;
154				reg-names = "pgpdo", "mscr";
155				interrupt-parent = <&eirq0>;
156				interrupts = <0 30>, <1 31>, <5 8>, <6 9>, <7 10>,
157					<8 11>, <9 12>, <10 13>, <12 14>, <15 15>;
158				nxp,wkpu = <&wkpu>;
159				nxp,wkpu-interrupts = <0 17>, <1 18>, <3 42>,
160					<5 43>, <7 44>, <10 45>, <12 46>;
161				gpio-controller;
162				#gpio-cells = <2>;
163				ngpios = <16>;
164				status = "disabled";
165			};
166
167			gpioc_l: gpio@4029170a {
168				compatible = "nxp,s32-gpio";
169				reg = <0x4029170a 0x02>, <0x40290340 0x40>;
170				reg-names = "pgpdo", "mscr";
171				interrupt-parent = <&eirq0>;
172				interrupts = <0 1>, <1 1>, <2 2>, <3 3>, <4 4>,
173					<5 5>, <6 6>, <7 7>, <8 16>, <9 17>,
174					<10 18>, <11 19>, <12 20>, <13 21>,
175					<14 22>, <15 23>;
176				nxp,wkpu = <&wkpu>;
177				nxp,wkpu-interrupts = <6 7>, <7 6>, <9 14>, <11 22>;
178				gpio-controller;
179				#gpio-cells = <2>;
180				ngpios = <16>;
181				status = "disabled";
182			};
183
184			gpioc_h: gpio@40291708 {
185				compatible = "nxp,s32-gpio";
186				reg = <0x40291708 0x02>, <0x40290380 0x40>;
187				reg-names = "pgpdo", "mscr";
188				interrupt-parent = <&eirq0>;
189				interrupts = <4 16>, <5 17>, <7 18>, <8 19>,
190					<9 20>, <10 21>, <11 22>, <13 23>;
191				nxp,wkpu = <&wkpu>;
192				nxp,wkpu-interrupts = <2 40>, <4 47>, <7 48>,
193					<8 50>, <9 49>, <10 52>, <13 51>, <15 53>;
194				gpio-controller;
195				#gpio-cells = <2>;
196				ngpios = <16>;
197				status = "disabled";
198			};
199
200			gpiod_l: gpio@4029170e {
201				compatible = "nxp,s32-gpio";
202				reg = <0x4029170e 0x02>, <0x402903c0 0x40>;
203				reg-names = "pgpdo", "mscr";
204				interrupt-parent = <&eirq0>;
205				interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>,
206					<5 13>, <6 14>, <7 15>, <8 24>,
207					<9 25>, <10 26>, <11 27>, <12 28>,
208					<13 29>, <14 30>, <15 31>;
209				nxp,wkpu = <&wkpu>;
210				nxp,wkpu-interrupts = <0 10>, <2 13>, <3 5>,
211					<4 26>, <13 28>;
212				gpio-controller;
213				#gpio-cells = <2>;
214				ngpios = <16>;
215				status = "disabled";
216			};
217
218			gpiod_h: gpio@4029170c {
219				compatible = "nxp,s32-gpio";
220				reg = <0x4029170c 0x02>, <0x40290400 0x40>;
221				reg-names = "pgpdo", "mscr";
222				interrupt-parent = <&eirq0>;
223				interrupts = <1 24>, <4 25>, <5 26>, <6 27>,
224					<7 28>, <8 29>, <11 30>, <12 31>;
225				nxp,wkpu = <&wkpu>;
226				nxp,wkpu-interrupts = <4 58>, <7 54>, <11 55>,
227					<13 56>, <15 57>;
228				gpio-controller;
229				#gpio-cells = <2>;
230				ngpios = <16>;
231				status = "disabled";
232			};
233
234			gpioe_l: gpio@40291712 {
235				compatible = "nxp,s32-gpio";
236				reg = <0x40291712 0x02>, <0x40290440 0x40>;
237				reg-names = "pgpdo", "mscr";
238				interrupt-parent = <&eirq0>;
239				interrupts = <0 0>, <1 1>, <2 2>, <3 3>,
240					<4 4>, <5 5>, <6 6>, <8 7>,
241					<9 8>, <10 9>, <11 10>, <12 11>,
242					<13 12>, <14 13>, <15 14>;
243				nxp,wkpu = <&wkpu>;
244				nxp,wkpu-interrupts = <0 30>, <2 31>, <5 36>,
245					<6 33>, <11 32>, <14 34>;
246				gpio-controller;
247				#gpio-cells = <2>;
248				ngpios = <16>;
249				status = "disabled";
250			};
251
252			gpioe_h: gpio@40291710 {
253				compatible = "nxp,s32-gpio";
254				reg = <0x40291710 0x02>, <0x40290480 0x40>;
255				reg-names = "pgpdo", "mscr";
256				interrupt-parent = <&eirq0>;
257				interrupts = <0 15>;
258				nxp,wkpu = <&wkpu>;
259				nxp,wkpu-interrupts = <0 23>, <2 59>, <5 60>,
260					<7 61>, <9 62>;
261				gpio-controller;
262				#gpio-cells = <2>;
263				ngpios = <16>;
264				status = "disabled";
265			};
266
267			gpiof_l: gpio@40291716 {
268				compatible = "nxp,s32-gpio";
269				reg = <0x40291716 0x02>, <0x402904c0 0x40>;
270				reg-names = "pgpdo", "mscr";
271				interrupt-parent = <&eirq0>;
272				interrupts = <0 0>, <1 1>, <2 2>, <3 3>,
273					<4 4>, <5 5>, <6 6>, <7 7>,
274					<8 16>, <9 17>, <10 18>, <11 19>,
275					<12 20>, <13 21>, <14 22>, <15 23>;
276				gpio-controller;
277				#gpio-cells = <2>;
278				ngpios = <16>;
279				status = "disabled";
280			};
281
282			gpiof_h: gpio@40291714 {
283				compatible = "nxp,s32-gpio";
284				reg = <0x40291714 0x02>, <0x40290500 0x40>;
285				reg-names = "pgpdo", "mscr";
286				gpio-controller;
287				#gpio-cells = <2>;
288				ngpios = <16>;
289				status = "disabled";
290			};
291
292			gpiog_l: gpio@4029171a {
293				compatible = "nxp,s32-gpio";
294				reg = <0x4029171a 0x02>, <0x40290540 0x40>;
295				reg-names = "pgpdo", "mscr";
296				interrupt-parent = <&eirq0>;
297				interrupts = <0 8>, <1 9>, <2 10>, <3 11>,
298					<4 12>, <5 13>, <6 14>, <7 15>,
299					<8 24>, <9 25>, <10 26>, <11 27>,
300					<12 28>, <13 29>, <14 30>, <15 31>;
301				gpio-controller;
302				#gpio-cells = <2>;
303				ngpios = <16>;
304				status = "disabled";
305			};
306
307			gpiog_h: gpio@40291718 {
308				compatible = "nxp,s32-gpio";
309				reg = <0x40291718 0x02>, <0x40290580 0x40>;
310				reg-names = "pgpdo", "mscr";
311				gpio-controller;
312				#gpio-cells = <2>;
313				ngpios = <16>;
314				status = "disabled";
315			};
316		};
317
318		wkpu: wkpu@402b4000 {
319			compatible = "nxp,s32-wkpu";
320			reg = <0x402b4000 0x4000>;
321			interrupts = <83 0>;
322			status = "disabled";
323		};
324
325		lpuart0: uart@40328000 {
326			compatible = "nxp,lpuart";
327			reg = <0x40328000 0x4000>;
328			interrupts = <141 0>;
329			clocks = <&clock NXP_S32_LPUART0_CLK>;
330			status = "disabled";
331		};
332
333		lpuart1: uart@4032c000 {
334			compatible = "nxp,lpuart";
335			reg = <0x4032c000 0x4000>;
336			interrupts = <142 0>;
337			clocks = <&clock NXP_S32_LPUART1_CLK>;
338			status = "disabled";
339		};
340
341		lpuart2: uart@40330000 {
342			compatible = "nxp,lpuart";
343			reg = <0x40330000 0x4000>;
344			interrupts = <143 0>;
345			clocks = <&clock NXP_S32_LPUART2_CLK>;
346			status = "disabled";
347		};
348
349		lpuart3: uart@40334000 {
350			compatible = "nxp,lpuart";
351			reg = <0x40334000 0x4000>;
352			interrupts = <144 0>;
353			clocks = <&clock NXP_S32_LPUART3_CLK>;
354			status = "disabled";
355		};
356
357		lpuart4: uart@40338000 {
358			compatible = "nxp,lpuart";
359			reg = <0x40338000 0x4000>;
360			interrupts = <145 0>;
361			clocks = <&clock NXP_S32_LPUART4_CLK>;
362			status = "disabled";
363		};
364
365		lpuart5: uart@4033c000 {
366			compatible = "nxp,lpuart";
367			reg = <0x4033c000 0x4000>;
368			interrupts = <146 0>;
369			clocks = <&clock NXP_S32_LPUART5_CLK>;
370			status = "disabled";
371		};
372
373		lpuart6: uart@40340000 {
374			compatible = "nxp,lpuart";
375			reg = <0x40340000 0x4000>;
376			interrupts = <147 0>;
377			clocks = <&clock NXP_S32_LPUART6_CLK>;
378			status = "disabled";
379		};
380
381		lpuart7: uart@40344000 {
382			compatible = "nxp,lpuart";
383			reg = <0x40344000 0x4000>;
384			interrupts = <148 0>;
385			clocks = <&clock NXP_S32_LPUART7_CLK>;
386			status = "disabled";
387		};
388
389		lpuart8: uart@4048c000 {
390			compatible = "nxp,lpuart";
391			reg = <0x4048c000 0x4000>;
392			interrupts = <149 0>;
393			clocks = <&clock NXP_S32_LPUART8_CLK>;
394			status = "disabled";
395		};
396
397		lpuart9: uart@40490000 {
398			compatible = "nxp,lpuart";
399			reg = <0x40490000 0x4000>;
400			interrupts = <150 0>;
401			clocks = <&clock NXP_S32_LPUART9_CLK>;
402			status = "disabled";
403		};
404
405		lpuart10: uart@40494000 {
406			compatible = "nxp,lpuart";
407			reg = <0x40494000 0x4000>;
408			interrupts = <151 0>;
409			clocks = <&clock NXP_S32_LPUART10_CLK>;
410			status = "disabled";
411		};
412
413		lpuart11: uart@40498000 {
414			compatible = "nxp,lpuart";
415			reg = <0x40498000 0x4000>;
416			interrupts = <152 0>;
417			clocks = <&clock NXP_S32_LPUART11_CLK>;
418			status = "disabled";
419		};
420
421		lpuart12: uart@4049c000 {
422			compatible = "nxp,lpuart";
423			reg = <0x4049c000 0x4000>;
424			interrupts = <153 0>;
425			clocks = <&clock NXP_S32_LPUART12_CLK>;
426			status = "disabled";
427		};
428
429		lpuart13: uart@404a0000 {
430			compatible = "nxp,lpuart";
431			reg = <0x404a0000 0x4000>;
432			interrupts = <154 0>;
433			clocks = <&clock NXP_S32_LPUART13_CLK>;
434			status = "disabled";
435		};
436
437		lpuart14: uart@404a4000 {
438			compatible = "nxp,lpuart";
439			reg = <0x404a4000 0x4000>;
440			interrupts = <155 0>;
441			clocks = <&clock NXP_S32_LPUART14_CLK>;
442			status = "disabled";
443		};
444
445		lpuart15: uart@404a8000 {
446			compatible = "nxp,lpuart";
447			reg = <0x404a8000 0x4000>;
448			interrupts = <156 0>;
449			clocks = <&clock NXP_S32_LPUART15_CLK>;
450			status = "disabled";
451		};
452
453		qspi0: qspi@404cc000 {
454			compatible = "nxp,s32-qspi";
455			reg = <0x404cc000 0x4000>;
456			#address-cells = <1>;
457			#size-cells = <0>;
458			status = "disabled";
459		};
460
461		flexcan0: can@40304000 {
462			compatible = "nxp,flexcan-fd", "nxp,flexcan";
463			reg = <0x40304000 0x4000>;
464			clocks = <&clock NXP_S32_FLEXCANA_CLK>;
465			clk-source = <0>;
466			interrupts = <109 0>, <110 0>, <111 0>, <112 0>;
467			interrupt-names = "ored", "ored_0_31_mb",
468						"ored_32_63_mb", "ored_64_95_mb";
469			status = "disabled";
470		};
471
472		flexcan1: can@40308000 {
473			compatible = "nxp,flexcan-fd", "nxp,flexcan";
474			reg = <0x40308000 0x4000>;
475			clocks = <&clock NXP_S32_FLEXCANA_CLK>;
476			clk-source = <0>;
477			interrupts = <113 0>, <114 0>, <115 0>;
478			interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb";
479			status = "disabled";
480		};
481
482		flexcan2: can@4030c000 {
483			compatible = "nxp,flexcan-fd", "nxp,flexcan";
484			reg = <0x4030c000 0x4000>;
485			clocks = <&clock NXP_S32_FLEXCANA_CLK>;
486			clk-source = <0>;
487			interrupts = <116 0>, <117 0>, <118 0>;
488			interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb";
489			status = "disabled";
490		};
491
492		flexcan3: can@40310000 {
493			compatible = "nxp,flexcan-fd", "nxp,flexcan";
494			reg = <0x40310000 0x4000>;
495			clocks = <&clock NXP_S32_FLEXCANB_CLK>;
496			clk-source = <0>;
497			interrupts = <119 0>, <120 0>;
498			interrupt-names = "ored", "ored_0_31_mb";
499			status = "disabled";
500		};
501
502		flexcan4: can@40314000 {
503			compatible = "nxp,flexcan-fd", "nxp,flexcan";
504			reg = <0x40314000 0x4000>;
505			clocks = <&clock NXP_S32_FLEXCANB_CLK>;
506			clk-source = <0>;
507			interrupts = <121 0>, <122 0>;
508			interrupt-names = "ored", "ored_0_31_mb";
509			status = "disabled";
510		};
511
512		flexcan5: can@40318000 {
513			compatible = "nxp,flexcan-fd", "nxp,flexcan";
514			reg = <0x40318000 0x4000>;
515			clocks = <&clock NXP_S32_FLEXCANB_CLK>;
516			clk-source = <0>;
517			interrupts = <123 0>, <124 0>;
518			interrupt-names = "ored", "ored_0_31_mb";
519			status = "disabled";
520		};
521
522		lpi2c0: i2c@40350000 {
523			compatible = "nxp,lpi2c";
524			reg = <0x40350000 0x10000>;
525			clocks = <&clock NXP_S32_LPI2C0_CLK>;
526			#address-cells = <1>;
527			#size-cells = <0>;
528			interrupts = <161 0>;
529			status = "disabled";
530		};
531
532		lpi2c1: i2c@40354000 {
533			compatible = "nxp,lpi2c";
534			reg = <0x40354000 0x10000>;
535			clocks = <&clock NXP_S32_LPI2C1_CLK>;
536			#address-cells = <1>;
537			#size-cells = <0>;
538			interrupts = <162 0>;
539			status = "disabled";
540		};
541
542		adc0: adc@400a0000 {
543			compatible = "nxp,s32-adc-sar";
544			reg = <0x400a0000 0x1000>;
545			interrupts = <180 0>;
546			#io-channel-cells = <1>;
547			status = "disabled";
548		};
549
550		adc1: adc@400a4000 {
551			compatible = "nxp,s32-adc-sar";
552			reg = <0x400a4000 0x1000>;
553			interrupts = <181 0>;
554			#io-channel-cells = <1>;
555			status = "disabled";
556		};
557
558		adc2: adc@400a8000 {
559			compatible = "nxp,s32-adc-sar";
560			reg = <0x400a8000 0x1000>;
561			interrupts = <182 0>;
562			#io-channel-cells = <1>;
563			status = "disabled";
564		};
565
566		lpspi0: spi@40358000 {
567			compatible = "nxp,lpspi";
568			reg = <0x40358000 0x4000>;
569			interrupts = <165 0>;
570			clocks = <&clock NXP_S32_LPSPI0_CLK>;
571			#address-cells = <1>;
572			#size-cells = <0>;
573			status = "disabled";
574		};
575
576		lpspi1: spi@4035c000 {
577			compatible = "nxp,lpspi";
578			reg = <0x4035c000 0x4000>;
579			interrupts = <166 0>;
580			clocks = <&clock NXP_S32_LPSPI1_CLK>;
581			#address-cells = <1>;
582			#size-cells = <0>;
583			status = "disabled";
584		};
585
586		lpspi2: spi@40360000 {
587			compatible = "nxp,lpspi";
588			reg = <0x40360000 0x4000>;
589			interrupts = <167 0>;
590			clocks = <&clock NXP_S32_LPSPI2_CLK>;
591			#address-cells = <1>;
592			#size-cells = <0>;
593			status = "disabled";
594		};
595
596		lpspi3: spi@40364000 {
597			compatible = "nxp,lpspi";
598			reg = <0x40364000 0x4000>;
599			interrupts = <168 0>;
600			clocks = <&clock NXP_S32_LPSPI3_CLK>;
601			#address-cells = <1>;
602			#size-cells = <0>;
603			status = "disabled";
604		};
605
606		lpspi4: spi@404bc000 {
607			compatible = "nxp,lpspi";
608			reg = <0x404bc000 0x4000>;
609			interrupts = <169 0>;
610			clocks = <&clock NXP_S32_LPSPI4_CLK>;
611			#address-cells = <1>;
612			#size-cells = <0>;
613			status = "disabled";
614		};
615
616		lpspi5: spi@404c0000 {
617			compatible = "nxp,lpspi";
618			reg = <0x404c0000 0x4000>;
619			interrupts = <170 0>;
620			clocks = <&clock NXP_S32_LPSPI5_CLK>;
621			#address-cells = <1>;
622			#size-cells = <0>;
623			status = "disabled";
624		};
625
626		emac0: ethernet@40480000 {
627			reg = <0x40480000 0x4000>;
628			compatible = "nxp,s32-gmac";
629			interrupts = <105 0>, <106 0>, <107 0>, <108 0>;
630			interrupt-names = "common", "tx", "rx", "safety";
631			status = "disabled";
632		};
633
634		mdio0: mdio@40480200 {
635			reg = <0x40480200 0x8>;
636			compatible = "nxp,s32-gmac-mdio";
637			clocks = <&clock NXP_S32_AIPS_PLAT_CLK>;
638			#address-cells = <1>;
639			#size-cells = <0>;
640			status = "disabled";
641		};
642
643		edma0: dma-controller@4020c000 {
644			compatible = "nxp,mcux-edma";
645			nxp,version = <3>;
646			reg = <0x4020c000 0x3000>, <0x40280000 0x4000>, <0x40284000 0x4000>;
647			dma-channels = <32>;
648			dma-requests = <64>;
649			dmamux-reg-offset = <3>;
650			channel-gap = <12 127>;
651			#dma-cells = <2>;
652			nxp,mem2mem;
653			interrupts = <4 0>, <5 0>, <6 0>, <7 0>,
654				     <8 0>, <9 0>, <10 0>, <11 0>,
655				     <12 0>, <13 0>, <14 0>, <15 0>,
656				     <16 0>, <17 0>, <18 0>, <19 0>,
657				     <20 0>, <21 0>, <22 0>, <23 0>,
658				     <24 0>, <25 0>, <26 0>, <27 0>,
659				     <28 0>, <29 0>, <30 0>, <31 0>,
660				     <32 0>, <33 0>, <34 0>, <35 0>;
661			no-error-irq;
662			status = "disabled";
663		};
664
665		emios0: emios@40088000 {
666			compatible = "nxp,s32-emios";
667			reg = <0x40088000 0x4000>;
668			clocks = <&clock NXP_S32_EMIOS0_CLK>;
669			interrupts = <61 0>, <62 0>, <63 0>,
670					<64 0>, <65 0>, <66 0>;
671			interrupt-names = "0_0", "0_1", "0_2",
672					"0_3", "0_4", "0_5";
673			internal-cnt = <0xC101FF>;
674			status = "disabled";
675
676			master_bus {
677				emios0_bus_a: emios0_bus_a {
678					channel = <23>;
679					bus-type = "BUS_A";
680					channel-mask = <0x07FFFFF>;
681					status = "disabled";
682				};
683
684				emios0_bus_b: emios0_bus_b {
685					channel = <0>;
686					bus-type = "BUS_B";
687					channel-mask = <0x00000FE>;
688					status = "disabled";
689				};
690
691				emios0_bus_c: emios0_bus_c {
692					channel = <8>;
693					bus-type = "BUS_C";
694					channel-mask = <0x0000FE00>;
695					status = "disabled";
696				};
697
698				emios0_bus_d: emios0_bus_d {
699					channel = <16>;
700					bus-type = "BUS_D";
701					channel-mask = <0x00FE0000>;
702					status = "disabled";
703				};
704
705				emios0_bus_f: emios0_bus_f {
706					channel = <22>;
707					bus-type = "BUS_F";
708					channel-mask = <0x0BFFFFF>;
709					status = "disabled";
710				};
711			};
712
713			pwm {
714				compatible = "nxp,s32-emios-pwm";
715				#pwm-cells = <3>;
716				status = "disabled";
717			};
718		};
719
720		emios1: emios@4008c000 {
721			compatible = "nxp,s32-emios";
722			reg = <0x4008c000 0x4000>;
723			clocks = <&clock NXP_S32_EMIOS1_CLK>;
724			interrupts = <69 0>, <70 0>, <71 0>,
725					<72 0>, <73 0>, <74 0>;
726			interrupt-names = "1_0", "1_1", "1_2",
727					"1_3", "1_4", "1_5";
728			internal-cnt = <0xC10101>;
729			status = "disabled";
730
731			master_bus {
732				emios1_bus_a: emios1_bus_a {
733					channel = <23>;
734					bus-type = "BUS_A";
735					channel-mask = <0x07FFFFF>;
736					status = "disabled";
737				};
738
739				emios1_bus_b: emios1_bus_b {
740					channel = <0>;
741					bus-type = "BUS_B";
742					channel-mask = <0x00000FE>;
743					status = "disabled";
744				};
745
746				emios1_bus_c: emios1_bus_c {
747					channel = <8>;
748					bus-type = "BUS_C";
749					channel-mask = <0x0000FE00>;
750					status = "disabled";
751				};
752
753				emios1_bus_d: emios1_bus_d {
754					channel = <16>;
755					bus-type = "BUS_D";
756					channel-mask = <0x00FE0000>;
757					status = "disabled";
758				};
759
760				emios1_bus_f: emios1_bus_f {
761					channel = <22>;
762					channel-mask = <0x0BFFFFF>;
763					bus-type = "BUS_F";
764					status = "disabled";
765				};
766			};
767
768			pwm {
769				compatible = "nxp,s32-emios-pwm";
770				#pwm-cells = <3>;
771				status = "disabled";
772			};
773		};
774
775		emios2: emios@40090000 {
776			compatible = "nxp,s32-emios";
777			reg = <0x40090000 0x4000>;
778			clocks = <&clock NXP_S32_EMIOS2_CLK>;
779			interrupts = <77 0>, <78 0>, <79 0>,
780					<80 0>, <81 0>, <82 0>;
781			interrupt-names = "2_0", "2_1", "2_2",
782					"2_3", "2_4", "2_5";
783			internal-cnt = <0xC10101>;
784			status = "disabled";
785
786			master_bus {
787				emios2_bus_a: emios2_bus_a {
788					channel = <23>;
789					bus-type = "BUS_A";
790					channel-mask = <0x07FFFFF>;
791					status = "disabled";
792				};
793
794				emios2_bus_b: emios2_bus_b {
795					channel = <0>;
796					bus-type = "BUS_B";
797					channel-mask = <0x00000FE>;
798					status = "disabled";
799				};
800
801				emios2_bus_c: emios2_bus_c {
802					channel = <8>;
803					bus-type = "BUS_C";
804					channel-mask = <0x0000FE00>;
805					status = "disabled";
806				};
807
808				emios2_bus_d: emios2_bus_d {
809					channel = <16>;
810					bus-type = "BUS_D";
811					channel-mask = <0x00FE0000>;
812					status = "disabled";
813				};
814
815				emios2_bus_f: emios2_bus_f {
816					channel = <22>;
817					bus-type = "BUS_F";
818					channel-mask = <0x0BFFFFF>;
819					status = "disabled";
820				};
821			};
822
823			pwm {
824				compatible = "nxp,s32-emios-pwm";
825				#pwm-cells = <3>;
826				status = "disabled";
827			};
828		};
829
830		flexio0: flexio@40324000 {
831			compatible = "nxp,flexio";
832			reg = <0x40324000 0x4000>;
833			interrupts = <139 0>;
834			clocks = <&clock NXP_S32_FLEXIO0_CLK>;
835			status = "disabled";
836
837			flexio0_pwm {
838				compatible = "nxp,flexio-pwm";
839				#pwm-cells = <3>;
840				status = "disabled";
841			};
842		};
843
844		lcu0: lcu@40098000 {
845			compatible = "nxp,s32-lcu";
846			reg = <0x40098000 0x4000>;
847			status = "disabled";
848		};
849
850		lcu1: lcu@4009c000 {
851			compatible = "nxp,s32-lcu";
852			reg = <0x4009c000 0x4000>;
853			status = "disabled";
854		};
855
856		trgmux: trgmux@40080000 {
857			compatible = "nxp,s32-trgmux";
858			reg = <0x40080000 0x4000>;
859			status = "disabled";
860		};
861
862		pmc: pmc@402e8000 {
863			compatible = "nxp,s32k3-pmc";
864			reg = <0x402e8000 0x4000>;
865		};
866
867		mc_me: mc_me@402dc000 {
868			compatible = "nxp,s32-mc-me";
869			reg = <0x402dc000 0x4000>;
870		};
871
872		mc_rgm: mc_rgm@4028c000 {
873			compatible = "nxp,s32-mc-rgm";
874			reg = <0x4028c000 0x4000>;
875			func-reset-threshold = <0>;
876			dest-reset-threshold = <0>;
877		};
878
879		swt0: watchdog@40270000 {
880			compatible = "nxp,s32-swt";
881			reg = <0x40270000 0x4000>;
882			interrupts = <42 0>;
883			clocks = <&clock NXP_S32_SIRC_CLK>;
884			service-mode = "fixed";
885			status = "okay";
886		};
887
888		stm0: stm@40274000 {
889			compatible = "nxp,s32-sys-timer";
890			reg = <0x40274000 0x10000>;
891			interrupts = <39 0>;
892			clocks = <&clock NXP_S32_STM0_CLK>;
893			status = "disabled";
894		};
895
896		stm1: stm@40474000 {
897			compatible = "nxp,s32-sys-timer";
898			reg = <0x40474000 0x10000>;
899			interrupts = <40 0>;
900			clocks = <&clock NXP_S32_STM1_CLK>;
901			status = "disabled";
902		};
903	};
904};
905
906&nvic {
907	arm,num-irq-priority-bits = <4>;
908};
909