1/* 2 * Copyright (c) 2023 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <st/h5/stm32h5.dtsi> 8#include <zephyr/dt-bindings/flash_controller/ospi.h> 9/* keep both header files for compatibility */ 10#include <zephyr/dt-bindings/flash_controller/xspi.h> 11#include <mem.h> 12 13/ { 14 clocks { 15 /* The pll scheme is similar to stm32u5 */ 16 pll3: pll3 { 17 #clock-cells = <0>; 18 compatible = "st,stm32u5-pll-clock"; 19 status = "disabled"; 20 }; 21 }; 22 23 soc { 24 compatible = "st,stm32h562", "st,stm32h5", "simple-bus"; 25 26 pinctrl: pin-controller@42020000 { 27 gpioe: gpio@42021000 { 28 compatible = "st,stm32-gpio"; 29 gpio-controller; 30 #gpio-cells = <2>; 31 reg = <0x42021000 0x400>; 32 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; 33 }; 34 35 gpiof: gpio@42021400 { 36 compatible = "st,stm32-gpio"; 37 gpio-controller; 38 #gpio-cells = <2>; 39 reg = <0x42021400 0x400>; 40 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; 41 }; 42 43 gpiog: gpio@42021800 { 44 compatible = "st,stm32-gpio"; 45 gpio-controller; 46 #gpio-cells = <2>; 47 reg = <0x42021800 0x400>; 48 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; 49 }; 50 51 gpioi: gpio@42022000 { 52 compatible = "st,stm32-gpio"; 53 gpio-controller; 54 #gpio-cells = <2>; 55 reg = <0x42022000 0x400>; 56 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>; 57 }; 58 }; 59 60 sram1: memory@20000000 { 61 compatible = "zephyr,memory-region", "mmio-sram"; 62 reg = <0x20000000 DT_SIZE_K(256)>; 63 zephyr,memory-region = "SRAM1"; 64 }; 65 66 sram2: memory@20040000 { 67 compatible = "zephyr,memory-region", "mmio-sram"; 68 reg = <0x20040000 DT_SIZE_K(64)>; 69 zephyr,memory-region = "SRAM2"; 70 }; 71 72 sram3: memory@20050000 { 73 compatible = "zephyr,memory-region", "mmio-sram"; 74 reg = <0x20050000 DT_SIZE_K(320)>; 75 zephyr,memory-region = "SRAM3"; 76 }; 77 78 backup_sram: memory@40036400 { 79 reg = <0x40036400 DT_SIZE_K(4)>; 80 }; 81 82 lptim3: timers@44004800 { 83 compatible = "st,stm32-lptim"; 84 clocks = <&rcc STM32_CLOCK(APB3, 12U)>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 reg = <0x44004800 0x400>; 88 interrupts = <127 1>; 89 interrupt-names = "wakeup"; 90 status = "disabled"; 91 }; 92 93 lptim4: timers@44004c00 { 94 compatible = "st,stm32-lptim"; 95 clocks = <&rcc STM32_CLOCK(APB3, 13U)>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 reg = <0x44004c00 0x400>; 99 interrupts = <128 1>; 100 interrupt-names = "wakeup"; 101 status = "disabled"; 102 }; 103 104 lptim5: timers@44005000 { 105 compatible = "st,stm32-lptim"; 106 clocks = <&rcc STM32_CLOCK(APB3, 14U)>; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 reg = <0x44005000 0x400>; 110 interrupts = <129 1>; 111 interrupt-names = "wakeup"; 112 status = "disabled"; 113 }; 114 115 lptim6: timers@44005400 { 116 compatible = "st,stm32-lptim"; 117 clocks = <&rcc STM32_CLOCK(APB3, 15U)>; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 reg = <0x44005400 0x400>; 121 interrupts = <130 1>; 122 interrupt-names = "wakeup"; 123 status = "disabled"; 124 }; 125 126 uart4: serial@40004c00 { 127 compatible = "st,stm32-uart"; 128 reg = <0x40004c00 0x400>; 129 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 130 resets = <&rctl STM32_RESET(APB1L, 19U)>; 131 interrupts = <61 0>; 132 status = "disabled"; 133 }; 134 135 uart5: serial@40005000 { 136 compatible = "st,stm32-uart"; 137 reg = <0x40005000 0x400>; 138 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 139 resets = <&rctl STM32_RESET(APB1L, 20U)>; 140 interrupts = <62 0>; 141 status = "disabled"; 142 }; 143 144 uart7: serial@40007800 { 145 compatible = "st,stm32-uart"; 146 reg = <0x40007800 0x400>; 147 clocks = <&rcc STM32_CLOCK(APB1, 30U)>; 148 resets = <&rctl STM32_RESET(APB1L, 30U)>; 149 interrupts = <98 0>; 150 status = "disabled"; 151 }; 152 153 uart8: serial@40007c00 { 154 compatible = "st,stm32-uart"; 155 reg = <0x40007c00 0x400>; 156 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 157 resets = <&rctl STM32_RESET(APB1L, 31U)>; 158 interrupts = <99 0>; 159 status = "disabled"; 160 }; 161 162 uart9: serial@40008000 { 163 compatible = "st,stm32-uart"; 164 reg = <0x40008000 0x400>; 165 clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; 166 resets = <&rctl STM32_RESET(APB1H, 0U)>; 167 interrupts = <100 0>; 168 status = "disabled"; 169 }; 170 171 usart6: serial@40006400 { 172 compatible = "st,stm32-usart", "st,stm32-uart"; 173 reg = <0x40006400 0x400>; 174 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; 175 resets = <&rctl STM32_RESET(APB1L, 25U)>; 176 interrupts = <85 0>; 177 status = "disabled"; 178 }; 179 180 usart10: serial@40006800 { 181 compatible = "st,stm32-usart", "st,stm32-uart"; 182 reg = <0x40006800 0x400>; 183 clocks = <&rcc STM32_CLOCK(APB1, 26U)>; 184 resets = <&rctl STM32_RESET(APB1L, 26U)>; 185 interrupts = <86 0>; 186 status = "disabled"; 187 }; 188 189 usart11: serial@40006c00 { 190 compatible = "st,stm32-usart", "st,stm32-uart"; 191 reg = <0x40006c00 0x400>; 192 clocks = <&rcc STM32_CLOCK(APB1, 27U)>; 193 resets = <&rctl STM32_RESET(APB1L, 27U)>; 194 interrupts = <87 0>; 195 status = "disabled"; 196 }; 197 198 uart12: serial@40008400 { 199 compatible = "st,stm32-uart"; 200 reg = <0x40008400 0x400>; 201 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>; 202 resets = <&rctl STM32_RESET(APB1H, 1U)>; 203 interrupts = <101 0>; 204 status = "disabled"; 205 }; 206 207 i2c3: i2c@44002800 { 208 compatible = "st,stm32-i2c-v2"; 209 clock-frequency = <I2C_BITRATE_STANDARD>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 reg = <0x44002800 0x400>; 213 clocks = <&rcc STM32_CLOCK(APB3, 7U)>; 214 interrupts = <80 0>, <81 0>; 215 interrupt-names = "event", "error"; 216 status = "disabled"; 217 }; 218 219 i2c4: i2c@44002c00 { 220 compatible = "st,stm32-i2c-v2"; 221 clock-frequency = <I2C_BITRATE_STANDARD>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 reg = <0x44002c00 0x400>; 225 clocks = <&rcc STM32_CLOCK(APB3, 8U)>; 226 interrupts = <125 0>, <126 0>; 227 interrupt-names = "event", "error"; 228 status = "disabled"; 229 }; 230 231 spi4: spi@40014c00 { 232 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0x40014c00 0x400>; 236 interrupts = <82 5>; 237 clocks = <&rcc STM32_CLOCK(APB2, 19U)>; 238 status = "disabled"; 239 }; 240 241 spi5: spi@44002000 { 242 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 reg = <0x44002000 0x400>; 246 interrupts = <83 5>; 247 clocks = <&rcc STM32_CLOCK(APB3, 5U)>; 248 status = "disabled"; 249 }; 250 251 spi6: spi@40015000 { 252 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 reg = <0x40015000 0x400>; 256 interrupts = <84 5>; 257 clocks = <&rcc STM32_CLOCK(APB2, 20U)>; 258 status = "disabled"; 259 }; 260 261 xspi1: spi@47001400 { 262 compatible = "st,stm32-xspi"; 263 reg = <0x47001400 0x400>; 264 interrupts = <78 0>; 265 clock-names = "xspix", "xspi-ker"; 266 clocks = <&rcc STM32_CLOCK(AHB4, 20U)>, 267 <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 adc2: adc@42028100 { 274 compatible = "st,stm32-adc"; 275 reg = <0x42028100 0x400>; 276 clocks = <&rcc STM32_CLOCK(AHB2, 10U)>; 277 interrupts = <69 0>; 278 status = "disabled"; 279 vref-mv = <3300>; 280 #io-channel-cells = <1>; 281 resolutions = <STM32_ADC_RES(12, 0x00) 282 STM32_ADC_RES(10, 0x01) 283 STM32_ADC_RES(8, 0x02) 284 STM32_ADC_RES(6, 0x03)>; 285 sampling-times = <3 7 13 25 48 93 248 641>; 286 st,adc-sequencer = "FULLY_CONFIGURABLE"; 287 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 288 }; 289 290 timers4: timers@40000800 { 291 compatible = "st,stm32-timers"; 292 reg = <0x40000800 0x400>; 293 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 294 resets = <&rctl STM32_RESET(APB1L, 2U)>; 295 interrupts = <47 0>; 296 interrupt-names = "global"; 297 status = "disabled"; 298 299 pwm { 300 compatible = "st,stm32-pwm"; 301 status = "disabled"; 302 #pwm-cells = <3>; 303 }; 304 305 counter { 306 compatible = "st,stm32-counter"; 307 status = "disabled"; 308 }; 309 }; 310 311 timers5: timers@40000c00 { 312 compatible = "st,stm32-timers"; 313 reg = <0x40000c00 0x400>; 314 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 315 resets = <&rctl STM32_RESET(APB1L, 3U)>; 316 interrupts = <48 0>; 317 interrupt-names = "global"; 318 status = "disabled"; 319 320 pwm { 321 compatible = "st,stm32-pwm"; 322 status = "disabled"; 323 #pwm-cells = <3>; 324 }; 325 326 counter { 327 compatible = "st,stm32-counter"; 328 status = "disabled"; 329 }; 330 }; 331 332 timers8: timers@40013400 { 333 compatible = "st,stm32-timers"; 334 reg = <0x40013400 0x400>; 335 clocks = <&rcc STM32_CLOCK(APB2, 13)>; 336 resets = <&rctl STM32_RESET(APB2, 13)>; 337 interrupts = <65 0>, <66 0>, <67 0>, <68 0>; 338 interrupt-names = "brk", "up", "trgcom", "cc"; 339 status = "disabled"; 340 341 pwm { 342 compatible = "st,stm32-pwm"; 343 status = "disabled"; 344 #pwm-cells = <3>; 345 }; 346 }; 347 348 timers12: timers@40001800 { 349 compatible = "st,stm32-timers"; 350 reg = <0x40001800 0x400>; 351 clocks = <&rcc STM32_CLOCK(APB1, 6U)>; 352 resets = <&rctl STM32_RESET(APB1L, 6U)>; 353 interrupts = <120 0>; 354 interrupt-names = "global"; 355 status = "disabled"; 356 357 pwm { 358 compatible = "st,stm32-pwm"; 359 status = "disabled"; 360 #pwm-cells = <3>; 361 }; 362 363 counter { 364 compatible = "st,stm32-counter"; 365 status = "disabled"; 366 }; 367 }; 368 369 timers13: timers@40001c00 { 370 compatible = "st,stm32-timers"; 371 reg = <0x40001c00 0x400>; 372 clocks = <&rcc STM32_CLOCK(APB1, 7U)>; 373 resets = <&rctl STM32_RESET(APB1L, 7U)>; 374 interrupts = <121 0>; 375 interrupt-names = "global"; 376 status = "disabled"; 377 378 pwm { 379 compatible = "st,stm32-pwm"; 380 status = "disabled"; 381 #pwm-cells = <3>; 382 }; 383 384 counter { 385 compatible = "st,stm32-counter"; 386 status = "disabled"; 387 }; 388 }; 389 390 timers14: timers@40002000 { 391 compatible = "st,stm32-timers"; 392 reg = <0x40002000 0x400>; 393 clocks = <&rcc STM32_CLOCK(APB1, 8U)>; 394 resets = <&rctl STM32_RESET(APB1L, 8U)>; 395 interrupts = <122 0>; 396 interrupt-names = "global"; 397 status = "disabled"; 398 399 pwm { 400 compatible = "st,stm32-pwm"; 401 status = "disabled"; 402 #pwm-cells = <3>; 403 }; 404 405 counter { 406 compatible = "st,stm32-counter"; 407 status = "disabled"; 408 }; 409 }; 410 411 timers15: timers@40014000 { 412 compatible = "st,stm32-timers"; 413 reg = <0x40014000 0x400>; 414 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 415 resets = <&rctl STM32_RESET(APB2, 16U)>; 416 interrupts = <71 0>; 417 interrupt-names = "global"; 418 status = "disabled"; 419 420 pwm { 421 compatible = "st,stm32-pwm"; 422 status = "disabled"; 423 #pwm-cells = <3>; 424 }; 425 426 counter { 427 compatible = "st,stm32-counter"; 428 status = "disabled"; 429 }; 430 }; 431 432 timers16: timers@40014400 { 433 compatible = "st,stm32-timers"; 434 reg = <0x40014400 0x400>; 435 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 436 resets = <&rctl STM32_RESET(APB2, 17U)>; 437 interrupts = <72 0>; 438 interrupt-names = "global"; 439 status = "disabled"; 440 441 pwm { 442 compatible = "st,stm32-pwm"; 443 status = "disabled"; 444 #pwm-cells = <3>; 445 }; 446 447 counter { 448 compatible = "st,stm32-counter"; 449 status = "disabled"; 450 }; 451 }; 452 453 timers17: timers@40014800 { 454 compatible = "st,stm32-timers"; 455 reg = <0x40014800 0x400>; 456 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 457 resets = <&rctl STM32_RESET(APB2, 18U)>; 458 interrupts = <73 0>; 459 interrupt-names = "global"; 460 status = "disabled"; 461 462 pwm { 463 compatible = "st,stm32-pwm"; 464 status = "disabled"; 465 #pwm-cells = <3>; 466 }; 467 468 counter { 469 compatible = "st,stm32-counter"; 470 status = "disabled"; 471 }; 472 }; 473 474 aes: aes@420c0000 { 475 compatible = "st,stm32-aes"; 476 reg = <0x420c0000 0x400>; 477 clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; 478 resets = <&rctl STM32_RESET(AHB2, 16U)>; 479 interrupts = <116 0>; 480 status = "disabled"; 481 }; 482 483 fdcan2: can@4000a800 { 484 compatible = "st,stm32-fdcan"; 485 reg = <0x4000a800 0x400>, <0x4000ac00 0x6a0>; 486 reg-names = "m_can", "message_ram"; 487 interrupts = <109 0>, <110 0>; 488 interrupt-names = "int0", "int1"; 489 /* common clock FDCAN 1 & 2 */ 490 clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>; 491 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; 492 status = "disabled"; 493 }; 494 495 sdmmc1: sdmmc@46008000 { 496 compatible = "st,stm32-sdmmc"; 497 reg = <0x46008000 0x400>; 498 clocks = <&rcc STM32_CLOCK(AHB4, 11U)>, 499 <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>; 500 resets = <&rctl STM32_RESET(AHB4, 11U)>; 501 interrupts = <79 0>; 502 status = "disabled"; 503 }; 504 505 fmc: memory-controller@47000400 { 506 compatible = "st,stm32-fmc"; 507 reg = <0x47000400 0x400>; 508 clocks = <&rcc STM32_CLOCK(AHB4, 16U)>; 509 status = "disabled"; 510 }; 511 }; 512 513 smbus3: smbus3 { 514 compatible = "st,stm32-smbus"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 i2c = <&i2c3>; 518 status = "disabled"; 519 }; 520 521 smbus4: smbus4 { 522 compatible = "st,stm32-smbus"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 i2c = <&i2c4>; 526 status = "disabled"; 527 }; 528}; 529
