1 /*
2 * Copyright (c) 2024, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_qtmr_pwm
8
9 #include <errno.h>
10 #include <zephyr/drivers/pwm.h>
11 #include <fsl_qtmr.h>
12 #include <fsl_clock.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/drivers/clock_control.h>
15 #include <zephyr/kernel.h>
16
17 #include <zephyr/logging/log.h>
18
19 LOG_MODULE_REGISTER(pwm_mcux_qtmr, CONFIG_PWM_LOG_LEVEL);
20
21 #define CHANNEL_COUNT TMR_CNTR_COUNT
22
23 struct pwm_mcux_qtmr_config {
24 TMR_Type *base;
25 uint32_t prescaler;
26 const struct pinctrl_dev_config *pincfg;
27 const struct device *clock_dev;
28 clock_control_subsys_t clock_subsys;
29 };
30
31 struct pwm_mcux_qtmr_data {
32 struct k_mutex lock;
33 };
34
mcux_qtmr_pwm_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)35 static int mcux_qtmr_pwm_set_cycles(const struct device *dev, uint32_t channel,
36 uint32_t period_cycles, uint32_t pulse_cycles,
37 pwm_flags_t flags)
38 {
39 const struct pwm_mcux_qtmr_config *config = dev->config;
40 struct pwm_mcux_qtmr_data *data = dev->data;
41 uint32_t periodCount, highCount, lowCount;
42 uint16_t reg;
43
44 if (channel >= CHANNEL_COUNT) {
45 LOG_ERR("Invalid channel");
46 return -EINVAL;
47 }
48
49 /* Counter values to generate a PWM signal */
50 periodCount = period_cycles;
51 highCount = pulse_cycles;
52 lowCount = period_cycles - pulse_cycles;
53
54 if (highCount > 0U) {
55 highCount -= 1U;
56 }
57 if (lowCount > 0U) {
58 lowCount -= 1U;
59 }
60
61 if ((highCount > 0xFFFFU) || (lowCount > 0xFFFFU)) {
62 /* This should not be a 16-bit overflow value. If it is, change to a larger divider
63 * for clock source.
64 */
65 return -EINVAL;
66 }
67
68 k_mutex_lock(&data->lock, K_FOREVER);
69
70 /* Set OFLAG pin for output mode and force out a low on the pin */
71 config->base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK);
72
73 QTMR_StopTimer(config->base, channel);
74
75 /* Setup the compare registers for PWM output */
76 config->base->CHANNEL[channel].COMP1 = (uint16_t)lowCount;
77 config->base->CHANNEL[channel].COMP2 = (uint16_t)highCount;
78
79 /* Setup the pre-load registers for PWM output */
80 config->base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount;
81 config->base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount;
82
83 reg = config->base->CHANNEL[channel].CSCTRL;
84 /* Setup the compare load control for COMP1 and COMP2.
85 * Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted
86 */
87 reg &= (uint16_t)(~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK));
88 reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1));
89 config->base->CHANNEL[channel].CSCTRL = reg;
90
91 reg = config->base->CHANNEL[channel].CTRL;
92 reg &= ~(uint16_t)TMR_CTRL_OUTMODE_MASK;
93 if (highCount == periodCount) {
94 /* Set OFLAG output on compare */
95 reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_SetOnCompare));
96 } else if (periodCount == 0U) {
97 /* Clear OFLAG output on compare */
98 reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ClearOnCompare));
99 } else {
100 /* Toggle OFLAG output using alternating compare register */
101 reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg));
102 }
103
104 config->base->CHANNEL[channel].CTRL = reg;
105
106 QTMR_StartTimer(config->base, channel, kQTMR_PriSrcRiseEdge);
107
108 k_mutex_unlock(&data->lock);
109
110 return 0;
111 }
112
mcux_qtmr_pwm_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)113 static int mcux_qtmr_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel,
114 uint64_t *cycles)
115 {
116 const struct pwm_mcux_qtmr_config *config = dev->config;
117 uint32_t clock_freq;
118
119 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq)) {
120 return -EINVAL;
121 }
122
123 *cycles = clock_freq / config->prescaler;
124
125 return 0;
126 }
127
mcux_qtmr_pwm_init(const struct device * dev)128 static int mcux_qtmr_pwm_init(const struct device *dev)
129 {
130 const struct pwm_mcux_qtmr_config *config = dev->config;
131 struct pwm_mcux_qtmr_data *data = dev->data;
132 qtmr_config_t qtmr_config;
133 int err;
134
135 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
136 if (err) {
137 return err;
138 }
139
140 k_mutex_init(&data->lock);
141
142 QTMR_GetDefaultConfig(&qtmr_config);
143 qtmr_config.primarySource = kQTMR_ClockDivide_1 + (31 - __builtin_clz(config->prescaler));
144
145 for (int i = 0; i < CHANNEL_COUNT; i++) {
146 QTMR_Init(config->base, i, &qtmr_config);
147 }
148
149 return 0;
150 }
151
152 static DEVICE_API(pwm, pwm_mcux_qtmr_driver_api) = {
153 .set_cycles = mcux_qtmr_pwm_set_cycles,
154 .get_cycles_per_sec = mcux_qtmr_pwm_get_cycles_per_sec,
155 };
156
157 #define PWM_MCUX_QTMR_DEVICE_INIT(n) \
158 PINCTRL_DT_INST_DEFINE(n); \
159 static struct pwm_mcux_qtmr_data pwm_mcux_qtmr_data_##n; \
160 \
161 static const struct pwm_mcux_qtmr_config pwm_mcux_qtmr_config_##n = { \
162 .base = (TMR_Type *)DT_INST_REG_ADDR(n), \
163 .prescaler = DT_INST_PROP(n, prescaler), \
164 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
165 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
166 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
167 }; \
168 \
169 DEVICE_DT_INST_DEFINE(n, mcux_qtmr_pwm_init, NULL, &pwm_mcux_qtmr_data_##n, \
170 &pwm_mcux_qtmr_config_##n, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
171 &pwm_mcux_qtmr_driver_api);
172
173 DT_INST_FOREACH_STATUS_OKAY(PWM_MCUX_QTMR_DEVICE_INIT)
174
