1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/**
8 * @file
9 * @brief MCXW72 Platform-Specific Initialization
10 *
11 * When compared to MCXW71, the Ram Banks with ECC
12 * are located in different addresses.
13 *
14 * MCXW72 SOC reset code that initializes RAM
15 * to prevent ECC causing faults, and calls SystemInit
16 */
17
18#include <zephyr/toolchain.h>
19#include <zephyr/linker/sections.h>
20
21_ASM_FILE_PROLOGUE
22
23GTEXT(soc_reset_hook)
24SECTION_SUBSEC_FUNC(TEXT,_reset_section,soc_reset_hook)
25
26.soc_reset_hook:
27    ldr r0, =0x14000000
28    ldr r1, =.ram_init_ctcm01
29    bics r1, #0x10000000
30    cmp r0, r1
31    bcc .ram_init_done
32.ram_init_ctcm01: /* Initialize ctcm01 */
33    ldr r0, =0x14000000
34    ldr r1, =0x14008000
35    ldr r2, =0
36    ldr r3, =0
37    ldr r4, =0
38    ldr r5, =0
39.loop01:
40    stmia r0!, {r2 - r5}
41    cmp r0, r1
42    bcc.n .loop01
43.ram_init_stcm012: /* Initialize stcm012 */
44    ldr r0, =0x30000000
45    ldr r1, =0x30010000
46.loop012:
47    stmia r0!, {r2 - r5}
48    cmp r0, r1
49    bcc.n .loop012
50.ram_init_stcm8:
51    ldr r0, =0x30038000
52    ldr r1, =0x3003a000
53.loop8: /* Initialize stcm5 */
54    stmia r0!, {r2 - r5}
55    cmp r0, r1
56    bcc.n .loop8
57.ram_init_done:
58    b SystemInit
59