1/*
2 * Copyright (c) 2021 Katsuhiro Suzuki
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/gpio/gpio.h>
8#include <freq.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13	compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
14	model = "sifive,FU540";
15
16	clocks {
17		coreclk: core-clk {
18			#clock-cells = <0>;
19			compatible = "fixed-clock";
20			clock-frequency = <DT_FREQ_M(1000)>;
21		};
22
23		tlclk: tl-clk {
24			#clock-cells = <0>;
25			compatible = "fixed-factor-clock";
26			clocks = <&coreclk>;
27			clock-div = <2>;
28		};
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu@0 {
36			compatible = "sifive,e51", "riscv";
37			device_type = "cpu";
38			i-cache-line-size = <0x4000>;
39			reg = <0x0>;
40			riscv,isa = "rv64imac_zicsr_zifencei";
41			hlic0: interrupt-controller {
42				compatible = "riscv,cpu-intc";
43				#address-cells = <0>;
44				#interrupt-cells = <1>;
45				interrupt-controller;
46			};
47		};
48
49		cpu@1 {
50			compatible = "sifive,u54", "riscv";
51			device_type = "cpu";
52			mmu-type = "riscv,sv39";
53			i-cache-line-size = <0x8000>;
54			d-cache-line-size = <0x8000>;
55			reg = <0x1>;
56			riscv,isa = "rv64gc";
57			hlic1: interrupt-controller {
58				compatible = "riscv,cpu-intc";
59				#address-cells = <0>;
60				#interrupt-cells = <1>;
61				interrupt-controller;
62			};
63		};
64
65		cpu@2 {
66			clock-frequency = <0>;
67			compatible = "sifive,u54", "riscv";
68			device_type = "cpu";
69			mmu-type = "riscv,sv39";
70			i-cache-line-size = <0x8000>;
71			d-cache-line-size = <0x8000>;
72			reg = <0x2>;
73			riscv,isa = "rv64gc";
74			hlic2: interrupt-controller {
75				compatible = "riscv,cpu-intc";
76				#address-cells = <0>;
77				#interrupt-cells = <1>;
78				interrupt-controller;
79			};
80		};
81
82		cpu@3 {
83			clock-frequency = <0>;
84			compatible = "sifive,u54", "riscv";
85			device_type = "cpu";
86			mmu-type = "riscv,sv39";
87			i-cache-line-size = <0x8000>;
88			d-cache-line-size = <0x8000>;
89			reg = <0x3>;
90			riscv,isa = "rv64gc";
91			hlic3: interrupt-controller {
92				compatible = "riscv,cpu-intc";
93				#address-cells = <0>;
94				#interrupt-cells = <1>;
95				interrupt-controller;
96			};
97		};
98
99		cpu@4 {
100			clock-frequency = <0>;
101			compatible = "sifive,u54", "riscv";
102			device_type = "cpu";
103			mmu-type = "riscv,sv39";
104			i-cache-line-size = <0x8000>;
105			d-cache-line-size = <0x8000>;
106			reg = <0x4>;
107			riscv,isa = "rv64gc";
108			hlic4: interrupt-controller {
109				compatible = "riscv,cpu-intc";
110				#address-cells = <0>;
111				#interrupt-cells = <1>;
112				interrupt-controller;
113			};
114		};
115	};
116
117	soc {
118		#address-cells = <1>;
119		#size-cells = <1>;
120		compatible = "fu540-soc", "sifive-soc", "simple-bus";
121		ranges;
122
123		modeselect: rom@1000 {
124			compatible = "sifive,modeselect0";
125			reg = <0x1000 0x1000>;
126			reg-names = "mem";
127		};
128
129		maskrom: rom@10000 {
130			compatible = "sifive,maskrom0";
131			reg = <0x10000 0x8000>;
132			reg-names = "mem";
133		};
134
135		dtim: dtim@1000000 {
136			compatible = "sifive,dtim0";
137			reg = <0x1000000 0x2000>;
138			reg-names = "mem";
139		};
140
141		itim0: itim0@1800000 {
142			compatible = "sifive,itim0";
143			reg = <0x1800000 0x2000>;
144			reg-names = "mem";
145		};
146
147		itim1: itim1@1808000 {
148			compatible = "sifive,itim0";
149			reg = <0x1808000 0x7000>;
150			reg-names = "mem";
151		};
152
153		itim2: itim2@1810000 {
154			compatible = "sifive,itim0";
155			reg = <0x1810000 0x7000>;
156			reg-names = "mem";
157		};
158
159		itim3: itim3@1818000 {
160			compatible = "sifive,itim0";
161			reg = <0x1818000 0x7000>;
162			reg-names = "mem";
163		};
164
165		itim4: itim4@1820000 {
166			compatible = "sifive,itim0";
167			reg = <0x1820000 0x7000>;
168			reg-names = "mem";
169		};
170
171
172		clint: clint@2000000 {
173			compatible = "sifive,clint0";
174			interrupts-extended = <&hlic0 3 &hlic0 7
175							&hlic1 3 &hlic1 7
176							&hlic2 3 &hlic2 7
177							&hlic3 3 &hlic3 7
178							&hlic4 3 &hlic4 7>;
179			interrupt-names = "soft0", "timer0", "soft1", "timer1",
180							"soft2", "timer2", "soft3", "timer3",
181							"soft4", "timer4";
182			reg = <0x2000000 0x10000>;
183		};
184
185		mtimer: timer@200bff8 {
186			compatible = "riscv,machine-timer";
187			interrupts-extended = <&hlic0 7
188						&hlic1 7
189						&hlic2 7
190						&hlic3 7
191						&hlic4 7>;
192			reg = <0x200bff8 0x8 0x2004000 0x8>;
193			reg-names = "mtime", "mtimecmp";
194		};
195
196		l2lim: l2lim@8000000 {
197			compatible = "sifive,l2lim0";
198			reg = <0x8000000 0x2000000>;
199			reg-names = "mem";
200		};
201
202		plic: interrupt-controller@c000000 {
203			compatible = "sifive,plic-1.0.0";
204			#interrupt-cells = <2>;
205			#address-cells = <1>;
206			interrupt-controller;
207			interrupts-extended = <&hlic0 11
208							&hlic1 11 &hlic1 9
209							&hlic2 11 &hlic2 9
210							&hlic3 11 &hlic3 9
211							&hlic4 11 &hlic4 9>;
212			reg = <0x0c000000 0x04000000>;
213			riscv,max-priority = <7>;
214			riscv,ndev = <52>;
215		};
216
217		uart0: serial@10010000 {
218			compatible = "sifive,uart0";
219			interrupt-parent = <&plic>;
220			interrupts = <4 1>;
221			reg = <0x10010000 0x1000>;
222			reg-names = "control";
223			status = "disabled";
224		};
225
226		uart1: serial@10011000 {
227			compatible = "sifive,uart0";
228			interrupt-parent = <&plic>;
229			interrupts = <5 1>;
230			reg = <0x10011000 0x1000>;
231			reg-names = "control";
232			status = "disabled";
233		};
234
235		spi0: spi@10040000 {
236			compatible = "sifive,spi0";
237			interrupt-parent = <&plic>;
238			interrupts = <51 1>;
239			reg = <0x10040000 0x1000 0x20000000 0x10000000>;
240			reg-names = "control", "mem";
241			status = "disabled";
242			#address-cells = <1>;
243			#size-cells = <0>;
244		};
245
246		spi1: spi@10041000 {
247			compatible = "sifive,spi0";
248			interrupt-parent = <&plic>;
249			interrupts = <52 1>;
250			reg = <0x10041000 0x1000>;
251			reg-names = "control";
252			status = "disabled";
253			#address-cells = <1>;
254			#size-cells = <0>;
255		};
256
257		spi2: spi@10050000 {
258			compatible = "sifive,spi0";
259			interrupt-parent = <&plic>;
260			interrupts = <6 1>;
261			reg = <0x10050000 0x1000>;
262			reg-names = "control";
263			status = "disabled";
264			#address-cells = <1>;
265			#size-cells = <0>;
266		};
267
268		gpio0: gpio@10060000 {
269			compatible = "sifive,gpio0";
270			gpio-controller;
271			ngpios = <16>;
272			interrupt-parent = <&plic>;
273			interrupts = <7 1>, <8 1>, <9 1>, <10 1>,
274				<11 1>, <12 1>, <13 1>, <14 1>,
275				<15 1>, <16 1>, <17 1>, <18 1>,
276				<19 1>, <20 1>, <21 1>, <22 1>;
277			reg = <0x10060000 0x1000>;
278			reg-names = "control";
279			status = "disabled";
280			#gpio-cells = <2>;
281
282			#address-cells = <1>;
283			#size-cells = <1>;
284			ranges;
285		};
286	};
287};
288