1 /*
2 * Copyright 2017, 2024-2025 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_ccm
8 #include <errno.h>
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/sys/util.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/dt-bindings/clock/imx_ccm.h>
13 #include <fsl_clock.h>
14
15 #if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
16 #include <main/ipc.h>
17 #endif
18
19 #define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
20 #include <zephyr/logging/log.h>
21 LOG_MODULE_REGISTER(clock_control);
22
23 #ifdef CONFIG_SPI_MCUX_LPSPI
24 static const clock_name_t lpspi_clocks[] = {
25 kCLOCK_Usb1PllPfd1Clk,
26 kCLOCK_Usb1PllPfd0Clk,
27 kCLOCK_SysPllClk,
28 kCLOCK_SysPllPfd2Clk,
29 };
30 #endif
31 #ifdef CONFIG_UART_MCUX_IUART
32 static const clock_root_control_t uart_clk_root[] = {
33 kCLOCK_RootUart1,
34 kCLOCK_RootUart2,
35 kCLOCK_RootUart3,
36 kCLOCK_RootUart4,
37 };
38
39 static const clock_ip_name_t uart_clocks[] = {
40 kCLOCK_Uart1,
41 kCLOCK_Uart2,
42 kCLOCK_Uart3,
43 kCLOCK_Uart4,
44 };
45 #endif
46
47 #ifdef CONFIG_UART_MCUX_LPUART
48
49 #ifdef CONFIG_SOC_MIMX8QM6_ADSP
50 static const clock_ip_name_t lpuart_clocks[] = {
51 kCLOCK_DMA_Lpuart0,
52 kCLOCK_DMA_Lpuart1,
53 kCLOCK_DMA_Lpuart2,
54 kCLOCK_DMA_Lpuart3,
55 kCLOCK_DMA_Lpuart4,
56 };
57
58 static const uint32_t lpuart_rate = MHZ(80);
59 #endif /* CONFIG_SOC_MIMX8QM6_ADSP */
60
61 #ifdef CONFIG_SOC_MIMX8QX6_ADSP
62 static const clock_ip_name_t lpuart_clocks[] = {
63 kCLOCK_DMA_Lpuart0,
64 kCLOCK_DMA_Lpuart1,
65 kCLOCK_DMA_Lpuart2,
66 kCLOCK_DMA_Lpuart3,
67 };
68
69 static const uint32_t lpuart_rate = MHZ(80);
70 #endif /* CONFIG_SOC_MIMX8QX6_ADSP */
71
72 #endif /* CONFIG_UART_MCUX_LPUART */
73
74 #ifdef CONFIG_DAI_NXP_SAI
75 #if defined(CONFIG_SOC_MIMX8QX6_ADSP) || defined(CONFIG_SOC_MIMX8QM6_ADSP)
76 static const clock_ip_name_t sai_clocks[] = {
77 kCLOCK_AUDIO_Sai1,
78 kCLOCK_AUDIO_Sai2,
79 kCLOCK_AUDIO_Sai3,
80 };
81 #endif
82 #endif /* CONFIG_DAI_NXP_SAI */
83
84 #if defined(CONFIG_I2C_NXP_II2C)
85 static const clock_ip_name_t i2c_clk_root[] = {
86 kCLOCK_RootI2c1,
87 kCLOCK_RootI2c2,
88 kCLOCK_RootI2c3,
89 kCLOCK_RootI2c4,
90 #ifdef CONFIG_SOC_MIMX8ML8
91 kCLOCK_RootI2c5,
92 kCLOCK_RootI2c6,
93 #endif
94 };
95 #endif
96
mcux_ccm_on(const struct device * dev,clock_control_subsys_t sub_system)97 static int mcux_ccm_on(const struct device *dev,
98 clock_control_subsys_t sub_system)
99 {
100 uint32_t clock_name = (uintptr_t)sub_system;
101 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
102
103 switch (clock_name) {
104 #ifdef CONFIG_UART_MCUX_IUART
105 case IMX_CCM_UART1_CLK:
106 case IMX_CCM_UART2_CLK:
107 case IMX_CCM_UART3_CLK:
108 case IMX_CCM_UART4_CLK:
109 CLOCK_EnableClock(uart_clocks[instance]);
110 return 0;
111 #endif
112
113 #if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QM6_ADSP)
114 case IMX_CCM_LPUART1_CLK:
115 case IMX_CCM_LPUART2_CLK:
116 case IMX_CCM_LPUART3_CLK:
117 case IMX_CCM_LPUART4_CLK:
118 case IMX_CCM_LPUART5_CLK:
119 CLOCK_EnableClock(lpuart_clocks[instance]);
120 return 0;
121 #endif
122
123 #if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QX6_ADSP)
124 case IMX_CCM_LPUART1_CLK:
125 case IMX_CCM_LPUART2_CLK:
126 case IMX_CCM_LPUART3_CLK:
127 case IMX_CCM_LPUART4_CLK:
128 CLOCK_EnableClock(lpuart_clocks[instance]);
129 return 0;
130 #endif
131
132 #ifdef CONFIG_DAI_NXP_SAI
133 #if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
134 case IMX_CCM_SAI1_CLK:
135 case IMX_CCM_SAI2_CLK:
136 case IMX_CCM_SAI3_CLK:
137 CLOCK_EnableClock(sai_clocks[instance]);
138 return 0;
139 #endif
140 #endif /* CONFIG_DAI_NXP_SAI */
141
142 #if defined(CONFIG_ETH_NXP_ENET)
143 #ifdef CONFIG_SOC_SERIES_IMX8M
144 #define ENET_CLOCK kCLOCK_Enet1
145 #else
146 #define ENET_CLOCK kCLOCK_Enet
147 #endif
148 case IMX_CCM_ENET_CLK:
149 CLOCK_EnableClock(ENET_CLOCK);
150 return 0;
151 #endif
152 default:
153 (void)instance;
154 return 0;
155 }
156 }
157
mcux_ccm_off(const struct device * dev,clock_control_subsys_t sub_system)158 static int mcux_ccm_off(const struct device *dev,
159 clock_control_subsys_t sub_system)
160 {
161 uint32_t clock_name = (uintptr_t)sub_system;
162 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
163
164 switch (clock_name) {
165 #ifdef CONFIG_UART_MCUX_IUART
166 case IMX_CCM_UART1_CLK:
167 case IMX_CCM_UART2_CLK:
168 case IMX_CCM_UART3_CLK:
169 case IMX_CCM_UART4_CLK:
170 CLOCK_DisableClock(uart_clocks[instance]);
171 return 0;
172 #endif
173
174 #ifdef CONFIG_DAI_NXP_SAI
175 #if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
176 case IMX_CCM_SAI1_CLK:
177 case IMX_CCM_SAI2_CLK:
178 case IMX_CCM_SAI3_CLK:
179 CLOCK_DisableClock(sai_clocks[instance]);
180 return 0;
181 #endif
182 #endif /* CONFIG_DAI_NXP_SAI */
183 default:
184 (void)instance;
185 return 0;
186 }
187 }
188
mcux_ccm_get_subsys_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)189 static int mcux_ccm_get_subsys_rate(const struct device *dev,
190 clock_control_subsys_t sub_system,
191 uint32_t *rate)
192 {
193 uint32_t clock_name = (uintptr_t)sub_system;
194
195 switch (clock_name) {
196
197 #ifdef CONFIG_I2C_MCUX_LPI2C
198 case IMX_CCM_LPI2C_CLK:
199 if (CLOCK_GetMux(kCLOCK_Lpi2cMux) == 0) {
200 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
201 / (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
202 } else {
203 *rate = CLOCK_GetOscFreq()
204 / (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
205 }
206
207 break;
208 #endif
209
210 #ifdef CONFIG_SPI_MCUX_LPSPI
211 case IMX_CCM_LPSPI_CLK:
212 {
213 uint32_t lpspi_mux = CLOCK_GetMux(kCLOCK_LpspiMux);
214 clock_name_t lpspi_clock = lpspi_clocks[lpspi_mux];
215
216 *rate = CLOCK_GetFreq(lpspi_clock)
217 / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1);
218 break;
219 }
220 #endif
221
222 #ifdef CONFIG_UART_MCUX_LPUART
223
224 #if defined(CONFIG_SOC_MIMX8QM6_ADSP)
225 case IMX_CCM_LPUART1_CLK:
226 case IMX_CCM_LPUART2_CLK:
227 case IMX_CCM_LPUART3_CLK:
228 case IMX_CCM_LPUART4_CLK:
229 case IMX_CCM_LPUART5_CLK:
230 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
231
232 CLOCK_SetIpFreq(lpuart_clocks[instance], lpuart_rate);
233 *rate = CLOCK_GetIpFreq(lpuart_clocks[instance]);
234 break;
235
236 #elif defined(CONFIG_SOC_MIMX8QX6_ADSP)
237 case IMX_CCM_LPUART1_CLK:
238 case IMX_CCM_LPUART2_CLK:
239 case IMX_CCM_LPUART3_CLK:
240 case IMX_CCM_LPUART4_CLK:
241 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
242
243 CLOCK_SetIpFreq(lpuart_clocks[instance], lpuart_rate);
244 *rate = CLOCK_GetIpFreq(lpuart_clocks[instance]);
245 break;
246
247 #else
248 case IMX_CCM_LPUART_CLK:
249 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) {
250 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
251 / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
252 } else {
253 *rate = CLOCK_GetOscFreq()
254 / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
255 }
256
257 break;
258 #endif
259 #endif
260
261 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc1)) && CONFIG_IMX_USDHC
262 case IMX_CCM_USDHC1_CLK:
263 *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
264 (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U);
265 break;
266 #endif
267
268 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc2)) && CONFIG_IMX_USDHC
269 case IMX_CCM_USDHC2_CLK:
270 *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
271 (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U);
272 break;
273 #endif
274
275 #ifdef CONFIG_DMA_MCUX_EDMA
276 case IMX_CCM_EDMA_CLK:
277 *rate = CLOCK_GetIpgFreq();
278 break;
279 #endif
280
281 #ifdef CONFIG_PWM_MCUX
282 case IMX_CCM_PWM_CLK:
283 *rate = CLOCK_GetIpgFreq();
284 break;
285 #endif
286
287 #ifdef CONFIG_ETH_NXP_ENET
288 case IMX_CCM_ENET_CLK:
289 #ifdef CONFIG_SOC_SERIES_IMX8M
290 *rate = CLOCK_GetFreq(kCLOCK_EnetIpgClk);
291 #else
292 *rate = CLOCK_GetIpgFreq();
293 #endif
294 #endif
295 break;
296
297 #ifdef CONFIG_PTP_CLOCK_NXP_ENET
298 case IMX_CCM_ENET_PLL:
299 *rate = CLOCK_GetPllFreq(kCLOCK_PllEnet);
300 break;
301 #endif
302
303 #ifdef CONFIG_UART_MCUX_IUART
304 case IMX_CCM_UART1_CLK:
305 case IMX_CCM_UART2_CLK:
306 case IMX_CCM_UART3_CLK:
307 case IMX_CCM_UART4_CLK:
308 {
309 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
310 clock_root_control_t clk_root = uart_clk_root[instance];
311 uint32_t uart_mux = CLOCK_GetRootMux(clk_root);
312
313 if (uart_mux == 0) {
314 *rate = MHZ(24);
315 } else if (uart_mux == 1) {
316 *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
317 (CLOCK_GetRootPreDivider(clk_root)) /
318 (CLOCK_GetRootPostDivider(clk_root)) /
319 10;
320 }
321
322 } break;
323 #endif
324
325 #ifdef CONFIG_CAN_MCUX_FLEXCAN
326 case IMX_CCM_CAN_CLK:
327 {
328 uint32_t can_mux = CLOCK_GetMux(kCLOCK_CanMux);
329
330 if (can_mux == 0) {
331 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
332 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
333 } else if (can_mux == 1) {
334 *rate = CLOCK_GetOscFreq()
335 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
336 } else {
337 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
338 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
339 }
340 } break;
341 #endif
342
343 #ifdef CONFIG_COUNTER_MCUX_GPT
344 case IMX_CCM_GPT_CLK:
345 *rate = CLOCK_GetFreq(kCLOCK_PerClk);
346 break;
347 #ifdef CONFIG_SOC_SERIES_IMX8M
348 case IMX_CCM_GPT_IPG_CLK:
349 {
350 uint32_t mux = CLOCK_GetRootMux(kCLOCK_RootGpt1);
351
352 if (mux == 0) {
353 *rate = OSC24M_CLK_FREQ;
354 } else {
355 *rate = 0;
356 }
357 } break;
358 #endif
359 #endif
360
361 #ifdef CONFIG_COUNTER_MCUX_QTMR
362 case IMX_CCM_QTMR_CLK:
363 *rate = CLOCK_GetIpgFreq();
364 break;
365 #endif
366
367 #ifdef CONFIG_I2S_MCUX_SAI
368 case IMX_CCM_SAI1_CLK:
369 *rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
370 / (CLOCK_GetDiv(kCLOCK_Sai1PreDiv) + 1)
371 / (CLOCK_GetDiv(kCLOCK_Sai1Div) + 1);
372 break;
373 case IMX_CCM_SAI2_CLK:
374 *rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
375 / (CLOCK_GetDiv(kCLOCK_Sai2PreDiv) + 1)
376 / (CLOCK_GetDiv(kCLOCK_Sai2Div) + 1);
377 break;
378 case IMX_CCM_SAI3_CLK:
379 *rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
380 / (CLOCK_GetDiv(kCLOCK_Sai3PreDiv) + 1)
381 / (CLOCK_GetDiv(kCLOCK_Sai3Div) + 1);
382 break;
383 #endif
384 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexspi))
385 case IMX_CCM_FLEXSPI_CLK:
386 *rate = CLOCK_GetClockRootFreq(kCLOCK_FlexspiClkRoot);
387 break;
388 #endif
389 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexspi2))
390 case IMX_CCM_FLEXSPI2_CLK:
391 *rate = CLOCK_GetClockRootFreq(kCLOCK_Flexspi2ClkRoot);
392 break;
393 #endif
394 #ifdef CONFIG_COUNTER_NXP_PIT
395 case IMX_CCM_PIT_CLK:
396 *rate = CLOCK_GetFreq(kCLOCK_PerClk);
397 break;
398 #endif
399 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio1)) && CONFIG_MCUX_FLEXIO
400 case IMX_CCM_FLEXIO1_CLK:
401 {
402 uint32_t flexio_mux = CLOCK_GetMux(kCLOCK_Flexio1Mux);
403 uint32_t source_clk_freq = 0;
404
405 if (flexio_mux == 0) {
406 source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
407 } else if (flexio_mux == 1) {
408 source_clk_freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2);
409 #ifdef PLL_VIDEO_OFFSET /* fsl_clock.h */
410 } else if (flexio_mux == 2) {
411 source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllVideo);
412 #endif
413 } else {
414 source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
415 }
416
417 *rate = source_clk_freq / (CLOCK_GetDiv(kCLOCK_Flexio1PreDiv) + 1)
418 / (CLOCK_GetDiv(kCLOCK_Flexio1Div) + 1);
419 } break;
420 #endif
421 #if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio2)) \
422 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio3))) && CONFIG_MCUX_FLEXIO
423 case IMX_CCM_FLEXIO2_3_CLK:
424 {
425 uint32_t flexio_mux = CLOCK_GetMux(kCLOCK_Flexio2Mux);
426 uint32_t source_clk_freq = 0;
427
428 if (flexio_mux == 0) {
429 source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
430 } else if (flexio_mux == 1) {
431 source_clk_freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2);
432 #ifdef PLL_VIDEO_OFFSET /* fsl_clock.h */
433 } else if (flexio_mux == 2) {
434 source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllVideo);
435 #endif
436 } else {
437 source_clk_freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
438 }
439
440 *rate = source_clk_freq / (CLOCK_GetDiv(kCLOCK_Flexio2PreDiv) + 1)
441 / (CLOCK_GetDiv(kCLOCK_Flexio2Div) + 1);
442 } break;
443 #endif
444
445 #ifdef CONFIG_SPI_MCUX_ECSPI
446 case IMX_CCM_ECSPI1_CLK:
447 *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
448 (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) /
449 (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1));
450 break;
451 case IMX_CCM_ECSPI2_CLK:
452 *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
453 (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi2)) /
454 (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi2));
455 break;
456 case IMX_CCM_ECSPI3_CLK:
457 *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
458 (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi3)) /
459 (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi3));
460 break;
461 #endif /* CONFIG_SPI_MCUX_ECSPI */
462
463 #if defined(CONFIG_I2C_NXP_II2C)
464 case IMX_CCM_I2C1_CLK:
465 case IMX_CCM_I2C2_CLK:
466 case IMX_CCM_I2C3_CLK:
467 case IMX_CCM_I2C4_CLK:
468 #ifdef CONFIG_SOC_MIMX8ML8
469 case IMX_CCM_I2C5_CLK:
470 case IMX_CCM_I2C6_CLK:
471 #endif
472 {
473 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
474 uint32_t i2c_mux = CLOCK_GetRootMux(i2c_clk_root[instance]);
475
476 if (i2c_mux == 0) {
477 *rate = MHZ(24);
478 } else if (i2c_mux == 1) {
479 *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
480 (CLOCK_GetRootPreDivider(i2c_clk_root[instance])) /
481 (CLOCK_GetRootPostDivider(i2c_clk_root[instance])) /
482 5; /* SYSTEM PLL1 DIV5 */
483 }
484
485 } break;
486 #endif
487 }
488
489 return 0;
490 }
491
492 /*
493 * Since this function is used to reclock the FlexSPI when running in
494 * XIP, it must be located in RAM when MEMC Flexspi driver is enabled.
495 */
496 #ifdef CONFIG_MEMC_MCUX_FLEXSPI
497 #define CCM_SET_FUNC_ATTR __ramfunc
498 #else
499 #define CCM_SET_FUNC_ATTR
500 #endif
501
mcux_ccm_set_subsys_rate(const struct device * dev,clock_control_subsys_t subsys,clock_control_subsys_rate_t rate)502 static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev,
503 clock_control_subsys_t subsys,
504 clock_control_subsys_rate_t rate)
505 {
506 uint32_t clock_name = (uintptr_t)subsys;
507 uint32_t clock_rate = (uintptr_t)rate;
508
509 switch (clock_name) {
510 case IMX_CCM_FLEXSPI_CLK:
511 __fallthrough;
512 case IMX_CCM_FLEXSPI2_CLK:
513 #if defined(CONFIG_SOC_SERIES_IMXRT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI)
514 /* The SOC is using the FlexSPI for XIP. Therefore,
515 * the FlexSPI itself must be managed within the function,
516 * which is SOC specific.
517 */
518 return flexspi_clock_set_freq(clock_name, clock_rate);
519 #endif
520 default:
521 /* Silence unused variable warning */
522 ARG_UNUSED(clock_rate);
523 return -ENOTSUP;
524 }
525 }
526
527
528
529 static DEVICE_API(clock_control, mcux_ccm_driver_api) = {
530 .on = mcux_ccm_on,
531 .off = mcux_ccm_off,
532 .get_rate = mcux_ccm_get_subsys_rate,
533 .set_rate = mcux_ccm_set_subsys_rate,
534 };
535
mcux_ccm_init(const struct device * dev)536 static int mcux_ccm_init(const struct device *dev)
537 {
538 #if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
539 sc_ipc_t ipc_handle;
540 int ret;
541
542 ret = sc_ipc_open(&ipc_handle, DT_REG_ADDR(DT_NODELABEL(scu_mu)));
543 if (ret != SC_ERR_NONE) {
544 return -ENODEV;
545 }
546
547 CLOCK_Init(ipc_handle);
548 #endif
549 return 0;
550 }
551
552 DEVICE_DT_INST_DEFINE(0, mcux_ccm_init, NULL, NULL, NULL,
553 PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
554 &mcux_ccm_driver_api);
555
