1/* 2 * Copyright (c) 2022 Intel Corporation. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6#include "skeleton.dtsi" 7#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 8#include <zephyr/dt-bindings/i2c/i2c.h> 9#include <zephyr/dt-bindings/pcie/pcie.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,raptor-lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 intc: ioapic@fec00000 { 32 compatible = "intel,ioapic"; 33 #address-cells = <1>; 34 #interrupt-cells = <3>; 35 reg = <0xfec00000 0x1000>; 36 interrupt-controller; 37 }; 38 39 intc_loapic: loapic@fee00000 { 40 compatible = "intel,loapic"; 41 reg = <0xfee00000 0x1000>; 42 interrupt-controller; 43 #interrupt-cells = <3>; 44 #address-cells = <1>; 45 }; 46 47 pcie0: pcie0 { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "pcie-controller"; 51 acpi-hid = "PNP0A08"; 52 ranges; 53 54 smbus0: smbus0 { 55 compatible = "intel,pch-smbus"; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 vendor-id = <0x8086>; 59 device-id = <0x7a23>; 60 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 61 interrupt-parent = <&intc>; 62 63 status = "okay"; 64 }; 65 66 i2c0_dma: i2c0_dma { 67 compatible = "intel,lpss"; 68 #dma-cells = <1>; 69 status = "okay"; 70 }; 71 72 i2c0: i2c0 { 73 compatible = "snps,designware-i2c"; 74 clock-frequency = <I2C_BITRATE_STANDARD>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 vendor-id = <0x8086>; 78 device-id = <0x7acc>; 79 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 80 interrupt-parent = <&intc>; 81 dmas = <&i2c0_dma 0>; 82 83 status = "okay"; 84 }; 85 86 i2c1_dma: i2c1_dma { 87 compatible = "intel,lpss"; 88 #dma-cells = <1>; 89 status = "disabled"; 90 }; 91 92 i2c1: i2c1 { 93 compatible = "snps,designware-i2c"; 94 clock-frequency = <I2C_BITRATE_STANDARD>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 vendor-id = <0x8086>; 98 device-id = <0x7acd>; 99 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 100 interrupt-parent = <&intc>; 101 dmas = <&i2c1_dma 0>; 102 103 status = "disabled"; 104 }; 105 106 i2c2_dma: i2c2_dma { 107 compatible = "intel,lpss"; 108 #dma-cells = <1>; 109 status = "disabled"; 110 }; 111 112 i2c2: i2c2 { 113 compatible = "snps,designware-i2c"; 114 clock-frequency = <I2C_BITRATE_STANDARD>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 vendor-id = <0x8086>; 120 device-id = <0x7ace>; 121 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 122 interrupt-parent = <&intc>; 123 dmas = <&i2c2_dma 0>; 124 125 status = "disabled"; 126 }; 127 128 i2c3_dma: i2c3_dma { 129 compatible = "intel,lpss"; 130 #dma-cells = <1>; 131 status = "disabled"; 132 }; 133 134 i2c3: i2c3 { 135 compatible = "snps,designware-i2c"; 136 clock-frequency = <I2C_BITRATE_STANDARD>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 vendor-id = <0x8086>; 140 device-id = <0x7acf>; 141 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 142 interrupt-parent = <&intc>; 143 dmas = <&i2c3_dma 0>; 144 145 status = "disabled"; 146 }; 147 148 i2c4_dma: i2c4_dma { 149 compatible = "intel,lpss"; 150 #dma-cells = <1>; 151 status = "disabled"; 152 }; 153 154 i2c4: i2c4 { 155 compatible = "snps,designware-i2c"; 156 clock-frequency = <I2C_BITRATE_STANDARD>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 vendor-id = <0x8086>; 160 device-id = <0x7afc>; 161 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 162 interrupt-parent = <&intc>; 163 dmas = <&i2c4_dma 0>; 164 165 status = "disabled"; 166 }; 167 168 i2c5_dma: i2c5_dma { 169 compatible = "intel,lpss"; 170 #dma-cells = <1>; 171 status = "disabled"; 172 }; 173 174 i2c5: i2c5 { 175 compatible = "snps,designware-i2c"; 176 clock-frequency = <I2C_BITRATE_STANDARD>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 vendor-id = <0x8086>; 180 device-id = <0x7afd>; 181 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 182 interrupt-parent = <&intc>; 183 dmas = <&i2c5_dma 0>; 184 185 status = "disabled"; 186 }; 187 188 i2c6_dma: i2c6_dma { 189 compatible = "intel,lpss"; 190 #dma-cells = <1>; 191 status = "disabled"; 192 }; 193 194 i2c6: i2c6 { 195 compatible = "snps,designware-i2c"; 196 clock-frequency = <I2C_BITRATE_STANDARD>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 vendor-id = <0x8086>; 200 device-id = <0x7ada>; 201 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 202 interrupt-parent = <&intc>; 203 dmas = <&i2c6_dma 0>; 204 205 status = "disabled"; 206 }; 207 208 i2c7_dma: i2c7_dma { 209 compatible = "intel,lpss"; 210 #dma-cells = <1>; 211 status = "disabled"; 212 }; 213 214 i2c7: i2c7 { 215 compatible = "snps,designware-i2c"; 216 clock-frequency = <I2C_BITRATE_STANDARD>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 vendor-id = <0x8086>; 220 device-id = <0x7adb>; 221 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 222 interrupt-parent = <&intc>; 223 dmas = <&i2c7_dma 0>; 224 225 status = "disabled"; 226 }; 227 228 spi0: spi0 { 229 compatible = "intel,penwell-spi"; 230 vendor-id = <0x8086>; 231 device-id = <0x7aaa>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 pw,cs-mode = <0>; 235 pw,cs-output = <0>; 236 pw,fifo-depth = <64>; 237 cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>; 238 clock-frequency = <100000000>; 239 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 240 interrupt-parent = <&intc>; 241 status = "okay"; 242 }; 243 244 spi1: spi1 { 245 compatible = "intel,penwell-spi"; 246 vendor-id = <0x8086>; 247 device-id = <0x7aab>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 pw,cs-mode = <0>; 251 pw,cs-output = <0>; 252 pw,fifo-depth = <64>; 253 cs-gpios = <&gpio_0_i 19 GPIO_ACTIVE_LOW>; 254 clock-frequency = <100000000>; 255 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 256 interrupt-parent = <&intc>; 257 status = "disabled"; 258 }; 259 260 spi2: spi2 { 261 compatible = "intel,penwell-spi"; 262 vendor-id = <0x8086>; 263 device-id = <0x7afb>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 pw,cs-mode = <0>; 267 pw,cs-output = <0>; 268 pw,fifo-depth = <64>; 269 cs-gpios = <&gpio_0_r 12 GPIO_ACTIVE_LOW>; 270 clock-frequency = <100000000>; 271 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 272 interrupt-parent = <&intc>; 273 status = "disabled"; 274 }; 275 276 uart0_dma: uart0_dma { 277 compatible = "intel,lpss"; 278 #dma-cells = <1>; 279 status = "disabled"; 280 }; 281 282 uart0: uart0 { 283 compatible = "ns16550"; 284 vendor-id = <0x8086>; 285 device-id = <0x7aa8>; 286 reg-shift = <2>; 287 clock-frequency = <1843200>; 288 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 289 interrupt-parent = <&intc>; 290 current-speed = <115200>; 291 dmas = <&uart0_dma 0>, <&uart0_dma 1>; 292 dma-names = "tx", "rx"; 293 status = "disabled"; 294 }; 295 296 uart1_dma: uart1_dma { 297 compatible = "intel,lpss"; 298 #dma-cells = <1>; 299 status = "disabled"; 300 }; 301 302 uart1: uart1 { 303 compatible = "ns16550"; 304 vendor-id = <0x8086>; 305 device-id = <0x7aa9>; 306 reg-shift = <2>; 307 clock-frequency = <1843200>; 308 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 309 interrupt-parent = <&intc>; 310 current-speed = <115200>; 311 dmas = <&uart1_dma 0>, <&uart1_dma 1>; 312 dma-names = "tx", "rx"; 313 status = "disabled"; 314 }; 315 316 uart2: uart2 { 317 compatible = "ns16550"; 318 vendor-id = <0x8086>; 319 device-id = <0x7afe>; 320 reg-shift = <2>; 321 clock-frequency = <1843200>; 322 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 323 interrupt-parent = <&intc>; 324 current-speed = <115200>; 325 status = "disabled"; 326 }; 327 }; 328 329 soc { 330 #address-cells = <1>; 331 #size-cells = <1>; 332 compatible = "simple-bus"; 333 ranges; 334 335 vtd: vtd@fed91000 { 336 compatible = "intel,vt-d"; 337 reg = <0xfed91000 0x1000>; 338 339 status = "okay"; 340 }; 341 342 uart_ec_0: uart@3f8 { 343 compatible = "ns16550"; 344 reg = <0x000003f8 0x100>; 345 io-mapped; 346 clock-frequency = <1843200>; 347 interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 348 interrupt-parent = <&intc>; 349 reg-shift = <0>; 350 io-mapped; 351 status = "okay"; 352 }; 353 354 gpio_0_i: gpio@e06e0700 { 355 compatible = "intel,gpio"; 356 reg = <0xe06e0700 0x1000>; 357 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 358 interrupt-parent = <&intc>; 359 group-index = <0x0>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 ngpios = <23>; 363 pin-offset = <0>; 364 365 status = "okay"; 366 }; 367 368 gpio_0_r: gpio@e06e0890 { 369 compatible = "intel,gpio"; 370 reg = <0xe06e0890 0x1000>; 371 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 372 interrupt-parent = <&intc>; 373 group-index = <0x1>; 374 gpio-controller; 375 #gpio-cells = <2>; 376 ngpios = <22>; 377 pin-offset = <26>; 378 379 status = "okay"; 380 }; 381 382 gpio_0_j: gpio@e06e0a00 { 383 compatible = "intel,gpio"; 384 reg = <0xe06e0a00 0x1000>; 385 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 386 interrupt-parent = <&intc>; 387 group-index = <0x2>; 388 gpio-controller; 389 #gpio-cells = <2>; 390 ngpios = <12>; 391 pin-offset = <49>; 392 393 status = "okay"; 394 }; 395 396 gpio_1_b: gpio@e06d0700 { 397 compatible = "intel,gpio"; 398 reg = <0xe06d0700 0x1000>; 399 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 400 interrupt-parent = <&intc>; 401 group-index = <0x0>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 ngpios = <24>; 405 pin-offset = <0>; 406 407 status = "okay"; 408 }; 409 410 gpio_1_g: gpio@e06d0880 { 411 compatible = "intel,gpio"; 412 reg = <0xe06d0880 0x1000>; 413 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 414 interrupt-parent = <&intc>; 415 group-index = <0x1>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 ngpios = <8>; 419 pin-offset = <24>; 420 421 status = "okay"; 422 }; 423 424 gpio_1_h: gpio@e06d0900 { 425 compatible = "intel,gpio"; 426 reg = <0xe06d0900 0x1000>; 427 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 428 interrupt-parent = <&intc>; 429 group-index = <0x2>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 ngpios = <24>; 433 pin-offset = <32>; 434 435 status = "okay"; 436 }; 437 438 gpio_3_a: gpio@e06b0790 { 439 compatible = "intel,gpio"; 440 reg = <0xe06b0790 0x1000>; 441 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 442 interrupt-parent = <&intc>; 443 group-index = <0x1>; 444 gpio-controller; 445 #gpio-cells = <2>; 446 ngpios = <15>; 447 pin-offset = <9>; 448 449 status = "okay"; 450 }; 451 452 gpio_3_c: gpio@e06b0890 { 453 compatible = "intel,gpio"; 454 reg = <0xe06b0890 0x1000>; 455 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 456 interrupt-parent = <&intc>; 457 group-index = <0x2>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 ngpios = <24>; 461 pin-offset = <25>; 462 463 status = "okay"; 464 }; 465 466 gpio_4_s: gpio@e06a0700 { 467 compatible = "intel,gpio"; 468 reg = <0xe06a0700 0x1000>; 469 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 470 interrupt-parent = <&intc>; 471 group-index = <0x0>; 472 gpio-controller; 473 #gpio-cells = <2>; 474 ngpios = <8>; 475 pin-offset = <0>; 476 477 status = "okay"; 478 }; 479 480 gpio_4_e: gpio@e06a0780 { 481 compatible = "intel,gpio"; 482 reg = <0xe06a0780 0x1000>; 483 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 484 interrupt-parent = <&intc>; 485 group-index = <0x1>; 486 gpio-controller; 487 #gpio-cells = <2>; 488 ngpios = <22>; 489 pin-offset = <8>; 490 491 status = "okay"; 492 }; 493 494 gpio_4_k: gpio@e06a08f0 { 495 compatible = "intel,gpio"; 496 reg = <0xe06a08f0 0x1000>; 497 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 498 interrupt-parent = <&intc>; 499 group-index = <0x2>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 ngpios = <12>; 503 pin-offset = <25>; 504 505 status = "okay"; 506 }; 507 508 gpio_4_f: gpio@e06a09e0 { 509 compatible = "intel,gpio"; 510 reg = <0xe06a09e0 0x1000>; 511 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 512 interrupt-parent = <&intc>; 513 group-index = <0x3>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 ngpios = <24>; 517 pin-offset = <41>; 518 519 status = "okay"; 520 }; 521 522 gpio_5_d: gpio@e0690700 { 523 compatible = "intel,gpio"; 524 reg = <0xe0690700 0x1000>; 525 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 526 interrupt-parent = <&intc>; 527 group-index = <0x0>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 ngpios = <24>; 531 pin-offset = <0>; 532 533 status = "okay"; 534 }; 535 536 pwm0: pwm@e06a0000 { 537 compatible = "intel,blinky-pwm"; 538 reg = <0xe06a0000 0x400>; 539 reg-offset = <0x304>; 540 clock-frequency = <32768>; 541 max-pins = <1>; 542 #pwm-cells = <2>; 543 status = "okay"; 544 }; 545 546 rtc: counter: rtc@70 { 547 compatible = "motorola,mc146818"; 548 reg = <0x70 0x0D 0x71 0x0D>; 549 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 550 interrupt-parent = <&intc>; 551 alarms-count = <1>; 552 553 status = "okay"; 554 }; 555 556 tgpio: tgpio@fe001200 { 557 compatible = "intel,timeaware-gpio"; 558 reg = <0xfe001200 0x100>; 559 timer-clock = <19200000>; 560 max-pins = <2>; 561 status = "okay"; 562 }; 563 564 hpet: hpet@fed00000 { 565 compatible = "intel,hpet"; 566 reg = <0xfed00000 0x400>; 567 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 568 interrupt-parent = <&intc>; 569 570 status = "okay"; 571 }; 572 573 tco_wdt: tco_wdt@400 { 574 compatible = "intel,tco-wdt"; 575 reg = <0x0400 0x20>; 576 577 status = "disabled"; 578 }; 579 }; 580}; 581
