1 /*
2 * Copyright 2023 The ChromiumOS Authors
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
10 #include <zephyr/fff.h>
11 #include <zephyr/ztest.h>
12
13 #define MY_GPIO DT_NODELABEL(gpioa)
14
15 const struct device *const gpio_dev = DEVICE_DT_GET(MY_GPIO);
16 static struct {
17 uint8_t fake;
18 uint8_t gpdmr;
19 uint8_t gpdr;
20 uint8_t gpotr;
21 uint8_t p18scr;
22 uint8_t wuemr, wuesr, wubemr;
23 uint8_t gpcr[DT_REG_SIZE_BY_IDX(MY_GPIO, 4)];
24 bool clear_gpcr_before_read;
25 } registers;
26 static int callback_called;
27 static struct gpio_callback callback_struct;
28
29 /* These values must match what is set in the dts overlay. */
30 #define TEST_PIN 1
31 #define TEST_IRQ DT_IRQ_BY_IDX(MY_GPIO, TEST_PIN, irq)
32 #define TEST_MASK DT_PROP_BY_IDX(MY_GPIO, wuc_mask, TEST_PIN)
33
34 DEFINE_FFF_GLOBALS;
35
ite_intc_get_irq_num(void)36 uint8_t ite_intc_get_irq_num(void)
37 {
38 return posix_get_current_irq();
39 }
40
fake_ecreg(intptr_t r)41 unsigned int *fake_ecreg(intptr_t r)
42 {
43 switch (r) {
44 case DT_REG_ADDR_BY_IDX(MY_GPIO, 0): /* GPDR */
45 return (unsigned int *)®isters.gpdr;
46 case DT_REG_ADDR_BY_IDX(MY_GPIO, 1): /* GPDMR */
47 return (unsigned int *)®isters.gpdmr;
48 case DT_REG_ADDR_BY_IDX(MY_GPIO, 2): /* GPOTR */
49 return (unsigned int *)®isters.gpotr;
50 case DT_REG_ADDR_BY_IDX(MY_GPIO, 3): /* P18SCR */
51 return (unsigned int *)®isters.p18scr;
52 case DT_PROP_BY_IDX(MY_GPIO, wuc_base, TEST_PIN):
53 return (unsigned int *)®isters.wuemr;
54 case DT_PROP_BY_IDX(MY_GPIO, wuc_base, TEST_PIN) + 1:
55 return (unsigned int *)®isters.wuesr;
56 case DT_PROP_BY_IDX(MY_GPIO, wuc_base, TEST_PIN) + 3:
57 return (unsigned int *)®isters.wubemr;
58 }
59 if (r >= DT_REG_ADDR_BY_IDX(MY_GPIO, 4) &&
60 r < DT_REG_ADDR_BY_IDX(MY_GPIO, 4) + DT_REG_SIZE_BY_IDX(MY_GPIO, 4)) {
61 if (registers.clear_gpcr_before_read) {
62 registers.gpcr[r - DT_REG_ADDR_BY_IDX(MY_GPIO, 4)] = 0;
63 }
64 return (unsigned int *)®isters.gpcr[r - DT_REG_ADDR_BY_IDX(MY_GPIO, 4)];
65 }
66 zassert_unreachable("Register access: %x", r);
67 return (unsigned int *)®isters.fake;
68 }
69
callback(const struct device * port,struct gpio_callback * cb,gpio_port_pins_t pins)70 static void callback(const struct device *port, struct gpio_callback *cb, gpio_port_pins_t pins)
71 {
72 callback_called++;
73 zexpect_equal(pins, BIT(TEST_PIN));
74
75 /* If the callback has been called 5 or more times, toggle the pin in the input register. */
76 if (callback_called >= 5) {
77 registers.gpdmr ^= pins;
78 }
79 }
80
before_test(void * fixture)81 static void before_test(void *fixture)
82 {
83 callback_called = 0;
84 memset(®isters, 0, sizeof(registers));
85 }
86
after_test(void * fixture)87 static void after_test(void *fixture)
88 {
89 if (callback_struct.handler != NULL) {
90 zassert_ok(gpio_remove_callback(gpio_dev, &callback_struct));
91 }
92 callback_struct.handler = NULL;
93 }
94
95 ZTEST_SUITE(gpio_ite_it8xxx2_v2, NULL, NULL, before_test, after_test, NULL);
96
ZTEST(gpio_ite_it8xxx2_v2,test_get_active_high)97 ZTEST(gpio_ite_it8xxx2_v2, test_get_active_high)
98 {
99 zassert_true(device_is_ready(gpio_dev));
100 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_HIGH));
101 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
102 zexpect_equal(registers.p18scr, 0);
103 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
104 registers.gpcr[TEST_PIN]);
105 registers.gpdmr = (uint8_t)~BIT(TEST_PIN);
106 zassert_false(gpio_pin_get(gpio_dev, TEST_PIN));
107 registers.gpdmr = BIT(TEST_PIN);
108 zassert_true(gpio_pin_get(gpio_dev, TEST_PIN));
109 }
110
ZTEST(gpio_ite_it8xxx2_v2,test_get_active_low)111 ZTEST(gpio_ite_it8xxx2_v2, test_get_active_low)
112 {
113 zassert_true(device_is_ready(gpio_dev));
114 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_LOW));
115 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
116 zexpect_equal(registers.p18scr, 0);
117 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
118 registers.gpcr[TEST_PIN]);
119 registers.gpdmr = (uint8_t)~BIT(TEST_PIN);
120 zassert_true(gpio_pin_get(gpio_dev, TEST_PIN));
121 registers.gpdmr = BIT(TEST_PIN);
122 zassert_false(gpio_pin_get(gpio_dev, TEST_PIN));
123 }
124
ZTEST(gpio_ite_it8xxx2_v2,test_interrupt_edge_rising)125 ZTEST(gpio_ite_it8xxx2_v2, test_interrupt_edge_rising)
126 {
127 zassert_true(device_is_ready(gpio_dev));
128 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_HIGH));
129
130 gpio_init_callback(&callback_struct, &callback, BIT(TEST_PIN));
131 zassert_ok(gpio_add_callback(gpio_dev, &callback_struct));
132 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_EDGE_TO_ACTIVE));
133 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
134 zexpect_equal(registers.p18scr, 0);
135 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
136 registers.gpcr[TEST_PIN]);
137 zexpect_equal(registers.wubemr, 0, "wubemr=%x", registers.wubemr);
138 zexpect_equal(registers.wuemr, 0, "wuemr=%x", registers.wuemr);
139 zexpect_equal(registers.wuesr, TEST_MASK, "wuesr=%x", registers.wuesr);
140 registers.wuesr = 0;
141
142 registers.gpdmr = BIT(TEST_PIN);
143 /* Mock the hardware interrupt. */
144 posix_sw_set_pending_IRQ(TEST_IRQ);
145 k_sleep(K_MSEC(100));
146 zassert_equal(callback_called, 1, "callback_called=%d", callback_called);
147 }
148
ZTEST(gpio_ite_it8xxx2_v2,test_interrupt_enable_disable)149 ZTEST(gpio_ite_it8xxx2_v2, test_interrupt_enable_disable)
150 {
151 zassert_true(device_is_ready(gpio_dev));
152 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_HIGH));
153
154 gpio_init_callback(&callback_struct, &callback, BIT(TEST_PIN));
155 zassert_ok(gpio_add_callback(gpio_dev, &callback_struct));
156 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_EDGE_TO_ACTIVE));
157 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
158 zexpect_equal(registers.p18scr, 0);
159 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
160 registers.gpcr[TEST_PIN]);
161 zexpect_equal(registers.wubemr, 0, "wubemr=%x", registers.wubemr);
162 zexpect_equal(registers.wuemr, 0, "wuemr=%x", registers.wuemr);
163 zexpect_equal(registers.wuesr, TEST_MASK, "wuesr=%x", registers.wuesr);
164 registers.wuesr = 0;
165
166 registers.gpdmr = BIT(TEST_PIN);
167 /* Mock the hardware interrupt. */
168 posix_sw_set_pending_IRQ(TEST_IRQ);
169 k_sleep(K_MSEC(100));
170 zassert_equal(callback_called, 1, "callback_called=%d", callback_called);
171 registers.gpdmr = 0;
172
173 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_MODE_DISABLED));
174 registers.gpdmr = BIT(TEST_PIN);
175 /* Mock the hardware interrupt, should be ignored */
176 posix_sw_set_pending_IRQ(TEST_IRQ);
177 k_sleep(K_MSEC(100));
178 zassert_equal(callback_called, 1, "callback_called=%d", callback_called);
179 /* Clear the missed interrupt */
180 posix_sw_clear_pending_IRQ(TEST_IRQ);
181 registers.gpdmr = 0;
182
183 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_EDGE_TO_ACTIVE));
184 registers.gpdmr = BIT(TEST_PIN);
185 /* Mock the hardware interrupt */
186 posix_sw_set_pending_IRQ(TEST_IRQ);
187 k_sleep(K_MSEC(100));
188 zassert_equal(callback_called, 2, "callback_called=%d", callback_called);
189 }
190
ZTEST(gpio_ite_it8xxx2_v2,test_interrupt_edge_falling)191 ZTEST(gpio_ite_it8xxx2_v2, test_interrupt_edge_falling)
192 {
193 zassert_true(device_is_ready(gpio_dev));
194 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_HIGH));
195
196 gpio_init_callback(&callback_struct, &callback, BIT(TEST_PIN));
197 zassert_ok(gpio_add_callback(gpio_dev, &callback_struct));
198 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_EDGE_TO_INACTIVE));
199 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
200 zexpect_equal(registers.p18scr, 0);
201 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
202 registers.gpcr[TEST_PIN]);
203 zexpect_equal(registers.wubemr, 0, "wubemr=%x", registers.wubemr);
204 zexpect_equal(registers.wuemr, TEST_MASK, "wuemr=%x", registers.wuemr);
205 zexpect_equal(registers.wuesr, TEST_MASK, "wuesr=%x", registers.wuesr);
206 registers.wuesr = 0;
207
208 registers.gpdmr = (uint8_t)~BIT(TEST_PIN);
209 /* Mock the hardware interrupt. */
210 posix_sw_set_pending_IRQ(TEST_IRQ);
211 k_sleep(K_MSEC(100));
212 zassert_equal(callback_called, 1, "callback_called=%d", callback_called);
213 }
214
ZTEST(gpio_ite_it8xxx2_v2,test_interrupt_edge_both)215 ZTEST(gpio_ite_it8xxx2_v2, test_interrupt_edge_both)
216 {
217 zassert_true(device_is_ready(gpio_dev));
218 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_HIGH));
219
220 gpio_init_callback(&callback_struct, &callback, BIT(TEST_PIN));
221 zassert_ok(gpio_add_callback(gpio_dev, &callback_struct));
222 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_EDGE_BOTH));
223 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
224 zexpect_equal(registers.p18scr, 0);
225 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
226 registers.gpcr[TEST_PIN]);
227 zexpect_equal(registers.wubemr, TEST_MASK, "wubemr=%x", registers.wubemr);
228 zexpect_equal(registers.wuemr, TEST_MASK, "wuemr=%x", registers.wuemr);
229 zexpect_equal(registers.wuesr, TEST_MASK, "wuesr=%x", registers.wuesr);
230 registers.wuesr = 0;
231
232 registers.gpdmr = BIT(TEST_PIN);
233 /* Mock the hardware interrupt. */
234 posix_sw_set_pending_IRQ(TEST_IRQ);
235 k_sleep(K_MSEC(100));
236 zassert_equal(callback_called, 1, "callback_called=%d", callback_called);
237 registers.gpdmr &= ~BIT(TEST_PIN);
238 /* Mock the hardware interrupt. */
239 posix_sw_set_pending_IRQ(TEST_IRQ);
240 k_sleep(K_MSEC(100));
241 zassert_equal(callback_called, 2, "callback_called=%d", callback_called);
242 }
243
244 /* Tests both the active level case and the interrupt not firing at configure case. */
ZTEST(gpio_ite_it8xxx2_v2,test_interrupt_level_active)245 ZTEST(gpio_ite_it8xxx2_v2, test_interrupt_level_active)
246 {
247 zassert_true(device_is_ready(gpio_dev));
248 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_HIGH));
249
250 gpio_init_callback(&callback_struct, &callback, BIT(TEST_PIN));
251 zassert_ok(gpio_add_callback(gpio_dev, &callback_struct));
252 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_LEVEL_ACTIVE));
253 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
254 zexpect_equal(registers.p18scr, 0);
255 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
256 registers.gpcr[TEST_PIN]);
257 zexpect_equal(registers.wubemr, 0, "wubemr=%x", registers.wubemr);
258 zexpect_equal(registers.wuemr, 0, "wuemr=%x", registers.wuemr);
259 zexpect_equal(registers.wuesr, TEST_MASK, "wuesr=%x", registers.wuesr);
260 registers.wuesr = 0;
261 k_sleep(K_MSEC(100));
262 zexpect_equal(callback_called, 0, "callback_called=%d", callback_called);
263
264 registers.gpdmr = BIT(TEST_PIN);
265 /* Mock the hardware interrupt. */
266 posix_sw_set_pending_IRQ(TEST_IRQ);
267 k_sleep(K_MSEC(100));
268 zexpect_equal(callback_called, 5, "callback_called=%d", callback_called);
269 }
270
271 /* Tests both the inactive level case and the interrupt already firing at configure case. */
ZTEST(gpio_ite_it8xxx2_v2,test_interrupt_level_inactive)272 ZTEST(gpio_ite_it8xxx2_v2, test_interrupt_level_inactive)
273 {
274 zassert_true(device_is_ready(gpio_dev));
275 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_ACTIVE_HIGH));
276
277 gpio_init_callback(&callback_struct, &callback, BIT(TEST_PIN));
278 zassert_ok(gpio_add_callback(gpio_dev, &callback_struct));
279 zassert_ok(gpio_pin_interrupt_configure(gpio_dev, TEST_PIN, GPIO_INT_LEVEL_INACTIVE));
280 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
281 zexpect_equal(registers.p18scr, 0);
282 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
283 registers.gpcr[TEST_PIN]);
284 zexpect_equal(registers.wubemr, 0, "wubemr=%x", registers.wubemr);
285 zexpect_equal(registers.wuemr, TEST_MASK, "wuemr=%x", registers.wuemr);
286 zexpect_equal(registers.wuesr, TEST_MASK, "wuesr=%x", registers.wuesr);
287 registers.wuesr = 0;
288 k_sleep(K_MSEC(100));
289 /* The interrupt was already active when we started. */
290 zexpect_equal(callback_called, 5, "callback_called=%d", callback_called);
291
292 registers.gpdmr = 0;
293 callback_called = 0;
294 /* Mock the hardware interrupt. */
295 posix_sw_set_pending_IRQ(TEST_IRQ);
296 k_sleep(K_MSEC(100));
297 zexpect_equal(callback_called, 5, "callback_called=%d", callback_called);
298 }
299
ZTEST(gpio_ite_it8xxx2_v2,test_set_active_high)300 ZTEST(gpio_ite_it8xxx2_v2, test_set_active_high)
301 {
302 gpio_flags_t flags;
303
304 zassert_true(device_is_ready(gpio_dev));
305 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_OUTPUT_INACTIVE | GPIO_ACTIVE_HIGH));
306 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
307 zexpect_equal(registers.p18scr, 0);
308 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_OUTPUT, "gpcr[%d]=%x", TEST_PIN,
309 registers.gpcr[TEST_PIN]);
310
311 zexpect_equal(registers.gpdr, 0, "gpdr=%x", registers.gpdr);
312 zassert_ok(gpio_pin_set(gpio_dev, TEST_PIN, true));
313 zexpect_equal(registers.gpdr, BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
314 zassert_ok(gpio_pin_set(gpio_dev, TEST_PIN, false));
315 zexpect_equal(registers.gpdr, 0, "gpdr=%x", registers.gpdr);
316 zassert_ok(gpio_port_toggle_bits(gpio_dev, BIT(TEST_PIN)));
317 zexpect_equal(registers.gpdr, BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
318 registers.gpdr = 0;
319 zassert_ok(gpio_port_set_masked(gpio_dev, BIT(TEST_PIN), 255));
320 zexpect_equal(registers.gpdr, BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
321 registers.gpdr = 255;
322 zassert_ok(gpio_port_set_masked(gpio_dev, BIT(TEST_PIN), 0));
323 zexpect_equal(registers.gpdr, (uint8_t)~BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
324
325 registers.gpdr = BIT(TEST_PIN);
326 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
327 zexpect_equal(flags, GPIO_OUTPUT_HIGH, "flags=%x", flags);
328 registers.gpdr = 0;
329 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
330 zexpect_equal(flags, GPIO_OUTPUT_LOW, "flags=%x", flags);
331 }
332
ZTEST(gpio_ite_it8xxx2_v2,test_set_active_low)333 ZTEST(gpio_ite_it8xxx2_v2, test_set_active_low)
334 {
335 gpio_flags_t flags;
336
337 zassert_true(device_is_ready(gpio_dev));
338 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_OUTPUT_INACTIVE | GPIO_ACTIVE_LOW));
339 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
340 zexpect_equal(registers.p18scr, 0);
341 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_OUTPUT, "gpcr[%d]=%x", TEST_PIN,
342 registers.gpcr[TEST_PIN]);
343
344 zexpect_equal(registers.gpdr, BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
345 zassert_ok(gpio_pin_set(gpio_dev, TEST_PIN, true));
346 zexpect_equal(registers.gpdr, 0, "gpdr=%x", registers.gpdr);
347 zassert_ok(gpio_pin_set(gpio_dev, TEST_PIN, false));
348 zexpect_equal(registers.gpdr, BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
349 zassert_ok(gpio_port_toggle_bits(gpio_dev, BIT(TEST_PIN)));
350 zexpect_equal(registers.gpdr, 0, "gpdr=%x", registers.gpdr);
351 registers.gpdr = 255;
352 zassert_ok(gpio_port_set_masked(gpio_dev, BIT(TEST_PIN), 255));
353 zexpect_equal(registers.gpdr, (uint8_t)~BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
354 registers.gpdr = 0;
355 zassert_ok(gpio_port_set_masked(gpio_dev, BIT(TEST_PIN), 0));
356 zexpect_equal(registers.gpdr, BIT(TEST_PIN), "gpdr=%x", registers.gpdr);
357
358 registers.gpdr = 0;
359 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
360 zexpect_equal(flags, GPIO_OUTPUT_LOW, "flags=%x", flags);
361 registers.gpdr = BIT(TEST_PIN);
362 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
363 zexpect_equal(flags, GPIO_OUTPUT_HIGH, "flags=%x", flags);
364 }
365
366 /* The next few tests just verify that the registers are set as expected on configure. */
367
ZTEST(gpio_ite_it8xxx2_v2,test_open_source)368 ZTEST(gpio_ite_it8xxx2_v2, test_open_source)
369 {
370 zassert_true(device_is_ready(gpio_dev));
371 zassert_equal(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_OPEN_SOURCE), -ENOTSUP);
372 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
373 zexpect_equal(registers.p18scr, 0);
374 zexpect_equal(registers.gpcr[TEST_PIN], 0, "gpcr[%d]=%x", TEST_PIN,
375 registers.gpcr[TEST_PIN]);
376 }
377
ZTEST(gpio_ite_it8xxx2_v2,test_open_drain_output)378 ZTEST(gpio_ite_it8xxx2_v2, test_open_drain_output)
379 {
380 gpio_flags_t flags;
381
382 zassert_true(device_is_ready(gpio_dev));
383 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_OUTPUT | GPIO_OPEN_DRAIN));
384 zexpect_equal(registers.gpotr, BIT(TEST_PIN), "gpotr=%x", registers.gpotr);
385 zexpect_equal(registers.p18scr, 0);
386 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_OUTPUT, "gpcr[%d]=%x", TEST_PIN,
387 registers.gpcr[TEST_PIN]);
388
389 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
390 zexpect_equal(flags, GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN, "flags=%x", flags);
391 }
392
ZTEST(gpio_ite_it8xxx2_v2,test_pull_up_input)393 ZTEST(gpio_ite_it8xxx2_v2, test_pull_up_input)
394 {
395 gpio_flags_t flags;
396
397 zassert_true(device_is_ready(gpio_dev));
398 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_PULL_UP));
399 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
400 zexpect_equal(registers.p18scr, 0);
401 zexpect_equal(registers.gpcr[TEST_PIN],
402 GPCR_PORT_PIN_MODE_INPUT | GPCR_PORT_PIN_MODE_PULLUP, "gpcr[%d]=%x", TEST_PIN,
403 registers.gpcr[TEST_PIN]);
404
405 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
406 zexpect_equal(flags, GPIO_INPUT | GPIO_PULL_UP, "flags=%x", flags);
407 }
408
ZTEST(gpio_ite_it8xxx2_v2,test_pull_down_input)409 ZTEST(gpio_ite_it8xxx2_v2, test_pull_down_input)
410 {
411 gpio_flags_t flags;
412
413 zassert_true(device_is_ready(gpio_dev));
414 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | GPIO_PULL_DOWN));
415 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
416 zexpect_equal(registers.p18scr, 0);
417 zexpect_equal(registers.gpcr[TEST_PIN],
418 GPCR_PORT_PIN_MODE_INPUT | GPCR_PORT_PIN_MODE_PULLDOWN, "gpcr[%d]=%x",
419 TEST_PIN, registers.gpcr[TEST_PIN]);
420
421 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
422 zexpect_equal(flags, GPIO_INPUT | GPIO_PULL_DOWN, "flags=%x", flags);
423 }
424
ZTEST(gpio_ite_it8xxx2_v2,test_disconnected_tristate_supported)425 ZTEST(gpio_ite_it8xxx2_v2, test_disconnected_tristate_supported)
426 {
427 gpio_flags_t flags;
428
429 zassert_true(device_is_ready(gpio_dev));
430 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_DISCONNECTED));
431 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
432 zexpect_equal(registers.p18scr, 0);
433 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_TRISTATE, "gpcr[%d]=%x",
434 TEST_PIN, registers.gpcr[TEST_PIN]);
435
436 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
437 zexpect_equal(flags, GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_INPUT | IT8XXX2_GPIO_VOLTAGE_3P3,
438 "flags=%x", flags);
439 }
440
ZTEST(gpio_ite_it8xxx2_v2,test_disconnected_tristate_unsupported)441 ZTEST(gpio_ite_it8xxx2_v2, test_disconnected_tristate_unsupported)
442 {
443 registers.clear_gpcr_before_read = true;
444 zassert_true(device_is_ready(gpio_dev));
445 zassert_equal(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_DISCONNECTED), -ENOTSUP);
446 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
447 zexpect_equal(registers.p18scr, 0);
448 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
449 registers.gpcr[TEST_PIN]);
450 }
451
ZTEST(gpio_ite_it8xxx2_v2,test_input_1P8V)452 ZTEST(gpio_ite_it8xxx2_v2, test_input_1P8V)
453 {
454 gpio_flags_t flags;
455
456 zassert_true(device_is_ready(gpio_dev));
457 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | IT8XXX2_GPIO_VOLTAGE_1P8));
458 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
459 zexpect_equal(registers.p18scr, BIT(TEST_PIN));
460 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
461 registers.gpcr[TEST_PIN]);
462
463 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
464 zexpect_equal(flags, GPIO_INPUT | IT8XXX2_GPIO_VOLTAGE_1P8, "flags=%x", flags);
465 }
466
ZTEST(gpio_ite_it8xxx2_v2,test_input_3P3V)467 ZTEST(gpio_ite_it8xxx2_v2, test_input_3P3V)
468 {
469 gpio_flags_t flags;
470
471 zassert_true(device_is_ready(gpio_dev));
472 zassert_ok(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | IT8XXX2_GPIO_VOLTAGE_3P3));
473 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
474 zexpect_equal(registers.p18scr, 0);
475 zexpect_equal(registers.gpcr[TEST_PIN], GPCR_PORT_PIN_MODE_INPUT, "gpcr[%d]=%x", TEST_PIN,
476 registers.gpcr[TEST_PIN]);
477
478 zassert_ok(gpio_pin_get_config(gpio_dev, TEST_PIN, &flags));
479 zexpect_equal(flags, GPIO_INPUT | IT8XXX2_GPIO_VOLTAGE_3P3, "flags=%x", flags);
480 }
481
ZTEST(gpio_ite_it8xxx2_v2,test_input_5V)482 ZTEST(gpio_ite_it8xxx2_v2, test_input_5V)
483 {
484 zassert_true(device_is_ready(gpio_dev));
485 zassert_equal(gpio_pin_configure(gpio_dev, TEST_PIN, GPIO_INPUT | IT8XXX2_GPIO_VOLTAGE_5P0),
486 -EINVAL);
487 zexpect_equal(registers.gpotr, 0, "gpotr=%x", registers.gpotr);
488 zexpect_equal(registers.p18scr, 0);
489 zexpect_equal(registers.gpcr[TEST_PIN], 0, "gpcr[%d]=%x", TEST_PIN,
490 registers.gpcr[TEST_PIN]);
491 }
492
