1 /*
2 * Copyright (c) 2025 Analog Devices, Inc.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #include <stdbool.h>
7 #include <zephyr/device.h>
8 #include <zephyr/devicetree.h>
9 #include <zephyr/drivers/adc.h>
10 #include <zephyr/drivers/spi.h>
11 #include <zephyr/logging/log.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/sys/util.h>
14 #include <zephyr/sys/byteorder.h>
15
16 LOG_MODULE_REGISTER(adc_ad405x, CONFIG_ADC_LOG_LEVEL);
17
18 #define ADC_CONTEXT_USES_KERNEL_TIMER
19 #include "adc_context.h"
20
21 #define AD4050_CHIP_ID 4050
22 #define AD4052_CHIP_ID 4052
23
24 #define AD4050_ADC_RESOLUTION 12U
25 #define AD4052_ADC_RESOLUTION 16U
26
27 #define AD405X_REG_INTERFACE_CONFIG_A 0x00U
28 #define AD405X_REG_DEVICE_CONFIG 0x02U
29 #define AD405X_REG_DEVICE_TYPE 0x03U
30 #define AD405X_REG_PRODUCT_ID_L 0x04U
31 #define AD405X_REG_PRODUCT_ID_H 0x05U
32 #define AD405X_REG_VENDOR_L 0x0CU
33 #define AD405X_REG_VENDOR_H 0x0DU
34 #define AD405X_REG_MODE_SET 0x20U
35 #define AD405X_REG_ADC_MODES 0x21U
36 #define AD405X_REG_AVG_CONFIG 0x23U
37 #define AD405X_REG_GP_PIN_CONF 0x24U
38 #define AD405X_REG_TIMER_CONFIG 0x27U
39
40 #define AD405X_REG_INTERFACE_CONFIG_A_VAL 0x10U
41 #define AD405X_REG_DEVICE_TYPE_VAL 0x07U
42 #define AD4052_REG_PRODUCT_ID_VAL 0x0072U
43 #define AD4050_REG_PRODUCT_ID_VAL 0x0070U
44 #define AD405X_REG_VENDOR_VAL 0x0456U
45 #define AD405X_REG_INTERFACE_CONFIG_A_RESET_VAL 0x81U
46
47 /** AD405X_REG_ADC_MODES Bit definition */
48 #define AD405X_ADC_MODES_MSK GENMASK(2, 0)
49 #define AD405X_BURST_AVERAGING_MODE BIT(0)
50 #define AD405X_AVERAGING_MODE BIT(1)
51
52 /** AD405X_REG_MODE_SET Bit definition */
53 #define AD405X_ENTER_ADC_MODE_MSK BIT(0)
54 #define AD405X_ENTER_ADC_MODE BIT(0)
55 #define AD405X_ENTER_SLEEP_MODE BIT(1) | BIT(0)
56 #define AD405X_ENTER_ACTIVE_MODE 0x0U
57
58 /** AD405X_REG_AVG_CONFIG Bit Definitions */
59 #define AD405X_AVG_WIN_LEN_MSK GENMASK(3, 0)
60
61 #define AD405X_WRITE_CMD 0x0U
62 #define AD405X_READ_CMD 0x80U
63
64 #define AD405X_SW_RESET_MSK BIT(7) | BIT(0)
65
66 #define AD405X_GP1_MODE_MSK GENMASK(6, 4)
67 #define AD405X_GP0_MODE_MSK GENMASK(2, 0)
68 #define AD405X_GP1 0x1U
69 #define AD405X_GP0 0x0U
70
71 /** AD405X_REG_TIMER_CONFIG Bit Definitions */
72 #define AD405X_FS_BURST_AUTO_MSK GENMASK(7, 4)
73
74 union ad405x_bus {
75 struct spi_dt_spec spi;
76 };
77
78 enum ad405x_gpx_mode {
79 AD405X_DISABLED = 0,
80 AD405X_GP0_1_INTR = 1,
81 AD405X_DATA_READY = 2,
82 AD405X_DEV_ENABLE = 3,
83 AD405X_CHOP = 4,
84 AD405X_LOGIC_LOW = 5,
85 AD405X_LOGIC_HIGH = 6,
86 AD405X_DEV_READY = 7
87 };
88
89 /** AD405X modes of operations */
90 enum ad405x_operation_mode {
91 AD405X_SAMPLE_MODE_OP = 0,
92 AD405X_BURST_AVERAGING_MODE_OP = 1,
93 AD405X_AVERAGING_MODE_OP = 2,
94 AD405X_MONITOR_AUTO_MODE_OP = 3,
95 AD405X_CONFIG_MODE_OP = 4,
96 AD405X_SLEEP_MODE_OP = 5,
97 AD405X_TRIGGER_AUTO_MODE_OP = 7
98 };
99
100 /** AD405X sample rate for burst and autonomous modes */
101 enum ad405x_sample_rate {
102 AD405X_2_MSPS,
103 AD405X_1_MSPS,
104 AD405X_333_KSPS,
105 AD405X_100_KSPS,
106 AD405X_33_KSPS,
107 AD405X_10_KSPS,
108 AD405X_3_KSPS,
109 AD405X_1_KSPS,
110 AD405X_500_SPS,
111 AD405X_333_SPS,
112 AD405X_250_SPS,
113 AD405X_200_SPS,
114 AD405X_166_SPS,
115 AD405X_140_SPS,
116 AD405X_125_SPS,
117 AD405X_111_SPS
118 };
119
120 /** AD405X averaging filter window length */
121 enum ad405x_avg_filter_l {
122 AD405X_LENGTH_2,
123 AD405X_LENGTH_4,
124 AD405X_LENGTH_8,
125 AD405X_LENGTH_16,
126 AD405X_LENGTH_32,
127 AD405X_LENGTH_64,
128 AD405X_LENGTH_128,
129 AD405X_LENGTH_256,
130 AD405X_LENGTH_512,
131 AD405X_LENGTH_1024,
132 AD405X_LENGTH_2048,
133 AD405X_LENGTH_4096
134 };
135 static const int avg_filter_values[] = {2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096};
136
137 struct adc_ad405x_config {
138 const union ad405x_bus bus;
139 enum ad405x_operation_mode active_mode;
140 #ifdef CONFIG_AD405X_TRIGGER
141 struct gpio_dt_spec gp1_interrupt;
142 struct gpio_dt_spec gp0_interrupt;
143 uint8_t has_gp1;
144 uint8_t has_gp0;
145 #endif
146 struct gpio_dt_spec conversion;
147 uint16_t chip_id;
148 uint16_t resolution;
149 };
150
151 struct adc_ad405x_data {
152 struct adc_context ctx;
153 const struct device *dev;
154 uint8_t adc_conf;
155 uint8_t diff;
156 uint8_t channels;
157 uint16_t *buffer;
158 uint16_t *repeat_buffer;
159 enum ad405x_operation_mode operation_mode;
160 struct k_sem sem_devrdy;
161 const struct device *gpio_dev;
162 enum ad405x_gpx_mode gp1_mode;
163 enum ad405x_gpx_mode gp0_mode;
164 uint8_t dev_en_pol;
165 enum ad405x_sample_rate rate;
166 enum ad405x_avg_filter_l filter_length;
167 #if CONFIG_AD405X_TRIGGER
168 struct gpio_callback gpio1_cb;
169 struct gpio_callback gpio0_cb;
170 struct k_sem sem_drdy;
171 uint8_t has_drdy;
172 #endif
173 };
174
ad405x_bus_is_ready_spi(const union ad405x_bus * bus)175 static bool ad405x_bus_is_ready_spi(const union ad405x_bus *bus)
176 {
177 bool ret = spi_is_ready_dt(&bus->spi);
178
179 return ret;
180 }
181
ad405x_reg_access_spi(const struct device * dev,uint8_t cmd,uint8_t reg_addr,uint8_t * data,size_t length)182 int ad405x_reg_access_spi(const struct device *dev, uint8_t cmd, uint8_t reg_addr, uint8_t *data,
183 size_t length)
184 {
185 const struct adc_ad405x_config *cfg = dev->config;
186 uint8_t access = reg_addr | cmd;
187 const struct spi_buf buf[2] = {{.buf = &access, .len = 1}, {.buf = data, .len = length}};
188 const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)};
189 struct spi_buf_set tx = {
190 .buffers = buf,
191 .count = 2,
192 };
193 int ret;
194
195 if (cmd == AD405X_READ_CMD) {
196 tx.count = 1;
197 ret = spi_transceive_dt(&cfg->bus.spi, &tx, &rx);
198 } else {
199 ret = spi_write_dt(&cfg->bus.spi, &tx);
200 }
201 return ret;
202 }
203
ad405x_reset_pattern_cmd(const struct device * dev)204 int ad405x_reset_pattern_cmd(const struct device *dev)
205 {
206 const struct adc_ad405x_config *cfg = dev->config;
207 #if CONFIG_AD405X_TRIGGER
208 struct adc_ad405x_data *data = dev->data;
209 #endif
210 uint8_t access[18] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
211 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE};
212 const struct spi_buf buf[1] = {{.buf = &access, .len = ARRAY_SIZE(access)}};
213 struct spi_buf_set tx = {
214 .buffers = buf,
215 .count = 1,
216 };
217
218 int ret = spi_write_dt(&cfg->bus.spi, &tx);
219
220 if (ret < 0) {
221 return ret;
222 }
223 #if CONFIG_AD405X_TRIGGER
224 if (cfg->has_gp1 != 0) {
225 k_sem_take(&data->sem_devrdy, K_FOREVER);
226 } else {
227 k_msleep(5);
228 }
229 #else
230 k_msleep(5);
231 #endif
232 return ret;
233
234 }
235
ad405x_read_raw(const struct device * dev,uint8_t * data,size_t len)236 int ad405x_read_raw(const struct device *dev, uint8_t *data, size_t len)
237 {
238 const struct adc_ad405x_config *cfg = dev->config;
239 int ret = 0;
240 const struct spi_buf buf[1] = {{.buf = data, .len = len}};
241 const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)};
242
243 ret = spi_transceive_dt(&cfg->bus.spi, NULL, &rx);
244
245 return ret;
246 }
247
ad405x_reg_access(const struct device * dev,uint8_t cmd,uint8_t addr,uint8_t * data,size_t len)248 int ad405x_reg_access(const struct device *dev, uint8_t cmd, uint8_t addr, uint8_t *data,
249 size_t len)
250 {
251 return ad405x_reg_access_spi(dev, cmd, addr, data, len);
252 }
253
ad405x_reg_write(const struct device * dev,uint8_t addr,uint8_t * data,uint8_t len)254 int ad405x_reg_write(const struct device *dev, uint8_t addr, uint8_t *data, uint8_t len)
255 {
256
257 return ad405x_reg_access(dev, AD405X_WRITE_CMD, addr, data, len);
258 }
259
ad405x_reg_read(const struct device * dev,uint8_t addr,uint8_t * data,uint8_t len)260 int ad405x_reg_read(const struct device *dev, uint8_t addr, uint8_t *data, uint8_t len)
261 {
262
263 return ad405x_reg_access(dev, AD405X_READ_CMD, addr, data, len);
264 }
265
ad405x_reg_write_byte(const struct device * dev,uint8_t addr,uint8_t val)266 int ad405x_reg_write_byte(const struct device *dev, uint8_t addr, uint8_t val)
267 {
268 return ad405x_reg_write(dev, addr, &val, 1);
269 }
270
ad405x_reg_read_byte(const struct device * dev,uint8_t addr,uint8_t * buf)271 int ad405x_reg_read_byte(const struct device *dev, uint8_t addr, uint8_t *buf)
272
273 {
274 return ad405x_reg_read(dev, addr, buf, 1);
275 }
276
ad405x_reg_update_bits(const struct device * dev,uint8_t addr,uint8_t mask,uint8_t val)277 int ad405x_reg_update_bits(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
278 {
279 int ret;
280 uint8_t byte = 0;
281
282 ret = ad405x_reg_read_byte(dev, addr, &byte);
283 if (ret < 0) {
284 return ret;
285 }
286
287 byte &= ~mask;
288 byte |= val;
289
290 return ad405x_reg_write_byte(dev, addr, byte);
291 }
292
293 #if CONFIG_AD405X_TRIGGER
ad405x_gpio1_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)294 static void ad405x_gpio1_callback(const struct device *dev, struct gpio_callback *cb,
295 uint32_t pins)
296 {
297 struct adc_ad405x_data *drv_data = CONTAINER_OF(cb, struct adc_ad405x_data, gpio1_cb);
298 const struct adc_ad405x_config *cfg = drv_data->dev->config;
299 gpio_flags_t gpio_flag = GPIO_INT_EDGE_TO_ACTIVE;
300
301 gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt, GPIO_INT_DISABLE);
302
303 switch (drv_data->gp1_mode) {
304 case AD405X_DEV_READY:
305 k_sem_give(&drv_data->sem_devrdy);
306 break;
307 case AD405X_DATA_READY:
308 k_sem_give(&drv_data->sem_drdy);
309 gpio_flag = GPIO_INT_EDGE_TO_INACTIVE;
310 break;
311 default: /* TODO */
312 break;
313 }
314
315 gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt, gpio_flag);
316 }
317
ad405x_gpio0_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)318 static void ad405x_gpio0_callback(const struct device *dev, struct gpio_callback *cb,
319 uint32_t pins)
320 {
321 struct adc_ad405x_data *drv_data = CONTAINER_OF(cb, struct adc_ad405x_data, gpio0_cb);
322 const struct adc_ad405x_config *cfg = drv_data->dev->config;
323 gpio_flags_t gpio_flag = GPIO_INT_EDGE_TO_ACTIVE;
324
325 gpio_pin_interrupt_configure_dt(&cfg->gp0_interrupt, GPIO_INT_DISABLE);
326
327 switch (drv_data->gp0_mode) {
328 case AD405X_DATA_READY:
329 k_sem_give(&drv_data->sem_drdy);
330 gpio_flag = GPIO_INT_EDGE_TO_INACTIVE;
331 break;
332 default:
333 break;
334 }
335
336 gpio_pin_interrupt_configure_dt(&cfg->gp0_interrupt, gpio_flag);
337
338 }
339 #endif
340
ad405x_init_conv(const struct device * dev)341 int ad405x_init_conv(const struct device *dev)
342 {
343 const struct adc_ad405x_config *cfg = dev->config;
344 struct adc_ad405x_data *drv_data = dev->data;
345 int ret;
346
347 if (!gpio_is_ready_dt(&cfg->conversion)) {
348 LOG_ERR("GPIO port %s not ready", cfg->conversion.port->name);
349 return -EINVAL;
350 }
351
352 ret = gpio_pin_configure_dt(&cfg->conversion, GPIO_OUTPUT_INACTIVE);
353 if (ret != 0) {
354 return ret;
355 }
356
357 ret = gpio_pin_set_dt(&cfg->conversion, 0);
358 drv_data->dev = dev;
359 return ret;
360 }
361
362 #if CONFIG_AD405X_TRIGGER
ad405x_init_interrupt(const struct device * dev)363 int ad405x_init_interrupt(const struct device *dev)
364 {
365 const struct adc_ad405x_config *cfg = dev->config;
366 struct adc_ad405x_data *drv_data = dev->data;
367 int ret;
368
369 if (cfg->has_gp1 != 0) {
370
371 if (!gpio_is_ready_dt(&cfg->gp1_interrupt)) {
372 LOG_ERR("GPIO port %s not ready", cfg->gp1_interrupt.port->name);
373 return -EINVAL;
374 }
375
376 ret = gpio_pin_configure_dt(&cfg->gp1_interrupt, GPIO_INPUT);
377 if (ret != 0) {
378 return ret;
379 }
380
381 gpio_init_callback(&drv_data->gpio1_cb, ad405x_gpio1_callback,
382 BIT(cfg->gp1_interrupt.pin));
383
384 ret = gpio_add_callback(cfg->gp1_interrupt.port, &drv_data->gpio1_cb);
385 if (ret != 0) {
386 LOG_ERR("Failed to set gpio callback!");
387 return ret;
388 }
389
390 gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt, GPIO_INT_EDGE_TO_ACTIVE);
391 }
392
393 if (cfg->has_gp0 != 0) {
394
395 if (!gpio_is_ready_dt(&cfg->gp0_interrupt)) {
396 LOG_ERR("GPIO port %s not ready", cfg->gp0_interrupt.port->name);
397 return -EINVAL;
398 }
399
400 ret = gpio_pin_configure_dt(&cfg->gp0_interrupt, GPIO_INPUT);
401 if (ret != 0) {
402 return ret;
403 }
404
405 gpio_init_callback(&drv_data->gpio0_cb, ad405x_gpio0_callback,
406 BIT(cfg->gp0_interrupt.pin));
407
408 ret = gpio_add_callback(cfg->gp0_interrupt.port, &drv_data->gpio0_cb);
409 if (ret != 0) {
410 LOG_ERR("Failed to set gpio callback!");
411 return ret;
412 }
413 }
414
415 return 0;
416 }
417 #endif
418
ad405x_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)419 static int ad405x_channel_setup(const struct device *dev,
420 const struct adc_channel_cfg *channel_cfg)
421 {
422 if (channel_cfg->channel_id != 0) {
423 LOG_ERR("invalid channel id %d", channel_cfg->channel_id);
424 return -EINVAL;
425 }
426
427 return 0;
428 }
429
adc_ad405x_validate_buffer_size(const struct device * dev,const struct adc_sequence * sequence)430 static int adc_ad405x_validate_buffer_size(const struct device *dev,
431 const struct adc_sequence *sequence)
432 {
433 uint8_t channels;
434 size_t needed;
435
436 channels = POPCOUNT(sequence->channels);
437 needed = channels * sizeof(uint16_t);
438
439 if (sequence->buffer_size < needed) {
440 return -ENOMEM;
441 }
442
443 return 0;
444 }
445
ad405x_conv_start(const struct device * dev)446 int ad405x_conv_start(const struct device *dev)
447 {
448 const struct adc_ad405x_config *cfg = dev->config;
449 int ret;
450
451 ret = gpio_pin_set_dt(&cfg->conversion, 1);
452 if (ret != 0) {
453 return ret;
454 }
455
456 /** CNV High Time min 10 ns */
457 k_busy_wait(1);
458 ret = gpio_pin_set_dt(&cfg->conversion, 0);
459 if (ret != 0) {
460 return ret;
461 }
462
463 return 0;
464 }
465
adc_context_start_sampling(struct adc_context * ctx)466 static void adc_context_start_sampling(struct adc_context *ctx)
467 {
468
469 struct adc_ad405x_data *data = CONTAINER_OF(ctx, struct adc_ad405x_data, ctx);
470 const struct adc_ad405x_config *cfg = (struct adc_ad405x_config *)data->dev->config;
471
472 uint8_t reg_val_x[3] = {0};
473 uint32_t data_be;
474 size_t len = 0;
475
476 switch (data->operation_mode) {
477 case AD405X_SAMPLE_MODE_OP:
478 len = 2;
479 ad405x_conv_start(data->dev);
480 break;
481 case AD405X_BURST_AVERAGING_MODE_OP:
482 if (cfg->chip_id == AD4052_CHIP_ID) {
483 len = 3;
484 }
485 ad405x_conv_start(data->dev);
486 break;
487 case AD405X_AVERAGING_MODE_OP:
488 if (cfg->chip_id == AD4052_CHIP_ID) {
489 len = 3;
490 }
491 uint16_t conv_avg = avg_filter_values[data->filter_length];
492
493 for (int i = 0; i < conv_avg; i++) {
494 ad405x_conv_start(data->dev);
495 }
496 break;
497 default:
498 len = 2;
499 break;
500 }
501
502 #if CONFIG_AD405X_TRIGGER
503 if (data->has_drdy != 0) {
504 k_sem_take(&data->sem_drdy, K_FOREVER);
505 }
506 #endif
507 ad405x_read_raw(data->dev, reg_val_x, len);
508 switch (len) {
509 case 2:
510 /* translate valid bytes to BE format */
511 data_be = sys_get_be16(reg_val_x);
512 break;
513 case 3:
514 data_be = sys_get_be24(reg_val_x);
515 break;
516 default:
517 data_be = sys_get_be16(reg_val_x);
518 break;
519 }
520 memcpy(ctx->sequence.buffer, &data_be, len);
521
522 adc_context_on_sampling_done(&data->ctx, data->dev);
523 }
524
ad405x_set_sample_rate(const struct device * dev,enum ad405x_sample_rate rate)525 int ad405x_set_sample_rate(const struct device *dev, enum ad405x_sample_rate rate)
526 {
527 struct adc_ad405x_data *data = dev->data;
528 int ret;
529
530 ret = ad405x_reg_update_bits(dev, AD405X_REG_TIMER_CONFIG, AD405X_FS_BURST_AUTO_MSK, rate);
531 if (ret != 0) {
532 return ret;
533 }
534
535 data->rate = rate;
536
537 return 0;
538 }
539
ad405x_set_averaging_filter_length(const struct device * dev,enum ad405x_avg_filter_l length)540 int ad405x_set_averaging_filter_length(const struct device *dev, enum ad405x_avg_filter_l length)
541 {
542 const struct adc_ad405x_config *cfg = dev->config;
543 struct adc_ad405x_data *data = dev->data;
544 int ret;
545
546 /* Restrict filter length depending on active device selected */
547 if (cfg->chip_id == AD4050_CHIP_ID) {
548 if (length > AD405X_LENGTH_256) {
549 return -EINVAL;
550 }
551 }
552 ret = ad405x_reg_update_bits(dev, AD405X_REG_AVG_CONFIG, AD405X_AVG_WIN_LEN_MSK, length);
553 if (ret) {
554 return ret;
555 }
556
557 data->filter_length = length;
558
559 return 0;
560 }
561
ad405x_exit_command(const struct device * dev)562 int ad405x_exit_command(const struct device *dev)
563 {
564 int ret;
565
566 const struct adc_ad405x_config *cfg = dev->config;
567 struct adc_ad405x_data *data = dev->data;
568 uint8_t access[1] = {0xA8};
569 const struct spi_buf buf[1] = {{.buf = &access, .len = ARRAY_SIZE(access)}};
570 struct spi_buf_set tx = {
571 .buffers = buf,
572 .count = 1,
573 };
574
575 ret = spi_write_dt(&cfg->bus.spi, &tx);
576 if (!ret) {
577 data->operation_mode = AD405X_CONFIG_MODE_OP;
578 }
579
580 return ret;
581 }
582
ad405x_set_operation_mode(const struct device * dev,enum ad405x_operation_mode operation_mode)583 int ad405x_set_operation_mode(const struct device *dev, enum ad405x_operation_mode operation_mode)
584 {
585 struct adc_ad405x_data *data = dev->data;
586 int ret;
587
588 if (data->operation_mode == AD405X_SLEEP_MODE_OP) {
589 if (operation_mode != AD405X_SLEEP_MODE_OP) {
590 ret = ad405x_reg_write_byte(dev, AD405X_REG_DEVICE_CONFIG,
591 AD405X_ENTER_ACTIVE_MODE);
592 if (ret != 0) {
593 return ret;
594 }
595 if (operation_mode != AD405X_CONFIG_MODE_OP) {
596 /* Set Operation mode. */
597 ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES,
598 AD405X_ADC_MODES_MSK, operation_mode);
599 if (ret != 0) {
600 return ret;
601 }
602 /* Enter ADC_MODE. */
603 ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET,
604 AD405X_ENTER_ADC_MODE_MSK,
605 AD405X_ENTER_ADC_MODE);
606 if (ret != 0) {
607 return ret;
608 }
609 }
610 }
611 } else if (data->operation_mode == AD405X_CONFIG_MODE_OP) {
612 if (operation_mode == AD405X_SLEEP_MODE_OP) {
613 ret = ad405x_reg_write_byte(dev, AD405X_REG_DEVICE_CONFIG,
614 AD405X_ENTER_SLEEP_MODE);
615 if (ret != 0) {
616 return ret;
617 }
618 } else {
619 /* Set Operation mode. */
620 ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES,
621 AD405X_ADC_MODES_MSK, operation_mode);
622 if (ret != 0) {
623 return ret;
624 }
625 /* Enter ADC_MODE. */
626 ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET,
627 AD405X_ENTER_ADC_MODE_MSK,
628 AD405X_ENTER_ADC_MODE);
629 if (ret != 0) {
630 return ret;
631 }
632 }
633 } else {
634 ret = ad405x_exit_command(dev);
635 if (ret != 0) {
636 return ret;
637 };
638 if (operation_mode == AD405X_SLEEP_MODE_OP) {
639 ret = ad405x_reg_write_byte(dev, AD405X_REG_DEVICE_CONFIG,
640 AD405X_ENTER_SLEEP_MODE);
641 if (ret != 0) {
642 return ret;
643 }
644 } else if (operation_mode != AD405X_CONFIG_MODE_OP) {
645 ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES,
646 AD405X_ADC_MODES_MSK, operation_mode);
647 if (ret != 0) {
648 return ret;
649 }
650 /* Enter ADC_MODE. */
651 ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET,
652 AD405X_ENTER_ADC_MODE_MSK,
653 AD405X_ENTER_ADC_MODE);
654 if (ret != 0) {
655 return ret;
656 }
657 }
658 }
659 data->operation_mode = operation_mode;
660 return 0;
661 }
662
663 #if CONFIG_AD405X_TRIGGER
ad405x_set_gpx_mode(const struct device * dev,uint8_t gp0_1,enum ad405x_gpx_mode gpx_mode)664 int ad405x_set_gpx_mode(const struct device *dev, uint8_t gp0_1, enum ad405x_gpx_mode gpx_mode)
665 {
666 const struct adc_ad405x_config *cfg = dev->config;
667 struct adc_ad405x_data *data = dev->data;
668 uint8_t mask = AD405X_GP1_MODE_MSK;
669 int ret;
670 enum ad405x_gpx_mode gpx_mode_tmp = gpx_mode;
671
672 if (gp0_1 == AD405X_GP0) {
673 mask = AD405X_GP0_MODE_MSK;
674 if (gpx_mode == AD405X_DEV_READY) {
675 return -EINVAL;
676 }
677 } else {
678 gpx_mode_tmp = gpx_mode_tmp << 4;
679 }
680
681 ret = ad405x_reg_update_bits(dev, AD405X_REG_GP_PIN_CONF, mask, gpx_mode_tmp);
682
683 if (ret == 0) {
684 if (gp0_1 == AD405X_GP0) {
685 if (gpx_mode == AD405X_DATA_READY) {
686 gpio_pin_interrupt_configure_dt(&cfg->gp0_interrupt,
687 GPIO_INT_EDGE_TO_INACTIVE);
688 }
689 data->gp0_mode = gpx_mode;
690 } else {
691 if (gpx_mode == AD405X_DATA_READY) {
692 gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt,
693 GPIO_INT_EDGE_TO_INACTIVE);
694 }
695 data->gp1_mode = gpx_mode;
696 }
697 }
698 return ret;
699 }
700 #endif
701
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)702 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
703 {
704 struct adc_ad405x_data *data = CONTAINER_OF(ctx, struct adc_ad405x_data, ctx);
705
706 if (repeat_sampling) {
707 data->buffer = data->repeat_buffer;
708 }
709 }
710
adc_ad405x_start_read(const struct device * dev,const struct adc_sequence * sequence)711 static int adc_ad405x_start_read(const struct device *dev, const struct adc_sequence *sequence)
712 {
713 const struct adc_ad405x_config *cfg = dev->config;
714 struct adc_ad405x_data *data = dev->data;
715 int ret;
716
717 if (cfg->chip_id == AD4050_CHIP_ID) {
718 if (sequence->resolution != AD4050_ADC_RESOLUTION) {
719 LOG_ERR("invalid resolution %d", sequence->resolution);
720 return -EINVAL;
721 }
722 }
723 if (cfg->chip_id == AD4052_CHIP_ID) {
724 if (sequence->resolution != AD4052_ADC_RESOLUTION) {
725 LOG_ERR("invalid resolution %d", sequence->resolution);
726 return -EINVAL;
727 }
728 }
729
730 ret = adc_ad405x_validate_buffer_size(dev, sequence);
731 if (ret < 0) {
732 LOG_ERR("insufficient buffer size");
733 return ret;
734 }
735
736 ad405x_set_operation_mode(dev, cfg->active_mode);
737
738 data->buffer = sequence->buffer;
739 adc_context_start_read(&data->ctx, sequence);
740
741 return adc_context_wait_for_completion(&data->ctx);
742 }
743
adc_ad405x_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)744 static int adc_ad405x_read_async(const struct device *dev, const struct adc_sequence *sequence,
745 struct k_poll_signal *async)
746 {
747 struct adc_ad405x_data *data = dev->data;
748 int ret;
749
750 adc_context_lock(&data->ctx, async ? true : false, async);
751 ret = adc_ad405x_start_read(dev, sequence);
752 adc_context_release(&data->ctx, ret);
753
754 return ret;
755 }
756
ad405x_read(const struct device * dev,const struct adc_sequence * sequence)757 static int ad405x_read(const struct device *dev, const struct adc_sequence *sequence)
758 {
759 return adc_ad405x_read_async(dev, sequence, NULL);
760 }
761
adc_ad405x_bus_is_ready(const struct device * dev)762 static inline bool adc_ad405x_bus_is_ready(const struct device *dev)
763 {
764 const struct adc_ad405x_config *cfg = dev->config;
765
766 return ad405x_bus_is_ready_spi(&cfg->bus);
767 }
768
ad405x_soft_reset(const struct device * dev)769 int ad405x_soft_reset(const struct device *dev)
770 {
771 int ret;
772
773 ret = ad405x_reg_update_bits(dev, AD405X_REG_INTERFACE_CONFIG_A, AD405X_SW_RESET_MSK,
774 AD405X_REG_INTERFACE_CONFIG_A_RESET_VAL);
775 if (ret < 0) {
776 return ret;
777 }
778
779 return ad405x_reg_update_bits(dev, AD405X_REG_INTERFACE_CONFIG_A, AD405X_SW_RESET_MSK, 0);
780 }
781
adc_ad405x_init(const struct device * dev)782 static int adc_ad405x_init(const struct device *dev)
783 {
784 const struct adc_ad405x_config *cfg = dev->config;
785 struct adc_ad405x_data *data = dev->data;
786 int ret;
787 uint8_t reg_val;
788 uint8_t reg_val_hi;
789 uint16_t reg_val_res;
790
791 if (!adc_ad405x_bus_is_ready(dev)) {
792 LOG_ERR("bus not ready");
793 return -ENODEV;
794 }
795
796 #if CONFIG_AD405X_TRIGGER
797 ret = ad405x_init_interrupt(dev);
798 if (ret != 0) {
799 LOG_ERR("Failed to initialize interrupt!");
800 return -EIO;
801 }
802 #else
803 data->gp0_mode = AD405X_DISABLED;
804 #endif
805 ad405x_init_conv(dev);
806 data->gp1_mode = AD405X_DEV_READY;
807 data->operation_mode = AD405X_CONFIG_MODE_OP;
808 data->filter_length = AD405X_LENGTH_2;
809 k_sem_init(&data->sem_devrdy, 0, 1);
810 adc_context_init(&data->ctx);
811
812 /* Reset */
813 ret = ad405x_reset_pattern_cmd(dev);
814 if (ret < 0) {
815 return ret;
816 }
817
818 ret = ad405x_reg_read_byte(dev, AD405X_REG_PRODUCT_ID_L, ®_val);
819 if (ret < 0) {
820 return ret;
821 }
822
823 ret = ad405x_reg_read_byte(dev, AD405X_REG_PRODUCT_ID_H, ®_val_hi);
824 if (ret < 0) {
825 return ret;
826 }
827
828 reg_val_res = (reg_val_hi << 8) | reg_val;
829 if ((reg_val_res != AD4052_REG_PRODUCT_ID_VAL) &
830 (reg_val_res != AD4050_REG_PRODUCT_ID_VAL)) {
831 LOG_ERR("Invalid product id");
832 return -ENODEV;
833 }
834
835 ret = ad405x_reg_read_byte(dev, AD405X_REG_DEVICE_TYPE, ®_val);
836 if (ret < 0) {
837 return ret;
838 }
839
840 if (reg_val != AD405X_REG_DEVICE_TYPE_VAL) {
841 LOG_ERR("Invalid device type");
842 return -ENODEV;
843 }
844
845 ret = ad405x_reg_read_byte(dev, AD405X_REG_VENDOR_L, ®_val);
846 if (ret < 0) {
847 return ret;
848 }
849
850 ret = ad405x_reg_read_byte(dev, AD405X_REG_VENDOR_H, ®_val_hi);
851 if (ret < 0) {
852 return ret;
853 }
854
855 reg_val_res = (reg_val_hi << 8) | reg_val;
856 if (reg_val_res != AD405X_REG_VENDOR_VAL) {
857 LOG_ERR("Invalid vendor value");
858 return -ENODEV;
859 }
860
861 #if CONFIG_AD405X_TRIGGER
862 if (cfg->has_gp1 != 0) {
863 ad405x_set_gpx_mode(dev, AD405X_GP1, AD405X_DATA_READY);
864 k_sem_init(&data->sem_drdy, 0, 1);
865 data->has_drdy = 1;
866 }
867 #endif
868
869 adc_context_unlock_unconditionally(&data->ctx);
870 data->dev = dev;
871 return ret;
872 }
873
874 static DEVICE_API(adc, ad405x_api_funcs) = {
875 .channel_setup = ad405x_channel_setup,
876 .read = ad405x_read,
877 .ref_internal = 2048,
878 #ifdef CONFIG_ADC_ASYNC
879 .read_async = ad405x_adc_read_async,
880 #endif
881 };
882
883 #define DT_INST_AD405X(inst, t) DT_INST(inst, adi_ad##t##_adc)
884
885 #define AD405X_GPIO_PROPS1(n) \
886 .gp1_interrupt = GPIO_DT_SPEC_INST_GET_OR(n, gp1_gpios, {0}), \
887 .has_gp1 = 1, \
888
889 #define AD405X_GPIO_PROPS0(n) \
890 .gp0_interrupt = GPIO_DT_SPEC_INST_GET_OR(n, gp0_gpios, {0}), \
891 .has_gp0 = 1, \
892
893 #define AD405X_GPIO(t, n) \
894 IF_ENABLED(DT_NODE_HAS_PROP(DT_INST_AD405X(n, t), gp1_gpios), \
895 (AD405X_GPIO_PROPS1(n))) \
896 IF_ENABLED(DT_NODE_HAS_PROP(DT_INST_AD405X(n, t), gp0_gpios), \
897 (AD405X_GPIO_PROPS0(n)))
898
899 #define AD405X_INIT(t, n, res) \
900 static struct adc_ad405x_data ad##t##_data_##n = {}; \
901 static const struct adc_ad405x_config ad##t##_config_##n = { \
902 .bus = {.spi = SPI_DT_SPEC_GET(DT_INST_AD405X(n, t), SPI_WORD_SET(8) | \
903 SPI_TRANSFER_MSB, 0)}, \
904 .conversion = GPIO_DT_SPEC_GET_BY_IDX(DT_INST_AD405X(n, t), conversion_gpios, 0),\
905 IF_ENABLED(CONFIG_AD405X_TRIGGER, (AD405X_GPIO(t, n))) \
906 .chip_id = t, \
907 .active_mode = AD405X_SAMPLE_MODE_OP, \
908 .resolution = res, \
909 }; \
910 DEVICE_DT_DEFINE(DT_INST_AD405X(n, t), adc_ad405x_init, NULL, &ad##t##_data_##n, \
911 &ad##t##_config_##n, POST_KERNEL, \
912 CONFIG_ADC_INIT_PRIORITY, &ad405x_api_funcs);
913
914 /*
915 * AD4052: 16 bit
916 */
917 #define AD4052_INIT(n) AD405X_INIT(AD4052_CHIP_ID, n, AD4052_ADC_RESOLUTION)
918 #undef DT_DRV_COMPAT
919 #define DT_DRV_COMPAT adi_ad4052_adc
920 DT_INST_FOREACH_STATUS_OKAY(AD4052_INIT)
921
922 /*
923 * AD4050: 12 bit
924 */
925 #define AD4050_INIT(n) AD405X_INIT(AD4050_CHIP_ID, n, AD4050_ADC_RESOLUTION)
926 #undef DT_DRV_COMPAT
927 #define DT_DRV_COMPAT adi_ad4050_adc
928 DT_INST_FOREACH_STATUS_OKAY(AD4050_INIT)
929
