1/* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7ecs: ecs@4000fc00 { 8 reg = <0x4000fc00 0x200>; 9}; 10pcr: pcr@40080100 { 11 compatible = "microchip,xec-pcr"; 12 reg = <0x40080100 0x100 0x4000a400 0x100>; 13 reg-names = "pcrr", "vbatr"; 14 interrupts = <174 0>; 15 core-clock-div = <1>; 16 /* MEC172x allows sources to be different */ 17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>; 18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>; 19 clk32kmon-period-min = <1435>; 20 clk32kmon-period-max = <1495>; 21 clk32kmon-duty-cycle-var-max = <132>; 22 clk32kmon-valid-min = <4>; 23 xtal-enable-delay-ms = <300>; 24 pll-lock-timeout-ms = <30>; 25 #clock-cells = <3>; 26}; 27ecia: ecia@4000e000 { 28 compatible = "microchip,xec-ecia"; 29 reg = <0x4000e000 0x400>; 30 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>; 31 clocks = <&pcr 1 0 MCHP_XEC_PCR_CLK_PERIPH>; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 ranges = <0x0 0x4000e000 0x400>; 36 37 girq8: girq8@0 { 38 compatible = "microchip,xec-ecia-girq"; 39 reg = <0x0 0x14>; 40 interrupts = <0 0>; 41 girq-id = <0>; 42 sources = <0 1 2 3 4 5 6 7 43 8 9 10 11 12 13 14 15 44 16 17 18 21 22 24 25 45 26 27 28 29>; 46 status = "disabled"; 47 }; 48 girq9: girq9@14 { 49 compatible = "microchip,xec-ecia-girq"; 50 reg = <0x14 0x14>; 51 interrupts = <1 0>; 52 girq-id = <1>; 53 sources = <0 1 2 3 4 5 6 7 54 8 9 10 11 12 13 14 15 55 16 17 18 19 20 21 22 23 56 24 25 26 27 28 29>; 57 status = "disabled"; 58 }; 59 girq10: girq10@28 { 60 compatible = "microchip,xec-ecia-girq"; 61 reg = <0x28 0x14>; 62 interrupts = <2 0>; 63 girq-id = <2>; 64 sources = <0 1 2 3 4 5 6 7 65 8 9 10 11 12 13 14 15 66 16 17 18 19 20 21 22 23 67 24 25 26 27 28 29 30>; 68 status = "disabled"; 69 }; 70 girq11: girq11@3c { 71 compatible = "microchip,xec-ecia-girq"; 72 reg = <0x3c 0x14>; 73 interrupts = <3 0>; 74 girq-id = <3>; 75 sources = <0 1 2 3 4 5 6 7 76 8 9 10 11 12 13 14 15 77 16 17 18 19 20 21 22 23 78 24 25 26 27 28 29 30>; 79 status = "disabled"; 80 }; 81 girq12: girq12@50 { 82 compatible = "microchip,xec-ecia-girq"; 83 reg = <0x50 0x14>; 84 interrupts = <4 0>; 85 girq-id = <4>; 86 sources = <0 1 2 3 4 5 6 7 87 8 9 10 11 12 13 14 15 88 16 17 18 19 20 21 22 23 89 24 25 26 27 28 29 30>; 90 status = "disabled"; 91 }; 92 girq13: girq13@64 { 93 compatible = "microchip,xec-ecia-girq"; 94 reg = <0x64 0x14>; 95 interrupts = <5 0>; 96 girq-id = <5>; 97 sources = <0 1 2 3 4>; 98 status = "disabled"; 99 }; 100 girq14: girq14@78 { 101 compatible = "microchip,xec-ecia-girq"; 102 reg = <0x78 0x14>; 103 interrupts = <6 0>; 104 girq-id = <6>; 105 sources = <0 1 2 3 4 5 6 7 106 8 9 10 11 12 13 14 15>; 107 status = "disabled"; 108 }; 109 girq15: girq15@8c { 110 compatible = "microchip,xec-ecia-girq"; 111 reg = <0x8c 0x14>; 112 interrupts = <7 0>; 113 girq-id = <7>; 114 sources = <0 1 2 3 4 5 6 7 115 8 9 10 11 12 13 14 15 116 16 17 18 19 20 22>; 117 status = "disabled"; 118 }; 119 girq16: girq16@a0 { 120 compatible = "microchip,xec-ecia-girq"; 121 reg = <0xa0 0x14>; 122 interrupts = <8 0>; 123 girq-id = <8>; 124 sources = <0 2 3>; 125 status = "disabled"; 126 }; 127 girq17: girq17@b4 { 128 compatible = "microchip,xec-ecia-girq"; 129 reg = <0xb4 0x14>; 130 interrupts = <9 0>; 131 girq-id = <9>; 132 sources = <0 1 2 3 4 8 9 10 11 12 13 14 15 133 16 17 20 21 22 23>; 134 status = "disabled"; 135 }; 136 girq18: girq18@c8 { 137 compatible = "microchip,xec-ecia-girq"; 138 reg = <0xc8 0x14>; 139 interrupts = <10 0>; 140 girq-id = <10>; 141 sources = <0 1 2 3 4 5 6 7 142 10 20 21 22 23 143 24 25 26 27 28>; 144 status = "disabled"; 145 }; 146 girq19: girq19@dc { 147 compatible = "microchip,xec-ecia-girq"; 148 reg = <0xdc 0x14>; 149 interrupts = <11 0>; 150 girq-id = <11>; 151 sources = <0 1 2 3 4 5 6 7 8 9 10>; 152 status = "disabled"; 153 }; 154 girq20: girq20@f0 { 155 compatible = "microchip,xec-ecia-girq"; 156 reg = <0xf0 0x14>; 157 interrupts = <12 0>; 158 girq-id = <12>; 159 sources = <3 9>; 160 status = "disabled"; 161 }; 162 girq21: girq21@104 { 163 compatible = "microchip,xec-ecia-girq"; 164 reg = <0x104 0x14>; 165 interrupts = <13 0>; 166 girq-id = <13>; 167 sources = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 168 18 19 25 26>; 169 status = "disabled"; 170 }; 171 girq22: girq22@118 { 172 compatible = "microchip,xec-ecia-girq"; 173 reg = <0x118 0x14>; 174 interrupts = <255 0>; 175 girq-id = <14>; 176 sources = <0 1 2 3 4 5 9 15>; 177 status = "disabled"; 178 }; 179 girq23: girq23@12c { 180 compatible = "microchip,xec-ecia-girq"; 181 reg = <0x12c 0x14>; 182 interrupts = <14 0>; 183 girq-id = <15>; 184 sources = <0 1 2 3 4 5 6 7 8 9 10 16 17>; 185 status = "disabled"; 186 }; 187 girq24: girq24@140 { 188 compatible = "microchip,xec-ecia-girq"; 189 reg = <0x140 0x14>; 190 interrupts = <15 0>; 191 girq-id = <16>; 192 sources = <0 1 2 3 4 5 6 7 8 9 10 11 193 12 13 14 15 16 17 18 19 194 20 21 22 23 24 25 26 27>; 195 status = "disabled"; 196 }; 197 girq25: girq25@154 { 198 compatible = "microchip,xec-ecia-girq"; 199 reg = <0x154 0x14>; 200 interrupts = <16 0>; 201 girq-id = <17>; 202 sources = <0 1 2 3 4 5 6 7 8 9 10 11 203 12 13 14 15>; 204 status = "disabled"; 205 }; 206 girq26: girq26@168 { 207 compatible = "microchip,xec-ecia-girq"; 208 reg = <0x168 0x14>; 209 interrupts = <17 0>; 210 girq-id = <18>; 211 sources = <0 1 2 3 4 5 6 12 13>; 212 status = "disabled"; 213 }; 214}; 215pinctrl: pin-controller@40081000 { 216 compatible = "microchip,xec-pinctrl"; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 reg = <0x40081000 0x1000>; 220 221 gpio_000_036: gpio@40081000 { 222 compatible = "microchip,xec-gpio-v2"; 223 reg = < 0x40081000 0x80 0x40081300 0x04 224 0x40081380 0x04 0x400813fc 0x04>; 225 interrupts = <3 2>; 226 gpio-controller; 227 port-id = <0>; 228 girq-id = <11>; 229 #gpio-cells=<2>; 230 }; 231 gpio_040_076: gpio@40081080 { 232 compatible = "microchip,xec-gpio-v2"; 233 reg = < 0x40081080 0x80 0x40081304 0x04 234 0x40081384 0x04 0x400813f8 0x4>; 235 interrupts = <2 2>; 236 gpio-controller; 237 port-id = <1>; 238 girq-id = <10>; 239 #gpio-cells=<2>; 240 }; 241 gpio_100_136: gpio@40081100 { 242 compatible = "microchip,xec-gpio-v2"; 243 reg = < 0x40081100 0x80 0x40081308 0x04 244 0x40081388 0x04 0x400813f4 0x04>; 245 gpio-controller; 246 interrupts = <1 2>; 247 port-id = <2>; 248 girq-id = <9>; 249 #gpio-cells=<2>; 250 }; 251 gpio_140_176: gpio@40081180 { 252 compatible = "microchip,xec-gpio-v2"; 253 reg = < 0x40081180 0x80 0x4008130c 0x04 254 0x4008138c 0x04 0x400813f0 0x04>; 255 gpio-controller; 256 interrupts = <0 2>; 257 port-id = <3>; 258 girq-id = <8>; 259 #gpio-cells=<2>; 260 }; 261 gpio_200_236: gpio@40081200 { 262 compatible = "microchip,xec-gpio-v2"; 263 reg = < 0x40081200 0x80 0x40081310 0x04 264 0x40081390 0x04 0x400813ec 0x04>; 265 gpio-controller; 266 interrupts = <4 2>; 267 port-id = <4>; 268 girq-id = <12>; 269 #gpio-cells=<2>; 270 }; 271 gpio_240_276: gpio@40081280 { 272 compatible = "microchip,xec-gpio-v2"; 273 reg = < 0x40081280 0x80 0x40081314 0x04 274 0x40081394 0x04 0x400813e8 0x04>; 275 gpio-controller; 276 interrupts = <17 2>; 277 port-id = <5>; 278 girq-id = <26>; 279 #gpio-cells=<2>; 280 }; 281}; 282wdog: watchdog@40000400 { 283 compatible = "microchip,xec-watchdog"; 284 reg = <0x40000400 0x400>; 285 interrupts = <171 0>; 286 girqs = <21 2>; 287 pcrs = <1 9>; 288}; 289rtimer: timer@40007400 { 290 compatible = "microchip,xec-rtos-timer"; 291 reg = <0x40007400 0x10>; 292 interrupts = <111 0>; 293 girqs = <23 10>; 294}; 295timer0: timer@40000c00 { 296 compatible = "microchip,xec-timer"; 297 clock-frequency = <48000000>; 298 reg = <0x40000c00 0x20>; 299 interrupts = <136 0>; 300 girqs = <23 0>; 301 pcrs = <1 30>; 302 max-value = <0xFFFF>; 303 prescaler = <0>; 304 status = "disabled"; 305}; 306timer1: timer@40000c20 { 307 compatible = "microchip,xec-timer"; 308 clock-frequency = <48000000>; 309 reg = <0x40000c20 0x20>; 310 interrupts = <137 0>; 311 girqs = <23 1>; 312 pcrs = <1 31>; 313 max-value = <0xFFFF>; 314 prescaler = <0>; 315 status = "disabled"; 316}; 317timer2: timer@40000c40 { 318 compatible = "microchip,xec-timer"; 319 clock-frequency = <48000000>; 320 reg = <0x40000c40 0x20>; 321 interrupts = <138 0>; 322 girqs = <23 2>; 323 pcrs = <3 21>; 324 max-value = <0xFFFF>; 325 prescaler = <0>; 326 status = "disabled"; 327}; 328timer3: timer@40000c60 { 329 compatible = "microchip,xec-timer"; 330 clock-frequency = <48000000>; 331 reg = <0x40000c60 0x20>; 332 interrupts = <139 0>; 333 girqs = <23 3>; 334 pcrs = <3 22>; 335 max-value = <0xFFFF>; 336 prescaler = <0>; 337 status = "disabled"; 338}; 339/* 340 * NOTE: When RTOS timer used as kernel timer, timer4 used 341 * to provide high speed busy wait counter. Keep disabled to 342 * prevent counter driver from claiming it. 343 */ 344timer4: timer@40000c80 { 345 compatible = "microchip,xec-timer"; 346 clock-frequency = <48000000>; 347 reg = <0x40000c80 0x20>; 348 interrupts = <140 0>; 349 girqs = <23 4>; 350 pcrs = <3 23>; 351 max-value = <0xFFFFFFFF>; 352 prescaler = <0>; 353 status = "disabled"; 354}; 355timer5: timer@40000ca0 { 356 compatible = "microchip,xec-timer"; 357 clock-frequency = <48000000>; 358 reg = <0x40000ca0 0x20>; 359 interrupts = <141 0>; 360 girqs = <23 5>; 361 pcrs = <3 24>; 362 max-value = <0xFFFFFFFF>; 363 prescaler = <0>; 364 status = "disabled"; 365}; 366cntr0: timer@40000d00 { 367 reg = <0x40000d00 0x20>; 368 interrupts = <142 0>; 369 girqs = <23 6>; 370 pcrs = <4 2>; 371 status = "disabled"; 372}; 373cntr1: timer@40000d20 { 374 reg = <0x40000d20 0x20>; 375 interrupts = <143 0>; 376 girqs = <23 7>; 377 pcrs = <4 3>; 378 status = "disabled"; 379}; 380cntr2: timer@40000d40 { 381 reg = <0x40000d40 0x20>; 382 interrupts = <144 0>; 383 girqs = <23 8>; 384 pcrs = <4 3>; 385 status = "disabled"; 386}; 387cntr3: timer@40000d60 { 388 reg = <0x40000d60 0x20>; 389 interrupts = <145 0>; 390 girqs = <23 9>; 391 pcrs = <4 4>; 392 status = "disabled"; 393}; 394cctmr0: timer@40001000 { 395 reg = <0x40001000 0x40>; 396 interrupts = <146 0>, <147 0>, <148 0>, <149 0>, 397 <150 0>, <151 0>, <152 0>, <153 0>, 398 <154 0>; 399 girqs = <18 20>, <18 21>, <18 22>, <18 23>, <18 24>, 400 <18 25>, <18 26>, <18 27>, <18 28>; 401 pcrs = <3 30>; 402 status = "disabled"; 403}; 404hibtimer0: timer@40009800 { 405 reg = <0x40009800 0x20>; 406 interrupts = <112 0>; 407 girqs = <23 16>; 408}; 409hibtimer1: timer@40009820 { 410 reg = <0x40009820 0x20>; 411 interrupts = <113 0>; 412 girqs = <23 17>; 413}; 414weektmr0: timer@4000ac80 { 415 reg = <0x4000ac80 0x80>; 416 interrupts = <114 0>, <115 0>, <116 0>, 417 <117 0>, <118 0>; 418 girqs = <21 3>, <21 4>, <21 5>, <21 6>, <21 7>; 419 status = "disabled"; 420}; 421bbram: bb-ram@4000a800 { 422 compatible = "microchip,xec-bbram"; 423 reg = <0x4000a800 0x100>; 424 reg-names = "memory"; 425}; 426vci0: vci@4000ae00 { 427 reg = <0x4000ae00 0x40>; 428 interrupts = <121 0>, <122 0>, <123 0>, 429 <124 0>, <125 0>; 430 girqs = <21 10>, <21 11>, <21 12>, <21 13>, <21 14>; 431 status = "disabled"; 432}; 433dmac: dmac@40002400 { 434 compatible = "microchip,xec-dmac"; 435 reg = <0x40002400 0xc00>; 436 interrupts = <24 1>, <25 1>, <26 1>, <27 1>, 437 <28 1>, <29 1>, <30 1>, <31 1>, 438 <32 1>, <33 1>, <34 1>, <35 1>, 439 <36 1>, <37 1>, <38 1>, <39 1>; 440 girqs = < MCHP_XEC_ECIA(14, 0, 6, 24) 441 MCHP_XEC_ECIA(14, 1, 6, 25) 442 MCHP_XEC_ECIA(14, 2, 6, 26) 443 MCHP_XEC_ECIA(14, 3, 6, 27) 444 MCHP_XEC_ECIA(14, 4, 6, 28) 445 MCHP_XEC_ECIA(14, 5, 6, 29) 446 MCHP_XEC_ECIA(14, 6, 6, 30) 447 MCHP_XEC_ECIA(14, 7, 6, 31) 448 MCHP_XEC_ECIA(14, 8, 6, 32) 449 MCHP_XEC_ECIA(14, 9, 6, 33) 450 MCHP_XEC_ECIA(14, 10, 6, 34) 451 MCHP_XEC_ECIA(14, 11, 6, 35) 452 MCHP_XEC_ECIA(14, 12, 6, 36) 453 MCHP_XEC_ECIA(14, 13, 6, 37) 454 MCHP_XEC_ECIA(14, 14, 6, 38) 455 MCHP_XEC_ECIA(14, 15, 6, 39) >; 456 pcrs = <1 6>; 457 #dma-cells = <2>; 458 dma-channels = <16>; 459 dma-requests = <16>; 460 status = "disabled"; 461}; 462i2c_smb_0: i2c@40004000 { 463 compatible = "microchip,xec-i2c-v2"; 464 reg = <0x40004000 0x80>; 465 clock-frequency = <I2C_BITRATE_STANDARD>; 466 interrupts = <20 1>; 467 girqs = <13 0>; 468 pcrs = <1 10>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 status = "disabled"; 472}; 473i2c_smb_1: i2c@40004400 { 474 compatible = "microchip,xec-i2c-v2"; 475 reg = <0x40004400 0x80>; 476 clock-frequency = <I2C_BITRATE_STANDARD>; 477 interrupts = <21 1>; 478 girqs = <13 1>; 479 pcrs = <3 13>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483}; 484i2c_smb_2: i2c@40004800 { 485 compatible = "microchip,xec-i2c-v2"; 486 reg = <0x40004800 0x80>; 487 clock-frequency = <I2C_BITRATE_STANDARD>; 488 interrupts = <22 1>; 489 girqs = <13 2>; 490 pcrs = <3 14>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494}; 495i2c_smb_3: i2c@40004c00 { 496 compatible = "microchip,xec-i2c-v2"; 497 reg = <0x40004C00 0x80>; 498 clock-frequency = <I2C_BITRATE_STANDARD>; 499 interrupts = <23 1>; 500 girqs = <13 3>; 501 pcrs = <3 15>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505}; 506i2c_smb_4: i2c@40005000 { 507 compatible = "microchip,xec-i2c-v2"; 508 reg = <0x40005000 0x80>; 509 clock-frequency = <I2C_BITRATE_STANDARD>; 510 interrupts = <158 1>; 511 girqs = <13 4>; 512 pcrs = <3 20>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 status = "disabled"; 516}; 517ps2_0: ps2@40009000 { 518 compatible = "microchip,xec-ps2"; 519 reg = <0x40009000 0x40>; 520 interrupts = <100 1>; 521 girqs = <18 10>, <21 18>; 522 pcrs = <3 5>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526}; 527pwm0: pwm@40005800 { 528 compatible = "microchip,xec-pwm"; 529 reg = <0x40005800 0x20>; 530 pcrs = <1 4>; 531 status = "disabled"; 532 #pwm-cells = <3>; 533}; 534pwm1: pwm@40005810 { 535 compatible = "microchip,xec-pwm"; 536 reg = <0x40005810 0x20>; 537 pcrs = <1 20>; 538 status = "disabled"; 539 #pwm-cells = <3>; 540}; 541pwm2: pwm@40005820 { 542 compatible = "microchip,xec-pwm"; 543 reg = <0x40005820 0x20>; 544 pcrs = <1 21>; 545 status = "disabled"; 546 #pwm-cells = <3>; 547}; 548pwm3: pwm@40005830 { 549 compatible = "microchip,xec-pwm"; 550 reg = <0x40005830 0x20>; 551 pcrs = <1 22>; 552 status = "disabled"; 553 #pwm-cells = <3>; 554}; 555pwm4: pwm@40005840 { 556 compatible = "microchip,xec-pwm"; 557 reg = <0x40005840 0x20>; 558 pcrs = <1 23>; 559 status = "disabled"; 560 #pwm-cells = <3>; 561}; 562pwm5: pwm@40005850 { 563 compatible = "microchip,xec-pwm"; 564 reg = <0x40005850 0x20>; 565 pcrs = <1 24>; 566 status = "disabled"; 567 #pwm-cells = <3>; 568}; 569pwm6: pwm@40005860 { 570 compatible = "microchip,xec-pwm"; 571 reg = <0x40005860 0x20>; 572 pcrs = <1 25>; 573 status = "disabled"; 574 #pwm-cells = <3>; 575}; 576pwm7: pwm@40005870 { 577 compatible = "microchip,xec-pwm"; 578 reg = <0x40005870 0x20>; 579 pcrs = <1 26>; 580 status = "disabled"; 581 #pwm-cells = <3>; 582}; 583pwm8: pwm@40005880 { 584 compatible = "microchip,xec-pwm"; 585 reg = <0x40005880 0x20>; 586 pcrs = <1 27>; 587 status = "disabled"; 588 #pwm-cells = <3>; 589}; 590tach0: tach@40006000 { 591 compatible = "microchip,xec-tach"; 592 reg = <0x40006000 0x10>; 593 interrupts = <71 4>; 594 girqs = <17 1>; 595 pcrs = <1 2>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599}; 600tach1: tach@40006010 { 601 compatible = "microchip,xec-tach"; 602 reg = <0x40006010 0x10>; 603 interrupts = <72 4>; 604 girqs = <17 2>; 605 pcrs = <1 11>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609}; 610tach2: tach@40006020 { 611 compatible = "microchip,xec-tach"; 612 reg = <0x40006020 0x10>; 613 interrupts = <73 4>; 614 girqs = <17 3>; 615 pcrs = <1 12>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619}; 620tach3: tach@40006030 { 621 compatible = "microchip,xec-tach"; 622 reg = <0x40006030 0x10>; 623 interrupts = <159 4>; 624 girqs = <17 4>; 625 pcrs = <1 13>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629}; 630rpmfan0: rpmfan@4000a000 { 631 reg = <0x4000a000 0x80>; 632 interrupts = <74 1>, <75 1>; 633 girqs = <17 20>, <17 21>; 634 pcrs = <3 12>; 635 status = "disabled"; 636}; 637rpmfan1: rpmfan@4000a080 { 638 reg = <0x4000a080 0x80>; 639 interrupts = <76 1>, <77 1>; 640 girqs = <17 22>, <17 23>; 641 pcrs = <4 7>; 642 status = "disabled"; 643}; 644adc0: adc@40007c00 { 645 compatible = "microchip,xec-adc"; 646 reg = <0x40007c00 0x90>; 647 interrupts = <78 0>, <79 0>; 648 girqs = <17 8>, <17 9>; 649 pcrs = <3 3>; 650 status = "disabled"; 651 #io-channel-cells = <1>; 652 clktime = <32>; 653}; 654kbd0: kbd@40009c00 { 655 compatible = "microchip,xec-kbd"; 656 reg = <0x40009c00 0x18>; 657 interrupts = <135 0>; 658 girqs = <21 25>; 659 pcrs = <3 11>; 660 status = "disabled"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663}; 664peci0: peci@40006400 { 665 compatible = "microchip,xec-peci"; 666 reg = <0x40006400 0x80>; 667 interrupts = <70 4>; 668 girqs = <17 0>; 669 pcrs = <1 1>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672}; 673spi0: spi@40070000 { 674 reg = <0x40070000 0x400>; 675 interrupts = <91 2>; 676 girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >; 677 clocks = <&pcr 4 8 MCHP_XEC_PCR_CLK_PERIPH>; 678 clock-frequency = <12000000>; 679 lines = <1>; 680 chip-select = <0>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 status = "disabled"; 684}; 685spi1: spi@40009400 { 686 reg = <0x40009400 0x80>; 687 interrupts = <92 2>, <93 2>; 688 girqs = <18 2>, <18 3>; 689 pcrs = <3 9>; 690 status = "disabled"; 691}; 692spi2: spi@40009480 { 693 reg = <0x40009480 0x80>; 694 interrupts = <94 2>, <95 2>; 695 girqs = <18 4>, <18 5>; 696 pcrs = <4 22>; 697 status = "disabled"; 698}; 699prochot0: prochot@40003400 { 700 reg = <0x40003400 0x20>; 701 interrupts = <87 0>; 702 girqs = <17 17>; 703 pcrs = <4 13>; 704 status = "disabled"; 705}; 706rcid0: rcid@40001400 { 707 reg = <0x40001400 0x80>; 708 interrupts = <80 0>; 709 girqs = <17 10>; 710 pcrs = <4 10>; 711 status = "disabled"; 712}; 713rcid1: rcid@40001480 { 714 reg = <0x40001480 0x80>; 715 interrupts = <81 0>; 716 girqs = <17 11>; 717 pcrs = <4 11>; 718 status = "disabled"; 719}; 720rcid2: rcid@40001500 { 721 reg = <0x40001500 0x80>; 722 interrupts = <82 0>; 723 girqs = <17 12>; 724 pcrs = <4 12>; 725 status = "disabled"; 726}; 727spip0: spip@40007000 { 728 reg = <0x40007000 0x100>; 729 interrupts = <90 0>; 730 girqs = <18 0>; 731 pcrs = <4 16>; 732 status = "disabled"; 733}; 734bbled0: bbled@4000b800 { 735 reg = <0x4000b800 0x100>; 736 interrupts = <83 0>; 737 girqs = <17 13>; 738 pcrs = <3 16>; 739 status = "disabled"; 740}; 741bbled1: bbled@4000b900 { 742 reg = <0x4000b900 0x100>; 743 interrupts = <84 0>; 744 girqs = <17 14>; 745 pcrs = <3 17>; 746 status = "disabled"; 747}; 748bbled2: bbled@4000ba00 { 749 reg = <0x4000ba00 0x100>; 750 interrupts = <85 0>; 751 girqs = <17 15>; 752 pcrs = <3 18>; 753 status = "disabled"; 754}; 755bbled3: bbled@4000bb00 { 756 reg = <0x4000bb00 0x100>; 757 interrupts = <86 0>; 758 girqs = <17 16>; 759 pcrs = <3 25>; 760 status = "disabled"; 761}; 762bclink0: bclink@4000cd00 { 763 reg = <0x4000cd00 0x20>; 764 interrupts = <96 0>, <97 0>; 765 girqs = <18 7>, <18 6>; 766 pcrs = <3 19>; 767 status = "disabled"; 768}; 769tfdp0: tfdp@40008c00 { 770 reg = <0x40008c00 0x10>; 771 pcrs = <1 7>; 772 status = "disabled"; 773}; 774glblcfg0: glblcfg@400fff00 { 775 reg = <0x400fff00 0x40>; 776 pcrs = <2 12>; 777 status = "disabled"; 778}; 779uart0: uart@400f2400 { 780 compatible = "microchip,xec-uart"; 781 reg = <0x400f2400 0x400>; 782 interrupts = <40 1>; 783 clock-frequency = <1843200>; 784 current-speed = <38400>; 785 girqs = <15 0>; 786 pcrs = <2 1>; 787 ldn = <9>; 788 status = "disabled"; 789}; 790uart1: uart@400f2800 { 791 compatible = "microchip,xec-uart"; 792 reg = <0x400f2800 0x400>; 793 interrupts = <41 1>; 794 clock-frequency = <1843200>; 795 current-speed = <38400>; 796 girqs = <15 1>; 797 pcrs = <2 2>; 798 ldn = <10>; 799 status = "disabled"; 800}; 801espi0: espi@400f3400 { 802 compatible = "microchip,xec-espi-v2"; 803 /* reg tuple contains one 32-bit address cell and one 804 * 32-bit length(size) cell. 805 */ 806 #address-cells = <1>; 807 #size-cells = <1>; 808 reg = < 0x400f3400 0x400 809 0x400f3800 0x400 810 0x400f9c00 0x400>; 811 reg-names = "io", "mem", "vw"; 812 interrupts = <103 3>, <104 3>, <105 3>, <106 3>, 813 <107 3>, <108 3>, <109 3>, <110 2>, 814 <156 3>; 815 interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up", 816 "oob_dn", "fc", "rst", "vw_chan_en"; 817 girqs = < MCHP_XEC_ECIA(19, 0, 11, 103) 818 MCHP_XEC_ECIA(19, 1, 11, 104) 819 MCHP_XEC_ECIA(19, 2, 11, 105) 820 MCHP_XEC_ECIA(19, 3, 11, 106) 821 MCHP_XEC_ECIA(19, 4, 11, 107) 822 MCHP_XEC_ECIA(19, 5, 11, 108) 823 MCHP_XEC_ECIA(19, 6, 11, 109) 824 MCHP_XEC_ECIA(19, 7, 11, 110) 825 MCHP_XEC_ECIA(19, 8, 11, 156) >; 826 pcrs = <2 19>; 827 status = "disabled"; 828 829 espi_saf0: espi_saf@40008000 { 830 compatible = "microchip,xec-espi-saf-v2"; 831 reg = <0x40008000 0x400>, <0x40070000 0x400>, 832 <0x40071000 0x400>; 833 reg-names = "safbr", "safqspi", "safcomm"; 834 interrupts = <166 3>, <167 3>; 835 interrupt-names = "done", "err"; 836 girqs = < MCHP_XEC_ECIA(19, 9, 11, 166) >, 837 < MCHP_XEC_ECIA(19, 10, 11, 167) >; 838 pcrs = <2 27>; 839 status = "disabled"; 840 }; 841 842 mbox0: mbox@400f0000 { 843 compatible = "microchip,xec-espi-host-dev"; 844 reg = <0x400f0000 0x200>; 845 interrupts = <60 3>; 846 girqs = < MCHP_XEC_ECIA(15, 20, 7, 60) >; 847 pcrs = <2 17>; 848 ldn = <0>; 849 status = "disabled"; 850 }; 851 kbc0: kbc@400f0400 { 852 compatible = "microchip,xec-espi-host-dev"; 853 reg = <0x400f0400 0x400>; 854 interrupts = <58 3>, <59 3>; 855 interrupt-names = "kbc_obe", "kbc_ibf"; 856 girqs = < MCHP_XEC_ECIA(15, 18, 7, 58) 857 MCHP_XEC_ECIA(15, 19, 7, 59) >; 858 ldn = <1>; 859 status = "disabled"; 860 }; 861 acpi_ec0: acpi_ec@400f0800 { 862 compatible = "microchip,xec-espi-host-dev"; 863 reg = <0x400f0800 0x400>; 864 interrupts = <45 3>, <46 3>; 865 interrupt-names = "acpi_ibf", "acpi_obe"; 866 girqs = < MCHP_XEC_ECIA(15, 5, 7, 45) 867 MCHP_XEC_ECIA(15, 6, 7, 46) >; 868 ldn = <2>; 869 status = "disabled"; 870 }; 871 acpi_ec1: acpi_ec@400f0c00 { 872 compatible = "microchip,xec-espi-host-dev"; 873 reg = <0x400f0c00 0x400>; 874 interrupts = <47 3>, <48 3>; 875 interrupt-names = "acpi_ibf", "acpi_obe"; 876 girqs = < MCHP_XEC_ECIA(15, 7, 7, 47) 877 MCHP_XEC_ECIA(15, 8, 7, 48) >; 878 ldn = <3>; 879 status = "disabled"; 880 }; 881 acpi_ec2: acpi_ec@400f1000 { 882 compatible = "microchip,xec-espi-host-dev"; 883 reg = <0x400f1000 0x400>; 884 interrupts = <49 3>, <50 3>; 885 interrupt-names = "acpi_ibf", "acpi_obe"; 886 girqs = < MCHP_XEC_ECIA(15, 9, 7, 49) 887 MCHP_XEC_ECIA(15, 10, 7, 50) >; 888 ldn = <4>; 889 status = "disabled"; 890 }; 891 acpi_ec3: acpi_ec@400f1400 { 892 compatible = "microchip,xec-espi-host-dev"; 893 reg = <0x400f1400 0x400>; 894 interrupts = <51 3>, <52 3>; 895 interrupt-names = "acpi_ibf", "acpi_obe"; 896 girqs = < MCHP_XEC_ECIA(15, 11, 7, 51) 897 MCHP_XEC_ECIA(15, 12, 7, 52) >; 898 ldn = <5>; 899 status = "disabled"; 900 }; 901 acpi_ec4: acpi_ec@400f1800 { 902 compatible = "microchip,xec-espi-host-dev"; 903 reg = <0x400f1800 0x400>; 904 interrupts = <53 3>, <54 3>; 905 interrupt-names = "acpi_ibf", "acpi_obe"; 906 girqs = < MCHP_XEC_ECIA(15, 13, 7, 53) 907 MCHP_XEC_ECIA(15, 14, 7, 54) >; 908 ldn = <6>; 909 status = "disabled"; 910 }; 911 acpi_pm1: acpi_pm1@400f1c00 { 912 compatible = "microchip,xec-espi-host-dev"; 913 reg = <0x400f1c00 0x400>; 914 interrupts = <55 3>, <56 3>, <57 3>; 915 interrupt-names = "pm1_ctl", "pm1_en", "pm1_sts"; 916 girqs = < MCHP_XEC_ECIA(15, 15, 7, 55) 917 MCHP_XEC_ECIA(15, 16, 7, 56) 918 MCHP_XEC_ECIA(15, 17, 7, 57) >; 919 ldn = <7>; 920 status = "disabled"; 921 }; 922 port92: port92@400f2000 { 923 compatible = "microchip,xec-espi-host-dev"; 924 reg = <0x400f2000 0x400>; 925 ldn = <8>; 926 status = "disabled"; 927 }; 928 emi0: emi@400f4000 { 929 compatible = "microchip,xec-espi-host-dev"; 930 reg = <0x400f4000 0x400>; 931 interrupts = <42 3>; 932 girqs = < MCHP_XEC_ECIA(15, 2, 7, 42) >; 933 ldn = <16>; 934 status = "disabled"; 935 }; 936 emi1: emi@400f4400 { 937 compatible = "microchip,xec-espi-host-dev"; 938 reg = <0x400f4400 0x400>; 939 interrupts = <43 3>; 940 girqs = < MCHP_XEC_ECIA(15, 3, 7, 43) >; 941 ldn = <17>; 942 status = "disabled"; 943 }; 944 emi2: emi@400f4800 { 945 compatible = "microchip,xec-espi-host-dev"; 946 reg = <0x400f4800 0x400>; 947 interrupts = <44 3>; 948 girqs = < MCHP_XEC_ECIA(15, 4, 7, 44) >; 949 ldn = <18>; 950 status = "disabled"; 951 }; 952 rtc0: rtc@400f5000 { 953 compatible = "microchip,xec-espi-host-dev"; 954 reg = <0x400f5000 0x100>; 955 interrupts = <119 3>, <120 3>; 956 girqs = < MCHP_XEC_ECIA(21, 8, 13, 119) 957 MCHP_XEC_ECIA(21, 9, 13, 120) >; 958 pcrs = <2 18>; 959 ldn = <20>; 960 status = "disabled"; 961 }; 962 /* Capture writes to host I/O 0x80 - 0x83 */ 963 p80bd0: p80bd@400f8000 { 964 compatible = "microchip,xec-espi-host-dev"; 965 reg = <0x400f8000 0x400>; 966 interrupts = <62 0>; 967 girqs = < MCHP_XEC_ECIA(15, 22, 7, 62) >; 968 pcrs = <2 25>; 969 ldn = <32>; 970 status = "disabled"; 971 }; 972 /* Capture writes to an 8-bit I/O and map to one of 0x80 to 0x83 */ 973 p80bd0_alias: p80bd@400f8400 { 974 compatible = "microchip,xec-espi-host-dev"; 975 reg = <0x400f8400 0x400>; 976 ldn = <33>; 977 host-io = <0x90>; 978 /* map 0x90 to 0x80 */ 979 host-io-addr-mask = <0x01>; 980 status = "disabled"; 981 }; 982}; 983 984symcr: symcr@40100000 { 985 compatible = "microchip,xec-symcr"; 986 reg = <0x40100000 0x1000>; 987 interrupts = <68 1>; 988 clocks = <&pcr 3 26 MCHP_XEC_PCR_CLK_PERIPH>; 989 girqs = <16 3>; 990 status = "disabled"; 991 #address-cells = <1>; 992 #size-cells = <1>; 993}; 994 995rom_api: rom_api@1f000 { 996 reg = <0x1f000 0x1000>; 997 status = "disabled"; 998}; 999
