1 /* 2 * Copyright (c) 2025 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __INTEL_DRIVER_MIC_PRIVACY_REGISTERS_H__ 8 #define __INTEL_DRIVER_MIC_PRIVACY_REGISTERS_H__ 9 10 #include <stdint.h> 11 #include <zephyr/arch/cpu.h> 12 #include <zephyr/arch/common/sys_io.h> 13 14 /** 15 * DFMICPVCP 16 * Microphone Privacy Policy 17 * 18 * Offset: 00h 19 * Block: DfMICPVC 20 * 21 * This register controls the microphone privacy DMA data zeroing feature HW policy. 22 */ 23 union DFMICPVCP { 24 uint32_t full; 25 struct { 26 /** 27 * DMA Data Zeroing Wait Time 28 * type: RW/L, rst: 0b, rst domain: PLTRST 29 * 30 * Indicates the time-out duration to wait before forcing the actual 31 * microphone privacy DMA data zeroing. Unit in number of RTC clocks. 32 * Valid and static when DDZE = 10. For DDZE = 0x or 11 case, time-out 33 * is not necessary as it will not be enabled or force mic disable statically. 34 * Locked when DDZPL = 1. 35 */ 36 uint32_t ddzwt : 16; 37 /** 38 * DMA Data Zeroing Enable 39 * type: RW/L, rst: 00b, rst domain: PLTRST 40 * 41 * Indicates the policy setting for HW to force the microphone privacy DMA data zeroing. 42 * 0x: Disabled 43 * 10: Enabled (mic disable dynamically depending on privacy signaling input) 44 * 11: Enabled (force mic disable statically) 45 * Locked when DDZPL = 1. 46 */ 47 uint32_t ddze : 2; 48 /** 49 * De-glitcher Enable 50 * type: RW/L, rst: 0b, rst domain: PLTRST 51 * 52 * De-glitcher enable for privacy signaling GPIO input running on resume clock domain. 53 * Locked when DDZPL = 1. 54 */ 55 uint32_t dge : 1; 56 /** 57 * DMA Data Zeroing Policy Lock 58 * type: RW/L, rst: 0b, rst domain: PLTRST 59 * 60 * When set to 1, it locks the privacy DMA data zeroing policy setting. 61 */ 62 uint32_t ddzpl : 1; 63 64 /** 65 * DMA Data Zeroing Link Select 66 * type: RW/L, rst: 0b, rst domain: PLTRST 67 * 68 * Select 1 or more audio link to apply the microphone privacy DMA data zeroing. 69 * 1 bit per audio link. 70 * [6:0]: SoundWire link segment 71 * [7]: DMIC 72 * Valid and static when DDZE = 1. 73 * Locked when DDZPL = 1. 74 */ 75 uint32_t ddzls : 8; 76 /** 77 * Reserved (Preserved) 78 * type: RO, rst: 000 0000h, rst domain: nan 79 * 80 * SW must preserve the original value when writing. 81 */ 82 uint32_t rsvd31 : 4; 83 } part; 84 }; 85 86 /** 87 * DFMICPVCS 88 * Microphone Privacy Status 89 * 90 * Offset: 04h 91 * Block: DfMICPVC 92 * 93 * This register reports the microphone privacy DMA data zeroing status. 94 */ 95 union DFMICPVCS { 96 uint16_t full; 97 struct { 98 /** 99 * Mic Disabled Indicator Output 100 * type: RO/V, rst: 0b, rst domain: nan 101 * 102 * Indicates the mic disabled status output to GPIO (i.e. the privacy 103 * indicator output). 104 */ 105 uint16_t mdio : 1; 106 /** 107 * Reserved (Zero) 108 * type: RO, rst: 0000h, rst domain: nan 109 * 110 * SW must use zeros for writes. 111 */ 112 uint16_t rsvd15 : 15; 113 } part; 114 }; 115 116 /** 117 * DFFWMICPVCCS 118 * FW Microphone Privacy Control & Status 119 * 120 * Offset: 06h 121 * Block: DfMICPVC 122 * 123 * This register allows DSP FW to manage the mic privacy operation (if not locked by trusted host). 124 */ 125 union DFFWMICPVCCS { 126 uint16_t full; 127 struct { 128 /** 129 * Mic Disable Status Changed Interrupt Enabled 130 * type: RW, rst: 0b, rst domain: DSPLRST 131 * 132 * When set to 1, it allows MDSTSCHG bit to be propagated as mic privacy interrupt 133 * to the DSP Cores. 134 */ 135 uint16_t mdstschgie : 1; 136 /** 137 * FW Managed Mic Disable 138 * type: RW/L, rst: 0b, rst domain: DSPLRST 139 * 140 * When set to 1, it indicates FW will manage its own time-out, decide which related link 141 * DMA should zero out the data (through DGLISxCS.DDZ), and update the privacy signaling 142 * output (through FMDSTS). 143 * HW will NOT control any of the DMIC / SoundWire link level DMA data zeroing or privacy 144 * signaling output in this case. Locked when DfMICPVCCGP. DDZPL = 1. 145 */ 146 uint16_t fmmd : 1; 147 /** 148 * FW Mic Disable Status 149 * type: RW, rst: 0b, rst domain: DSPLRST 150 * 151 * When set to 1, it indicates FW has quiesced the mic input stream gracefully and 152 * instructs HW to set privacy indicator output (no dependency on privacy 153 * signaling input). Valid if FMMD = 1. 154 */ 155 uint16_t fmdsts : 1; 156 /** 157 * Reserved (Preserved) 158 * type: RO, rst: 00h, rst domain: nan 159 * 160 * SW must preserve the original value when writing. 161 */ 162 uint16_t rsvd7 : 5; 163 /** 164 * Mic Disable Status Changed 165 * type: RW/1C, rst: 0b, rst domain: DSPLRST 166 * 167 * Asserted when mic disable status has changed state (independent of MDSTSCHGIE setting), 168 * and trigger interrupt if enabled. 169 * 170 * Note: If MDSTS change again before the current MDSTSCHG is acknowledged by DSP FW, 171 * the bit will still remain set until cleared by DSP FW. 172 */ 173 uint16_t mdstschg : 1; 174 /** 175 * Mic Disable Status 176 * type: RO/V, rst: 0b, rst domain: nan 177 * 178 * Indicates the live mic disable status input from GPIO (if FMMD = 1). When asserted and 179 * the microphone privacy DMA data zeroing policy is enabled, FW will manage its 180 * own time-out and decide which related link DMA should zero out the data 181 * (DGLISxCS.DDZ = 1), followed by setting the mic privacy indicator output (FMDSTS = 1). 182 * When de-asserted, FW should remove the DMA data zeroing (DGLISxCS.DDZ = 0) and clear 183 * the privacy indicator output (FMDSTS = 0) as soon as possible. 184 */ 185 uint16_t mdsts : 1; 186 /** 187 * Reserved (Preserved) 188 * type: RO, rst: 00h, rst domain: nan 189 * 190 * SW must preserve the original value when writing. 191 */ 192 uint16_t rsvd15 : 6; 193 } part; 194 }; 195 196 /** 197 * DMICXPVCCS 198 * Digital Microphone x Privacy Control & Status 199 * 200 * Offset: 10h 201 * Block: DMICVSSX_AON 202 * 203 * This register controls the status reporting structure of the microphone privacy DMA data 204 * zeroing feature. 205 */ 206 union DMICXPVCCS { 207 uint16_t full; 208 struct { 209 /** 210 * Mic Disable Status Changed Interrupt Enabled 211 * type: RW, rst: 0h, rst domain: FLR 212 * 213 * When set to 1, it allows MDSTSCHG bit to be propagated as DMIC 214 * / SoundWire interrupt to the DSP Cores / host CPU. 215 */ 216 uint16_t mdstschgie : 1; 217 /** 218 * Reserved 219 * type: RO, rst: 00h, rst domain: N/A 220 */ 221 uint16_t rsvd7 : 7; 222 /** 223 * Mic Disable Status Changed 224 * type: RW/1C, rst: 0h, rst domain: FLR 225 * 226 * Asserted when mic disable status has changed state (independent of MDSTSCHGIE 227 * setting), and trigger interrupt if enabled. 228 * Note: If MDSTS change again before the current MDSTSCHG is acknowledged by 229 * DSP FW / host SW, the bit will still remain set until cleared by 230 * DSP FW / host SW. 231 */ 232 uint16_t mdstschg: 1; 233 /** 234 * Mic Disable Status 235 * type: RO/V, rst: 0h, rst domain: N/A 236 * 237 * Indicates the live mic disable status input from GPIO 238 * (for the selected mic audio link per DFMICPVCP.DDZLS). 239 * When asserted and the microphone privacy DMA data zeroing policy is enabled, 240 * the timer will start counting and force the selected mic data to zero 241 * (after time-out). When de-asserted, 242 * it remove the DMA data zeroing immediately (including stopping the timer 243 * if it has not expired). 244 */ 245 uint16_t mdsts: 1; 246 /** 247 * Force Mic Disable 248 * type: RO/V, rst: 0h, rst domain: N/A 249 * 250 * Indicates the microphone endpoint 251 * (for the selected mic audio link per DFMICPVCP.DDZLS) 252 * is statically force mic disable by trusted agent and SW / FW should hide 253 * the endpoint from being exposed to OS. 254 */ 255 uint16_t fmdis: 1; 256 /** 257 * Reserved 258 * type: RO, rst: 00h, rst domain: N/A 259 */ 260 uint16_t rsvd15: 5; 261 } part; 262 }; 263 #endif /* __INTEL_DAI_DRIVER_MIC_PRIVACY_REGISTERS_H__ */ 264
